Download Presentation





Overview of current memory technologies :
› DRAM, SRAM, Flash memory etc.
› Limitations of the above
Need for new memory technologies
› Resistive memory devices
 PCRAM, MRAM, CBRAM, Organic memory etc.
Comparison of the technologies
Summary
2
Memories are used to store digital values. These are the data
storage units of any processor; used extensively in almost ALL
electronic devices
 Divided into large number of CELLS – each cell stores 1 bit of data in
the digital form (HIGH or LOW)
 Desirable characteristics:
› Fast access, read and write operations
› Large storage density (i.e. small size)
› Preferably non-volatile
› High retention
› Cheap / easy to produce in large numbers
› High endurance

3

MOSFET based memory devices :
› Volatile memory: Data is stored only as long as the memory cell is
powered.
› Examples:
 Static RAM (SRAM)
 Dynamic RAM (DRAM)
› Non-volatile memory: Data is stored even when powered off –
data is destroyed only when forcefully erased.
› Examples:
 Flash RAM
4






Uses one capacitor and one transistor per cell
Based on charge storage by capacitor and
switching action of the transistor
Presence/absence of charge is detected as LOW
and HIGH in digital logic
Cells are arranged in the form of a matrix, with
word lines connecting each row
The word lines control the transistor (which is operated as a switch)
› Reading: Done using the capacitor connected to the bit line;
destructive readout because of division of voltage across Cbl
and Cs
› Writing: Switch is closed and data is transferred through the bit
line
However, due to charge leakage across the capacitor, data
has to be continuously refreshed to prevent data loss
5
„Static‟ in the sense that data is stored until powered off
 Data reminiscence achieved through bi-stable
stable
latching circuitry
 CMOS technology used : 6 transistors per cell is
the most common configuration
› 4 transistors form a cross-coupled inverters;
› 2 transistors used for access during read write operations
 Operation:
Ref. [1]
› Standby: absence of data on the word line causes the access
transistors to cutoff access to M1 – M4 ; M1 – M4 reinforce each
other in the presence of the supply
› Writing: Data written using bit lines; similar to applying reset to an
SR latch
› Reading: Action of a differential sense amplifier

6
Floating gate electrode is used
 Charges stored in gate-oxide
oxide layer of transistor, causing changes in
the threshold voltage
 Considering an nMOS transistor:
› When the floating gate is filled with
electrons  logic 1 (HIGH)
› When the floating gate is uncharged
 logic 0 (LOW)
 Electrons cross the oxide by hot electron
injection or Nordheim tunneling

Ref. [2]
7
DRAM
• Cheap
• Large storage
density
• Large number of
read/write cycles
• Volatile memory
• Refreshing
required
• Slower than SRAM
SRAM
• No refreshing
required
• Better
performance than
DRAM
• Large number of
read/write cycles
• Costly
• Volatile memory
• More components
used per cell (low
density)
Flash memory
• Non-volatile
• Fast erasing of
data
• Relatively cheap,
nowadays
• Writing is slow
• Less number of
read/write cycles
8




Overview of current memory technologies :
› DRAM, SRAM, Flash memory etc.
› Limitations of the above
Need for new memory technologies
› Resistive memory devices
 PCRAM, MRAM, CBRAM, Organic memory etc.
Comparison of the technologies
Summary
9
The main problem faced: MOSFET down-scaling; channel length has
come down from 130 nm (2000) to 32 nm (current)
 Problems:
› Reduced chip speed (due to interconnects)
› Higher sub-threshold, more leakage
› Difficulty in prediction of operation
 Requirements:
› Small size (higher density)
› Low cost
› Low power consumption (to suit mobile devices)
› Non-volatile (high retention time)
 The solution:
› RESISTIVE MEMORY DEVICES!!!

10
As the name suggests, it‟s based on change in resistance by altering
certain parameters of the device
 Principle: dielectric can be made to conduct through a conduction
path on applying a sufficiently large voltage
 Tracking of change with respect to reference allows reading of data
 Non-volatile memory


Examples:
› Magneto-resistive RAM (MRAM)
› Phase change RAM (PRAM)
› Conductive bridge RAM (CBRAM)
› Ferroelectric RAM (FeRAM)
11





Principle: In ferromagnetic materials, motion of electron is
influenced by spin orientation w.r.t local magnetization
Stronger effect than spin conservation
Two effects:
› Giant magnetoresistance (GMR)
› Tunnel magnetoresistance (TMR)
Based on the fact that polarization doesn‟t leak away like charge
Each magnetic state offers different resistance; thereby enabling
distinction between HIGH and LOW states
12







Two layers of ferromagnetic plates used:
› One is magnetically pinned down, i.e. set to a certain
polarization – called hard layer
› Other layer‟s magnetization can rotate (called soft layer)
Zero field  layers align anti-parallel
Sufficiently large field  layers align parallel
Spin dependent reflectivity is responsible for electrical resistance
Only the states near the Fermi energy can contribute to conductivity
- they can reach the empty states above Fermi energy after some
scattering event
Anti-parallel alignment  large resistance (Rap)
Parallel alignment  small resistance (Rp)
13

Figure illustrating the
GMR effect; resistance
in the parallel and antiantiparallel configurations
Ref. [3]
14







Observed when two thin film electrodes (ferromagnetic) are
separated by an insulating / semiconducting barrier (generally AlOx)
Spin is conserved during tunneling (barrier thickness ~ spin diffusion
length)
Initially spin-up electron tunnels to a spin-up state
TMR arises due to difference in spin-up and spin-down electrons
Value of resistance depends on relative magnetization on both
sides of the layer
TMR ~ 40% to 50% (observed)
Implementation using Magnetic
Tunnel Junction (MTJ)
15
Cell : Magnetic tunnel junction (MTJ)
 TMR is used as it has higher value of magnetoresistance
 Top layer  reverses easily under applied field
› Negative field  free layer becomes anti-parallel to the fixed
CoFe layer  high resistance
› Positive field  free layer becomes parallel to the fixed CoFe
layer  low resistance
 Even in the absence of field, state is retained unless reverse field is
applied  NON-VOLATILE MEMORY!

Ref. [4]
16

READING: Transistor is turned ON; small
sense current is passed through the MTJ
to ground; comparison with reference is
made

WRITING: Transistor is turned OFF; current
passed through lower conductor; hard
axis field created; magnetization of free
layer tilts
› Only the bit in which current is
applied in BOTH the easy and hard
axes will be written
› Other bits are HALF-SELECTED
(can cause errors)
Ref. [5] for both the diagrams
17
Thermally activated reversal of free layer
› Causes increase in error rate
› Certain level of energy barrier has to be maintained (E > 50 kbT;
where kb is the Boltzmann constant and T is the absolute
temperature)
 Loss of read-out signal due to switching induced demagnetization
of the free layer
 Integration with current CMOS technology; compatibility issues etc.
 Current status:
› 4 Mb chip @ 40 MHz by Freescale
› 16 Mb prototype by IBM

18
Ref. [6]

Advantages:
› Non-volatile
› Fast read/write operations
› Unlimited endurance
› Software development will be easy
(due to simple architecture and
overwrite)

Disadvantages:
› Integration of the magnetic stack is
critical due to the exact thickness definition of the tunnel layer
› Half-select phenomenon
› High power consumption during write
› Is it scalable? What factors affect scalability in the magnetic
domain?
19
Principle: Resistivity of a material depends on its present PHASE
 Chalcogenides (alloys of group VI elements) exhibit the following
properties:
› Existence in poly-crystalline and amorphous phases
› Quick and reversible change from one phase to another (on
change of temperature)
› Significant differences in resistivity of the two phases
 Amorphous phase has low free-electron density, low electron
mobility  low conductivity (high resistivity)  represents logic LOW
 Crystalline phase has high free-electron density, high electron
mobility  high conductivity (low resistivity)  represents logic HIGH

20
Material used: Ge2Sb2Te5
› Crystallization time ~ 20 ns
› Bitrates up to 35 Mbits/sec
› Overwrite capability up to105 cycles
 Writing:
› Changing from 1 to 0 (RESET):
› Large current (> 350 µA) is passed for a short time (~ 40 ns)
› Due to Joule heating, the material melts
› Then, it is rapidly quenched (to prevent recrystallization)
› Changing from 0 to 1 (SET):
› Small current (150 µA – 350 µA) is passed for a long time (~ 80 ns)
› Material crystallizes  logic 1

21
Reading:
› Very low current is passed (negligible Joule heating)
› Resistance is monitored (w.r.t. a reference)
› This differentiates between HIGH and LOW states
 Advantages:
› Non-volatile
› Very good scope for scaling
› Very high retention period (more than 10 years @ 125oC)
 Disadvantages:
› Large size (due to large current in the RESET stage) – CRITICAL
› Proximity disturbances (for e.g. heat transfer between
programming cell and adjacent cell)

22







Principle: Similar to PCRAM, except that an oxidizable top electrode
is used; leads to formation of a
conductive bridge (metallic pathway)
in chalcogenide once a threshold
voltage is achieved (LOW resistance)
This pathway breaks when polarity
is reversed (HIGH resistance)
Lower currents are required; allows for
smaller sizes due to reduction in size
of access transistors
Anode: easily oxidizable (e.g. Ag or Cu)
Ref. [7]
Cathode: Inert electrode
Solid electrolyte: Ag and GexS1-x (generally, 0.3 < x < 0.35)
The electrodes are separated by a dielectric; a via hole in this layer
defines the device parameter
23








On application of a small voltage at the anode, the following
reaction takes place:
› M  M+ + eAg ions are driven into the chalcogenide
This causes reduction of ions at the cathode to form metal ions
Positive ions get repelled into the solid electrolyte
Hence, a conductive path of metal ions is formed  LOW resistance
This is the ON state
On application of a reverse bias, the bridge is destroyed  OFF
state
Information is, however retained, due to electrodeposition
24

Advantages:
› Non-volatile
› Fast switching (< 50ns)
› Relatively low power consumption (low programming current)
› Scalability (down to 15 nm demonstrated)
› High retention time
› Can be used as a multi-bit storage

Disadvantages:
› Erase time is relatively high
› Ion diffusion and electromigration type loss can lead to loss in
data retention
› Silver has a high diffusion coefficient in Silicon
› Process related issues
25





Principle: Organic charge transfer complexes exhibiting
conductance switching used as active
layer
Materials exhibiting reversible conductance
switching are used
Device is a sandwich structure consisting of
3 layers between top and bottom
electrodes
The three materials are: AIDCN, Al and
AIDCN
(AIDCN  2-amino-4,5-imidazole
imidazole dicarbonitrile)
Acts like a resistive switch : states 0 and 1
Ref. [8]
26

Advantages:
› High resistance ratio between ON and OFF states
› Non-destructive read operation
› Reduced process complexity (suitable for vacuum deposition
and spin-coating processes)
› Hybrid memories: integration with CMOS is easily done
› Consists of frontend-of-the-line processing for CMOS circuit
fabrication; memory layers added on top
› High scalability

Disadvantages:
› Temperature stability
27

Millipede:
› Currently being researched and developed by IBM
› Efforts to combine the best features of DRAM and conventional
hard disk drive: speed of DRAM + high storage density of hard
disk
› Nanoscopic pits burnt on a thin thermo-active polymer layer,
called „sled‟
› Reading / writing by MEMS-based probes (parallel operation)
› Very useful in small footprint devices
28





READING:
› Probe heated to 2000C; keeps scanning data sled
› Presence of pit  cooling rate increases  resistance decreases
› Absence of pit  less cooling area  relatively high resistance
› Low resistance  read as logic HIGH (logic 1)
› High resistance  read as logic LOW (logic 0)
WRITING:
› Probe heated above glass transition temperature (around 400 K)
› To write 1, probe is lowered onto the sled; dent is created
› To write 0, heated probe is withdrawn from the surface 
surface tension causes the surface to be flat again
Advantages: Highly parallel, can reach high data-transfer rates
Disadvantages: Can consume a lot of power at high data rates
However, at few Mbits/sec, power consumption is comparable
29
to that in flash drives









High speed memory under research
U-shaped magnetic nano-wire
wire embedded into Si chip
Magnetically stored data moved electronically by
pulses of polarized current (spin coherent)
Writing done by heads that change magnetization
direction in domains
Reading by sensors arranged in the Si chip itself
Domain wall could be read as HIGH; it‟s absence as
LOW
MAIN PROBLEM: Crystal imperfections impede
movement; domains get stuck; using shorter (nanosecond) pulses could help
High storage density; very good read-write performance
Strong candidate for „universal memory‟
Ref. [9]
30








Based on position of carbon nano-tubes deposited on a chip-like
substrate
Many nano-tubes suspended on insulating "lands“ over a metal
electrode
At rest they lie above the electrode "in the air”
A small dot of gold is deposited on top of the nanotubes on one of
the lands, providing an electrical connection, or terminal
A second electrode lies below the surface, about 100 nm away
Voltage applied between terminal & lower electrode
High density, low power consumption
Mainly limited by current state of the art in lithography
31








Called the „fourth fundamental circuit element‟
Resistance is a function of the history of current through
and voltage across the device
Inherent memory present
Active research being conducted: ability to
perform digital logic operations proved in
April 2010
Very large number of read/write cycles
Very low power consumption
Very high density
Expected to reach density of 20 Gbytes/cm2 by
2013
Ref. [10]
Ref. [11]




Overview of current memory technologies :
› DRAM, SRAM, Flash memory etc.
› Limitations of the above
Need for new memory technologies
› Resistive memory devices
 PCRAM, MRAM, CBRAM, Organic memory etc.
Comparison of the technologies
Summary
33
34 Ref. [12]




Overview of current memory technologies :
› DRAM, SRAM, Flash memory etc.
› Limitations of the above
Need for new memory technologies
› Resistive memory devices
 PCRAM, MRAM, CBRAM, Organic memory etc.
Comparison of the technologies
Summary
35




Current memory technologies like SRAM, DRAM, flash
memory may not suffice for ever-increasing demand
Current need for cheap, scalable, non-volatile memory
technology
MRAM, PCRAM, CBRAM: good competitors
Novel technologies like racetrack memory, memristor-based
memory, nano-RAM certainly look promising
36




Thanks to FAU and all IITs for the wonderful opportunity
Special thanks to Prof. Heiner Ryssel for constant help and
guidance throughout
Thanks to Prof. Nandita Dasgupta for her support
Thanks to all present for being a wonderful audience 
37
[1] http://en.wikipedia.org/wiki/Static_random_access_memory
[2] http://en.wikipedia.org/wiki/Flash_memory
[3] 2B1750 Smart Electronic Materials, “Non-Volatile Random Access Memory
Technologies (MRAM, FeRAM, PRAM)”, Muhammad Muneeb, Imran Akram, Aftab
Nazir
[4], [6] The Emergence of Practical MRAM, Barry Hoberman, Crocus Technologies
[5] Non-MOSFET based memory, Alex Rodriguez-Triana, Terence Frederick
[7] A Scalable, Low-Power, Non-Volatile Memory Technology Based on a Solid State
Electrolyte, Michael Kund, Qimonda
[8] Organic Materials for High-Density Non-Volatile Memory Applications, R. Sezi, A.
Walter, R. Engl, A. Maltenberger, J. Schumann, M. Kund, and C. Dehm, Infineon
Technologies AG, Germany
[9] IBM (Almaden research centre)
http://www.almaden.ibm.com/spinaps/research/sd/?racetrack
[10] http://en.wikipedia.org/wiki/Memristor
[11] http://h30507.www3.hp.com/t5/Data-Central/HP-and-Hynix-Bringing-thememristor-to-market-in-next-generation/ba-p/82218
[12] Resistance Change Memories – Overview and Challenges, Tushar Merchant,
Freescale Semiconductor
38














Resistive memory devices, Harshit S. Vaishnav, Indo-German Winter Academy, 2009
Future memory devices, Andreas Hürner, Indo-German Winter Academy, 2008
Non-MOSFET based memory, Alex Rodriguez-Triana, Terence Frederick
Wikipedia articles - www. wikipedia.org
The Emergence of Practical MRAM, Barry Hoberman, Crocus Technologies
IBM (Almaden research centre)
http://www.almaden.ibm.com/spinaps/research/sd/?racetrack
http://www.technologyreview.com/computing/25018/?a=f
http://www.hpl.hp.com/news/2008/apr-jun/memristor.html
http://h30507.www3.hp.com/t5/Data-Central/HP-and-Hynix-Bringing-the-memristor-tomarket-in-next-generation/ba-p/82218
http://www.newscientist.com/article/dn11837
A Scalable, Low-Power, Non-Volatile Memory Technology Based on a Solid State
Electrolyte, Michael Kund, Qimonda
2B1750 Smart Electronic Materials, “Non-Volatile Random Access Memory Technologies
Resistance Change Memories – Overview and Challenges, Tushar Merchant, Freescale
Semiconductor
Organic Materials for High-Density Non-Volatile Memory Applications, R. Sezi, A. Walter,
R. Engl, A. Maltenberger, J. Schumann, M. Kund, and C. Dehm,, Infineon Technologies
AG, Germany
39