* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Download Design of a Self-Correcting Active Pixel Sensor
Pulse-width modulation wikipedia , lookup
Variable-frequency drive wikipedia , lookup
Three-phase electric power wikipedia , lookup
Power inverter wikipedia , lookup
Fault tolerance wikipedia , lookup
Electrical substation wikipedia , lookup
History of electric power transmission wikipedia , lookup
Immunity-aware programming wikipedia , lookup
Semiconductor device wikipedia , lookup
Current source wikipedia , lookup
Surge protector wikipedia , lookup
Voltage optimisation wikipedia , lookup
Stray voltage wikipedia , lookup
Schmitt trigger wikipedia , lookup
Resistive opto-isolator wikipedia , lookup
Alternating current wikipedia , lookup
Power electronics wikipedia , lookup
Voltage regulator wikipedia , lookup
Two-port network wikipedia , lookup
Switched-mode power supply wikipedia , lookup
Buck converter wikipedia , lookup
Mains electricity wikipedia , lookup
History of the transistor wikipedia , lookup
Design of a Self-Correcting Active Pixel Sensor Yves Audet Ecole Polytechnique, Dept. of Electrical and Computer Eng., P.O. Box 6079, Station Centre-ville, Montréal, Québec, Canada H3C 3A7 Tel: (514) 340-4711 Fax: (514) 340-4147 e-mail: [email protected] Glenn H. Chapman Simon Fraser University, School of Engineering Science, 8888 University Dr., Burnaby, B.C., Canada V5A 1S6 Tel: (604) 291-3814 Fax: (604) 291-4951 e-mail: [email protected] Abstract Digital cameras are growing ever larger in silicon area and pixel count, which increases the occurance of defects at fabrication time, or dead pixels that develop over their lifetime. An Active Pixel Sensors self-correcting for most common faults is created by spliting the photodiode and readout transistors into two parallel portions with only a small area cost. Simulations show operation is the same a single large device when no faults. When one half of the redundant pixel is stuck at low, output over a wide current range is reduced by 1.98 to 2.01. For one half stuck at high faults output, after offset removal, is reduced by a factor of 1.85 to 1.92. Hence self-correction of the pixel can be done with good accuracy via a simple shift circuit and with high accuracy with digital processing. Variation in transistor threshold voltages between the pixel halves of even 10% only causes modification of factors by 2-4%, hence giving a small effect.. 1. Introduction Digital cameras are becoming ever more prevalent these days due to the many advantages of digital photography over the regular film. An important trend has been the move to ever larger detector sizes for both resolution enhancement (higher number of pixels), and uses the larger lens systems available on existing camera systems. Currently the new generation of cameras is approaching standard 35 mm detector sizes (though about 22 mm wide is the largest currently available). As these detectors grow in size it becomes ever more important to avoid defects in the detector for systems involving millions of detector cells. Furthermore in other applications digital cameras are being put in environment that are remote or severe so that replacement of failed systems is not possible (for example in space probes). Thus there is a need for developing self-correcting camera systems which repair themselves. A more recent trend has been the move from the CCD detectors to the CMOS based Active Pixel Sensors [3]. This is occurring because CMOS detectors are easier to produce (using a nearly standard process), less expensive, offer lower power consumption and the ability to integrate other devices (like the A/D converters) on chip. In a previous paper [1] the authors first proposed an alternative APS cell which offers the additional capability of being redundant, and thus more reliable. In a subsequent paper [2] with other authors it was noted that this design was actually a Hardware self-Correcting Hardware (HC), which could be combined with additional Software Correction to create a very reliable system. In this paper a sample redundant APS cell has been designed. Simulations of this cell are investigated to confirm the self-repairing ability proposed previously. 2. The redundant pixel circuit The hardware correction method consists of two active pixel circuits working in parallel. Figure 1 shows the schematic diagram of the two active pixel circuits connected to achieve a redundant pixel. Considering one active pixel circuit, the light detection mechanism is described as follows. In normal operation, the incident light increases the reverse bias current of the photodiode Photodiode 1. This current charges the capacitance of the photosite node Photosite1 formed by the capacitance of the photodiode in parallel with the gate capacitance of the readout transistor M2.1. The photosite node is precharged through the reset transistor M1.1 to a voltage level applied at the line V Pix Reset prior to the voltage integration of the photocurrent. At the end of an integration period, the row select transistor M3.1 is activated in order to deliver at the line Col Out1 a current inversely proportional to the voltage built at the gate of the readout transistor. The redundant pixel of figure 1 is composed of two identical single pixel circuits working in parallel, providing built-in redundancy for a robust active pixel sensor array. While this circuit from the diagram shows some duplication, in practice it does not consume much increase in area. The photodiode area is much larger than minimum size (typically 25%40% cell area) and splitting it into two actually costs only a few percentage of the cell area. The readout (M2.1, M2.2) and row select (M3.1, M3.2) transistors are best scaled to half size to keep the circuit working like a full size device, so the total increase in area is low. Much of an APS cell’s area is also taken by the row/column/power lines, which are not duplicated. Future designs may use only a single row select transistor M3 shared between the two readout transistors (M2.1, M2.2) to save area. Col In Vdd Photodiode 1 Reset M1.2 Vdd Photodiode 2 Photosite1 Photosite2 Readout M2.1 Readout M2.2 Row Select M3.1 Row Select M3.2 Pix_Res Reset M1.1 Row_Sel V Pix Reset Col Out1 Col Out2 Figure 1. Schematic diagram of the redundant pixel P+ Polysilicon N+ Gate oxide V Pix Reset Pix_Res Vdd N-well Readout M2 Photodiode Reset M1 Reset M1 Figure 2. Details of the pixel fabrication layers. 3. The redundant pixel self-correcting scheme The self-correcting scheme built in the APS is designed especially to counter defects affecting the photosite of the pixel. Figure 2 depicts a cross-section view of the important layers involved in the fabrication of one pixel using a CMOS 0.35µm process. The P+ implant in the N-well forms the photodiode. This same P+ implant acts also as the source of the reset transistor M1. The readout transistor M2 is patterned separately and connected to the photodiode through a metal line. As in many other circuits there are two most probable outcomes from defects affecting the pixel. In the event where defects short the P+ - N-well regions of the photodiode, the photosite is said ‘stuck at high’ and the gate of the readout transistor is permanently connected to Vdd. The same effect will be observed if the reset transistor stays open and is unable to discharge the photosite. Then, the photodiode current will charge the photosite until Vdd is reached. This creates half the pixel as stuck on, so produces a constant offset to which the signal is added. The case where defects open permanently the row select and/or the readout transistor is also equivalent to a stuck at high type of fault since no current will be flowing through Col Out. On the other hand, defects shorting the P+ implant of the photodiode to the drain of the reset transistor will connect the photosite permanently to V Pix Reset. In this condition or others where the readout transistor is permanently turned on, the photodiode is said ‘stuck at low’. Calibration tests can identify the stuck pixels: a dark field (no illumination) test shows the stuck at highs as half the maximum output swing plus an offset. A light field (maximum illumination) test identifies stuck at lows by their half maximum output swing. Only the case where the row select and/or the readout transistor are shorted is not corrected by this scheme. In order to achieve the self-correcting scheme, the redundant pixel used the circuit of figure 3 as a column amplifier. Here, a current mirror formed by the transistor pair M4 and M5 having the same size, copy the added current of Col Out1 and Col Out2, Ipix, to the drain of transistor M6. The transistor M6 is used in its linear mode of operation and acts as a simple resistor. Hence, the output voltage Vout is given by: Vout = Vdd − RM 6 ∗ Ipix (1) Vdd Row_Sel Row_Sel Pix_Res 0.6V V Pix Reset Col In M6 Redundant Pixel Col Out1 Col Out2 Vout Ipix M4 M5 Figure 3. Schematic diagram of the pixel column amplifier Where RM6 is the output resistance of the transistor M6. Investigations of the circuit behavior of the redundant pixel have been performed using Spectre simulations for a CMOS 0.35µm process provided by the Canadian Microelectronics Corporation. The photosites reset voltage V Pix Reset is set to 0.6 V and the row select transistors M1.1, M1.2 are permanently turned "on" to establish the biasing currents during the simulations. It should be noted that when using the redundant pixel within a pixel array, the row select transistors are only activated at the end of an integration period, to allow the sharing of the amplifier among the pixels of a same column [1]. The results of the Spectre simulations are presented in figure 4. The output voltage of the column amplifier Vout is plotted for three different cases: The redundant pixel is defect free Vout_df, one photosite of the redundant pixel is stuck at low Vout_sl, meaning permanently connected to V Pix Reset and finally, one photosite is stuck at high Vout_sh, meaning permanently connected to Vdd. In order to simulate the light generated phtotodiode currents, a current source of 50 nA has been added in parallel to both photodiodes. The photosite voltage integration period is initiated by a Pix_Res impulsion shorting the photosite nodes to V Pix Reset through the reset transistors. Then the voltages at the photosite nodes start rising, as shown in figure 4, from the curves of the voltage at the node Photosite1, (see curve Vphoto1) producing a ramp of a 1.36 V increase over 9 µs of integration until the Pix_Res impulsion resets the photosite voltage. In the case of Vout being defect free, the integration voltage ramp Vphoto1 is equivalent to the one at the node Photosite2, whereas in the suck at low case, Photosite2 is shorted to V Pix Res and in the stuck at high case, Photosite2 is shorted to Vdd. The three output voltages exhibit a non-linear variation. This behavior is expla ined from the fact that the output currents Col Out1 and Col Out2 of each pixel follows a square law with respect to the photosite voltage, due to the readout transistor operating in the saturation region. Hence, the resulting added current value, Ipix follows a square law, which is reflected on the output voltages according to the equation (1). Pix_Res Vout _sh Vout _df Vout _sl Vphoto1 Figure 4. Output voltage results from the simulations in the case of defect free (Vout), stuck at low (Vout_sl) and stuck at high (Vout_sh) redundant pixel. From figure 4, we noticed that Vout_sl and Vout_sh experience approximately the same output voltage swing, being half the one of the defect free output voltage Vout_df, except that Vout_sh is shifted by a positive offset voltage. This offset voltage corresponds to the constant current produce at the output of Col Out2 when the node Photosite2 is permanently connected to V Pix Res. Having the output voltage swing in the case of the stuck at high and the stuck at low type of defect being exactly half the defect free case, would greatly simplify and speed up the correction algorithm. In that case, only a simple binary left shift (multiply by 2) would be required to re-establish a faulty pixel output to the value of a defect free one once the output voltage is converted in digital format. In order to evaluate the ratio of the output voltages for both defectives cases, a simulation of the ratios Vout_df /Vout_sl and Vout_df /Vout_sh have been performed for four values of photo-generated currents. These currents varying from 10 nA to 50 nA correspond to low to bright illumination of the pixel, and the ratios for the two faults are represented by Rsl and Rsh on the graphs of figure 5. For each of the three output voltages, their respective offset voltage have been subtracted before evaluating the ratios. In both cases, except for the beginning of the integration period where some instability is created due to the very small output voltage values, the ratios remain constant over the entire integration period. For Rsl ratios of approximately 1.98 to 2.01 are observed meaning an error of 1% compare to the ideal value of 2.00. Similarly, Rsh varies from approximately 1.85 to 1.92 meaning a maximum error of 7.5%. 50 nA 37 nA Rsl 23 nA Rsh 10 nA 37 nA 50 nA 23 nA 10 nA a) b) Figure 5. Simulation results for ratios of the output voltages in the case of a) stuck at low (Rsl) b) stuck at high (Rsh) faults for four values of photo-current. 4. Stability of the self–correcting scheme Similar to any important characteristic of a given device, the characteristic of the selfcorrecting scheme must also be tolerant to the variation of process parameters throughout the same die. In the present case of the redundant pixel design, the ratios Rsl, Rsh have been chosen as the characteristic to evaluate the tolerance of the self–correcting scheme to variations of the process parameters. In this design the readout transistors represent the most critical component of the pixel since it is responsible of converting the integrated photo-current into the pixel output current, which dictates the output voltage according to the equation (1). In order to verify the dependence of the ratios on the readout transistor parameters, simulation of the ratios, similar to the ones of figure 5, have been performed where the nominal threshold voltage Vtpo of one readout transistor of the redundant pixel was varied from –10% to +10% of its nominal value. Table 1 summarizes the results obtained where the worst ratios over the integration period of 9 µs have been recorded. The photo-current was set to 50 nA (full illumination). The results on the Error rows represent the difference in percentage of the ratios compared to their values at Vtpo nominal (variation of 0%). Both ratios, present a good stability yielding an error of +3.5% to –2.5% in the case of the stuck at low and +4% to –2% for the stuck at high. These results demonstrate the tolerance of the self-correcting scheme to transistor threshold voltage variations, where the error on the ratios are smaller than half the percentage of variation of Vtpo itself. Table 1. Simulation results for ratios of the output voltages as a function of the nominal threshold voltage (Vtpo) variation on one readout transistor. Vtpo variation Rsl Ratios Error (%) Rsh Ratios Error (%) - 10% -5% +0% +5% +10% 2.08 +3.5 1.94 +4.0 2.05 +2.0 1.90 +2.0 2.01 0 1.86 0 1.97 -1.0 1.84 -1.0 1.94 -2.5 1.82 -2.0 5. Output voltage linearization The ouput voltages obtained on figure 4 exhibit a non-linear progression, which could be non-desirable for image processing and image compression. Knowing the quadratic relation between the photosite voltages and the pixel output current, the output can be linarized. The gate voltage of the output transistor is proportional to the photo-generated current. Iphoto, and the integration time, t. The readout transistor being in saturation mode, the pixel output current, Ipix, is then proportional to the square of the gate voltage, which leads to: Ipix ∝ (Iphoto ∗ t ) 2 (2) From equation (1), Ipix can be expressed in terms of Vout to obtain linear expression as a function of integration time: Ipix = Vdd − Vout ∝ Iphoto ∗ t RM 6 (3) The graph of figure 6 illustrates the effect of modifying the three values of the output voltages of figure 4 according to equation (3). An offset voltage is also subtracted from Vdd in the case of the stuck at high output in order to establish the same initial voltage level than the two other cases. The curves show a more linear relationship, although a non-linearity is still detected. It is suspected that these non-quadratic effects are due to the transistors of the current mirror and the PMOS transistor M6 used as a resistor. While not possible with a simple circuit most digital cameras are combined with microprocessors for image compression and correction. Algorithms for the pixel correction using the calibration tests discussed in section 3, and these current correction formulas can easily be handled by such on board system. Alternatively they can be corrected in by post camera processing for systems where accuracy of images is very important. 6. Conclusion This study has demonstrated the robustness of the self-correcting scheme proposed to improve the yield of a large area APS sensor. It has been shown that the redundant pixel circuit proposed with a simple column amplifier produces ratios of defect free pixel over faulty pixel output voltages of nearly 2.0 for stuck at high and stuck at low types of fault. The value of 2.0 ½ (Ipix_df) (A) ½ ½ (Ipix_sl) ½ (Ipix_sh) Figure 6. Effects of the linearization algorithm on the output voltages of figure 4. of the ratios represents an ideal characteristic for a simple and fast correction algorithm consisting of only a left bit shift of the digitally converted output from the column amplifier. The ratios have been proven to be stable for different values of photo-current and over the entire range of integration. Also, we have found that variation of the threshold voltage of one readout transistor of the redundant pixel affected the ratios in less than half the values of threshold voltage variation itself. Based on these simulation results a good level of confidence is expected for this self-correcting scheme implemented on a real device A simple mathematical transformation algorithm has been study in order to linearize the output response of the column amplifier. This algorithm has been proven effective in removing most of the non-linearity. Samples of the redundant pixel design are being fabricated in a 0.35µm process. Laser modifications of the fabricated devices will be used to induce stuck at high and stuck at low types of fault. Focusing the laser beam at a moderate power on one of the photodiodes of the redundant pixel will generate enough photo-current to completely charge to Vdd the corresponding photosite in a very short time, thus, creating a stuck at high type of fault. Care should be taken to reduce as much as possible stray laser beam reflections from reaching the defect free photodiode during measurement. Also the laser power should be carefully monitored to avoid damaging the photodiode. On the other hand, stuck at low type of fault could be generated with a short intense laser pulse to induce dopant diffusion from the P+ implant of the photodiode through the N-well and down to the P-substrate. Hence, a low resistance path will be created between the photosite and the P-substrate, connected to the ground, producing a stuck at low type of fault. 7. Acknowledgement The authors would like to express their gratitude to the following founding organizations supporting this research, the National Research Council of Canada (NSERC), Micronet and BC Advanced Systems Institute. 8. References [1] G.H. Chapman and Y. Audet, "Creating 35 mm Camera Active Pixel Sensors", Pro ceedings Intern. Symposium on Defect and Fault Tolerance in VLSI Systems 1999, pp 22-30, Albuquerque, NM, Nov. 1999. [2] I. Koren , G. H. Chapman , and Z. Koren, “A Self-Correcting Active Pixel Camera” Proceedings Intern. Symposium on Defect and Fault Tolerance in VLSI Systems 2000, Japan, Nov. 2000 [3] E.R. Fossum, "Active Pixel Sensors: Are CCD's Dinosaurs? ", Proc. SPIE, Charge-Coupled Devices and Solid -State Optical Sensors III, Feb. 1993 Vol. 1900, pp. 2-14.