Download COEN6511 LECTURE 3

Week_12
Driving high loads
On the chip, there are many situations that we have to drive large loads. Some of these
loads require special attention such as the clock distribution network, or the output pad
drivers. The figure below shows the arrangement of the PADs and the VDD and Gnd
lines. In here there is only one VDD and One Ground, usually there are many more and
they are well distributed all around the chip.
For example if we take the output pad driver which is a large load and see how can we
design it.
Example:
Consider a pad and driver circuit, pay particular attention to the size of the pad and the
driver.
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Lecture#12 Overview
If we take the cross section of the pad, we get:
1. A two metal layers circuit.
2. A two metal layers circuit with space for pad.
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Lecture#12 Overview
The area of the pad is 10,000um2
The pad is made up of level-2 metal with capacitance of 18aF/ um2
Total capacitance of pad = 0.18pF
This is not considering the wire and the solder.
Consider the clock distribution tree network,
The length covered by the clock distribution is a significant amount. How do we drive
this network? For the clock we have a special design due to special requirements but
generally for large loads we design a tapered buffer:
Assume the small buffer driving a large load then the delay is calculated as:
   0 * fan out
If fan out is 10,000 then   10,000. 0
This delay is un acceptable for most applications
The solution to the problem of driving large loads from a small driver is solved by using
Tapered Buffers.
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Lecture#12 Overview
Tapered buffers or drivers
1. Assume that the scaling factor S is uniform
2. Assume for the time being that load capacitance of each stage can be represented
by its input capacitances ( gate capacitance) of each inverter
We then have:
That is, we neglect the Cdrains (diffusion capacitance and routing capacitances. This is
over-simplification but easier to show the design, real designs particularly in sub micron
domain, the drain capacitances can not be ignored and this will be treated later).
CL
, CL is the load capacitance, Cin is the input capacitance of the smallest inverter
C in
in the circuit, Y=fan-out
Then, Y  S N , N is the number of inverters and S is the scaling factor.
Y
ln Y  N ln S
ln Y
N
ln S
Total delay T = N * S *  in
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Lecture#12 Overview
What is the scaling factor that gives minimum delay and what is that delay?
T
ln Y
* S * in
ln S
(ln S 
1
S)
S
dT
 ln Y in
dS
ln S 2
for minimum delay: dT/dS= 0,
hence 0  ln S  1 ,
S e
Optimum scaling factor for minimum delay is Sopt=e
T = N * Sopt *  in
Example
Design a buffer driver to drive a 3pF load, with an initial Cg for small inverter of 3fF and
 in =10ps.
Optimum delay S=e
3 pF
Y
 1000
3 fF
ln Y ln 1000
N

 6.9
ln S
1
N  7 stages
CL
e
CN
CN 
C L 3 pF

 1.1 pF
e
2.7
CgN  1.1 pF
Assume Cox=3.5fF/um2,
CgN  Cox(Wn Ln  Wp Lp )
Assume Wp=2Wn,
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Lecture#12 Overview
1.1*1012  3.5 *1015 * 3 *WN LN
1.1
WN LN 
 105m 2
3.5 *10 3 * 3
or
Assume a 0.5um process, L=0.5um.
WN of N = 210um
WP of P = 420um
N
N-1
N-2
N-3
N-4
N-5
N-6
N
210
77
28
10.6
4
1.5
0.5
P
420
154
56
21.2
8
2
1
Delay= 7 * 2.7 *10 ps
 189 ps
Initially, T= 1000 *10 ps
= 10,000 ps
Area of last stage = 3 x Ln Wn
= 3 x 210 x 0.5
= 315um
Similarly, area for previous stages is calculated and the total area is found to be about
500um2.
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Lecture#12 Overview
Design techniques
**Please note, as a first approximation, now that we have the initial sizes. Now we
can calculate the drain capacitances and take it into account in our intermediate
loads, probably 2 or 3 iterations are required to come to convergence**
Example
Use 3 stages for the previous buffer and comment on the delay and area.
N=3, Y=1000, S=10
CL 3 pF

C3
C3
3 pF
C3 
 300 fF
10
10 
(3Wn Ln )3.5  3 fF or Wn Ln 
Wn3=58um
Wn2=5.8um
Wn1=0.6um
300
 29m 2
3.5 * 3
Wp3=116um
Wp2=11.6um
Wp1=1.2um
Delay = N * S *  0
3 * 10 * 10ps
300ps
Area = (29+2.9+3) x 3 = 100 um2
1
2
3
Case
S=7
S=3
S=1
Area
500 um2
100 um2
1 um2
Delay
189
300
10,000
Criteria to consider when choosing right driver are Power(P), Delay(D) and Area(A) or
PD (power delay), AT or AT2. In this case if we choose AT, the 3 stage driver gives a
better performance.
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Lecture#12 Overview
The layout for a driver is done in such a way so as to reduce the area. An example of a
large transistor design showing only diffusion and poly layers is shown below.
Another transistor design including the VDD and GND is shown below.
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Lecture#12 Overview
A PAD and its driver is shown below, to indicate all the interconnection and
the relative sizes of the PAD and the Driver.
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Lecture#12 Overview
Input protection circuits
The gate of a cMOS device appears like a small capacitance in order of few
fF with a small leakage voltage less than pA.
Without protection the cMOS transistors can be damaged with electrostatic discharges (
sometimes permanently). The protection circuitry lowers the input resistance from 1014
to 16
10 . To 1010 ohm. The decrease in resistance is of little consequence in digital circuitry.
The principal in designing the protection circuitry is to ensure that the voltage applied to
the gate is limited by the protection device.
Electric-field at which oxide breaks down is about 5 x 106 V/Cm
For our technology, t ox  100 Ao ( CMOSIS process technology TOX=9.6 10-9 nm)
Voltage at break down point =
5 *10 6 V
 5V , (10-8 * 5*10 6.)/10-2
10 6
for a power supply of 3.3V
For this reason, a protection circuitry is essential.
Most protection circuitry is based around two principles.
1. Punch through ( Source to drain)
2. Avalanche ( drain diffusion to substrate)
In punch through due to high voltage the depletion region is extended until it
reaches the source where current can flow freely, only limited by the external
resistor.
In Avalanche, due to the large electric field applied to the drain the electric field
built up will accelerate the electrons sufficiently to ionize neutral silicon atoms.
This process continues, current flows freely from drain to diffusion, only limited
by external circuitry.
1 Punch Through
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2. Avalanche
Lecture#12 Overview
Protection circuitry using input resistor and reverse diode
RD is the dynamic resistance of the transistor.
Vg  Vin
RD
RD  RP
Where Vin is the voltage applied to the Pad and Vg is the safe gate voltage. RD the
dynamic resistance of the structure.
Example,
RP
Vg
Assume Vg=3.3V, Vin=5.0V, RP=500 
RD
3.3  5 *
RD  500
Or
RD
Vp
3.3RD  1550  5RD
1550

1.7
Approximation: At this stage, the transistor works like a large diode. The area of the
drain has to be large enough to handle the large current due to the avalanche.
So let 1/RD ~ β approximate
or 1.7/ 1550 ~196.47 8 10-6 W/L
W
We have used    n Cox , we can find W by assuming L. Note that we used
L
CMOSIS 5B transconductance parameter K’P = 196.47 8 10-6 µA/V2. Please note that we
are applying the transistor model which is not appropriate here, however it gives us some
approximate value for W.
RD 
W/L ~ 6 , if L= 0.5 μm, then W= 12μm
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Lecture#12 Overview
Other methods:
The Figure below shows a structure that can be used to protect against surges in voltage.
When input voltage increases the depletion layer increases. When it reaches the lower
diffusion then current will flow to ground protecting the gate of the circuit. X is the
depletion layer thickness and is calculated in such a way that at a certain voltage, current
goes to ground.
(
)1/2 (
)1/2
X = ( 2 q ) (NA + ND)/NA ND
Φo – V
Φo, NA , ND Can be obtained from Process Technology parameters and 2 q is a
constant. V is the gate input voltage.
Generally we have to protect the circuit against both negative and positive voltage surges.
The circuit below is a good protection circuit that can be easily implemented in CMOS
technology.
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Lecture#12 Overview
Design techniques.
Use P+ and N+ guardrings around nMOS and pMOS transistors and connect them to Vdd
and Gnd to reduce latch up
Place substrate and well connections close to the source of the device.
Use minimum area of either p-well or nwell depending on technology.
For large transistors and critical transistors you will find guard rings in the layout. These
guard rings are used to reduce noise in the substrate that are coupled by the reverse biased
diodes capacitances. Surround the n MOS in the p-substrate with p-diffusion ring and
connect it to Vss. In the same way surround the pMOS in the n-substrate with ndiffusion ring and connect it to Vdd, in this way all the stray electrons and holes will be
collected by the N and P guard rings.
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Lecture#12 Overview
VDD
Vin
Diffusion n+
N
Contact
Polysilicon
Metal
Vss
Diffusion P+
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Lecture#12 Overview