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Transcript
An Oscilloscope Array for HighImpedance Device Characterization Fred Chen, Anantha Chandrakasan, Vladimir Stojanović Massachusetts Institute of Technology Connecting Systems to Emerging Devices Develop Device Models Micro-architect Circuits RWL RDRV Enable use for system level exploration CDRV P H CNT Characterization CLOAD CWL CC CP CC S CP W T Extract Tradeoff Curves Make Informed Architecture Choices Feedback for device research Ease new device testing/characterization Enables comparison of emerging devices ESSCIRC 2009 2 Traditional Measurement Techniques Measurement Limitations Large impedance mismatch Poor power transfer ESSCIRC 2009 3 Traditional Measurement Techniques Measurement Limitations Large impedance mismatch Poor power transfer Large test parasitic Limits accuracy Limits bandwidth ESSCIRC 2009 4 Traditional Measurement Techniques Measurement Limitations Large impedance mismatch Large test parasitic Poor power transfer Limits accuracy Limits bandwidth Physical Test Setup Cumbersome Difficult to reproduce Limited number of measurements ESSCIRC 2009 5 Silicon Sub-sampling Scope Chip SEM Transceiver Layout Transceiver Block Diagram TX ΔΣ Pad + Cap for ΔΣ RX Create a flexible pad interface 16 x 16 array of 52x52μm pads Independent 100x100μm transceivers talking to each pad Adjustable termination impedance to improve power transfer Reduce pad/interface parasitic Improve measurement accuracy – less to de-embed ESSCIRC 2009 6 Silicon Sub-sampling Scope Transceiver A Transceiver B DUT creates the ‘channel’ for the link Channel Interface allows for arbitrary connections between pads Measure step response (TDR, TDT) using sub-sampling Key Challenges: Simultaneously enabling wide bandwidth input with high impedance Accurate measurements with small devices Fine time resolution (10’s ps) with large time range (100’s ns) ESSCIRC 2009 7 Transmitter and Pad ESSCIRC 2009 Large pad capacitance 8 Transmitter and Pad Force pad coupling to a known node Add dummy driver with similar bandwidth (lower Z) to drive the coupled node Effectively null out the ~60fF pad capacitance ESSCIRC 2009 9 Transmitter and Pad Force pad coupling to a known node Add dummy driver with similar bandwidth (lower Z) to drive the coupled node Effectively null out the ~60fF pad capacitance ESSCIRC 2009 10 Delta-Sigma DAC ΔΣ-DAC Current Filter: Traditionally requires very large caps & inductors Add voltage filter in current mirror: Enables lower corner frequency using smaller capacitors 1MHz corner for C1, C2 & C3 ~ 340fF Filter bandwidth dependent on bias current (gm) – wider as for larger gm ESSCIRC 2009 11 Receiver Adopted from [1] to function rail-to-rail Calibration port enables off-line offset calibration 2 20-bit counters in Rx: [1] M. Takamiya, Mizuno, M., Symposium on VLSI Circuits, 2004. Extract voltage/timing distribution 1 million averages to reduce noise by up to 60dB ESSCIRC 2009 12 Timing Generation Need fine time resolution over a long period PLL Æ fine resolution, short period Divided clock Æ coarse resolution, long periods Feed fixed and rotating phases of PLL into dividers Accumulate phase differences at the divider outputs ESSCIRC 2009 13 Measurement Noise For each slice in time, sweep voltage to get CDF Use PDF to acquire mean voltage 30mVp-p ~ 3σ Æaverage down to σ ~10’s uV Resolution limited by external reference ESSCIRC 2009 14 Delta-Sigma DAC Linearity f M ≥ 2 fC ⋅ 2 B LSB = 330nA ENOB = 4.6 bits @ fM=500MHz Indicates ~ -35dB filter frequency of 10.3MHz ESSCIRC 2009 16 Pad Cap Compensation Normalized Step Responses Normalized Frequency Responses with cap compensation 3X No cap compensation Step responses at transmitter (7.5kΩ termination): Bandwidth of step with compensation is ~ 3X larger than with no pad capacitance nulling ~5fF of residual pad capacitance & 15fF of device capacitance ESSCIRC 2009 17 Carbon Nanotube Step Response Tx Rx Measured step response across a sheet of CNTs 30-50μm each over a > 10μm span (A to B) ~6dB loss at Rx Connection automatically detected ESSCIRC 2009 18 Conclusions Silicon test infrastructure for emerging highimpedance devices: Adjustable termination offers better power transfer Interface parasitic can be better controlled Flexible pad interface for faster detection and repeatable measurements Minimizing Interface Capacitance Requires small devices Æ larger variation Variation/error can be corrected with compact & efficient calibration circuitry ESSCIRC 2009 19
