Download Analog IO VDD (2.5V)

PCB Design
Preeti Mulage
04/05/2010
GND
Chip Connections
• Four Plane PCB
• Two Power Planes
VR_IL
VR_IR
• Analog IO VDD, Digital
IO VDD and Digital VDD
VR_VB
VR_VBR
• GND
CEN_B
• Inputs and outputs from
the FPGA are at 2.5V
D0
D1
2.5V
IO_VSS
PRB1
VSS
PRB2
TEN
IBIAS_L
SC_SER_IN
IBIAS_R
SC_RESET
VB
SC_READ_CTRL
VBR
SC_COUNT_CTRL
PBREAK
EQ_B
2.5V
AVDD
AVSS
• Two for routing
• Inputs and outputs from
the pads are at 2.5V
1.2V
SC_SER_IN
SC_RESET
SC_READ_CTRL
SC_COUNT_CTRL
SC_CLOCK
SC_SER_OUT
IO_VDD
D2
VDD
D3
EQ_B
Q3
CEN_B
Q2
Q0
WEN
Q1
RWEN
D0
TESTOUT
D1
TESTIN
VSS
TEN
VDD
IO_VSS
Test Point
IO_VDD
SMA Connector
SC_CLOCK
SC_SER_OUT
D2
D3
WEN
RWEN
TESTOUT
TESTIN
FPGA Connections
• iBOB
• Connections using Z-DOK connector with 40 pins
• Small swing differential signals from/to the FPGA – LVDS chips used to convert
them to single ended full rail signals to/from the chip
Voltage Regulators – LT3026
• Input Voltage Range: 1.14V to 3.5V
• Adjustable Output Range: 0.4V to 2.6V
• Output Current: Upto 1.5A
To be used to generate:
• Analog IO VDD (2.5V)
• Digital IO VDD (2.5V)
• VDD (1.2V)
Bias Voltages – Resistor Dividers
• Potentiometer : 5 kΩ
• Adjustable Output Range : 10mV to 2.5V or can be directly bypassed to ground
through the header
To be used to generate:
• VB
• VBR
• IBIAS_R
• IBIAS_L
Packaging – CPG06418
• 64 Pin PGA package from Spectrum Semiconductors
64
59
54
49
1
47
5
42
10
37
15
33
17
21
26
Bonding Diagram
31
ZIF Socket – 265-6310-9UA-1902
Components Needed
• Voltage Regulators
• Capacitors (for the regulator and for de-coupling caps)
• Resistors & Potentiometer
• Test Points
• SMA Connectors
• Jumpers
• 2x1 Headers
• One 40by2 Z-DOK Connector