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STICK DIAGRAM
EMT251
Schematic vs Layout
VDD
VDD
M2
In
Out
M1
In
Out
Inverter circuit
GND
Schematic vs Layout
VDD
2-input NAND gate
VDD
B
A
B
Out
A
GND
Stick Diagram
A stick diagram is a graphical view of a
layout.
 Does show all components/vias (except
possibly tub ties), relative placement.
 Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub
boundaries.

Stick Diagram
Represents relative positions of transistors
 Stick diagrams help plan layout quickly

 Need
not be to scale
 Draw with color pencils or dry-erase markers
VDD
VDD
Inverter
NAND2
Out
Out
In
GND
GND
A B
Stick Diagram
Layers
Metal (BLUE)
Polysilicion (RED )
N-Diffusion (Green)
P-Diffusion (Brown)
Contact / Via
How to design?
Logic Graph / Euler Path
X
A
j
C
C
B
X = C • (A + B)
C
A
PUN
i
i
X
B
VDD
j
B
A
B
C
GND
A
PDN
Stick Diagram of C • (A + B)
A
C
B
A
B
C
VDD
VDD
X
GND
X
GND
Consistent Euler Path
X
C
i
X
B
VDD
j
GND
A
A B C
Example
A
C
B
D
X
D
X = (A+B)•(C+D)
C
D
A
B
C
VDD
X
B
A
B
C
D
PUN
A
GND
PDN
LAYOUT DESIGN
RULES
EMT251
3D View
Design Rules
Interface between designer and process
engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width
scalable design rules: lambda
parameter
absolute dimensions (micron rules)

CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Representation
Draw PMOS:
1. Active + Poly
2. Contact_to_active
3. Metal1 above Contact
4. P-Plus Select
5. N-Well
6. N-Well Contact
Draw NMOS:
1. Active + Poly
2. Contact_to_active
3. Metal1 above Contact
4. N-Plus Select
5. P-Well
6. P-Well Contact
Layers in 0.35 mm CMOS process
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
Select
3
Metal1
2
3
2
4
Metal2
3
Transistor
Transistor Layout
1
3
2
5
Vias and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
Select Layer
2
3
Select
2
1
3
3
2
Substrate
5
Well
CMOS Inverter Layout
GND
In
VDD
Out
(a) Layout