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ETHERNET
for
HCMOS 7 x 5mm
3.3V
50ppm
Model: FXO-HC735RGB-156
XO Freq: 156.25MHz
Features
Low Jitter
Low Cost
Tri-State Enable / Disable Feature
Industry Standard Package
Gold over Nickel Termination Finish
V DD
Enable / Disable
FOX
X PRESSO
OUTPUT
ASICs
GND
Electrical Characteristics
Parameters
Frequency
Symbol
Condition
FO
156.25 MHz
Frequency Stability 1
Temperature Range
Supply Voltage
TO
TSTG
VDD
Input Current
IDD
Output Load
HCMOS
Start-Up Time
Standard operating
Storage
Standard
50 ppm
-40°C to +85°C
-55°C to +125°C
3.3V ± 5%
Standard Load
55 mA
Standard
15 pF
TS
10 mS
Output Enable / Disable Time
Moisture Sensitivity Level
Termination Finish
Maximum Value
(unless otherwise noted)
100 nS
MSL
1
Au
Note 1 – Stability is inclusive of 25°C tolerance, operating temperature range, input voltage change, load change, aging, shock and vibration.
Output Wave Characteristics
Parameters
Symbol
Condition
Standard Load
Standard Load
@ 50% VDD Level
Maximum Value
Output LOW Voltage
Output HIGH Voltage
Output Symmetry
VOL
VOH
Output Enable (PIN # 1) Voltage
VIH
≥70% VDD
Output Disable (PIN # 1) Voltage
Cycle Rise Time
Cycle Fall Time
VIL
TR
TF
≤ 30% VDD
3 nS
3 nS
20% ~ 80% VDD
80% ~ 20% VDD
20% VDD
80% VDD MIN
45% ~ 55%
DWG-100718 | Rev. 6/2/2010
Page 1 of 2
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© 2010 FOX ELECTRONICS | ISO9001:2000 Certified
ETHERNET
for
HCMOS 7 x 5mm
3.3V
50ppm
Model: FXO-HC735RGB-156
XO Freq: 156.25MHz
Dimensional Drawing & Pad Layout
0.01 F
E/D
#1
NC
GND
VDD
#4
NC
#2
#3
OUT
HCMOS LOAD
(15 pF)
Phase Jitter & Time Interval Error (TIE) (Typical Measurements)
Frequency
Phase Jitter
TIE
(12kHz to 20MHz)
(Sigma of Jitter Distribution)
Units
156.25 MHz
0.77
3.3
pS RMS
Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; VDD = 3.3V.
TIE was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; VDD = 3.3V.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Random & Deterministic Jitter Composition (Typical Measurements)
Frequency
156.25 MHz
Random (Rj)
Deterministic (Dj)
(pS RMS)
(pS P-P)
1.27
8.6
Total Jitter (Tj)
(14 x Rj) + Dj
26.6 pS
Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software.
Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)
Pin Functional Description
Pin #
Name
Type
1
1
2
3
4
E/D
GND
Output
VDD
Test
Points
2
N. C.
Logic
Ground
Output
Power
Hi Z
Function
Enable / Disable Control of Output (0 = Disabled)
Electrical Ground for VDD
HCMOS Oscillator Output
Power Supply Source Voltage
No Connection (Factory Use ONLY)
NOTES:
1
2
Includes pull-up resistor to VDD to provide output when the pin (1) is No Connect.
Installation should include a 0.01µF bypass capacitor placed between VDD
(Pin 4) and GND (Pin 2) to minimize power supply line noise.
DWG-100718 | Rev. 6/2/2010
Page 2 of 2
© 2010 FOX ELECTRONICS | ISO9001:2000 Certified | FOXONLINE