Download 1 - University of California, Berkeley

UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified by Yida Duan ([email protected])
Andrei Vladimirescu
Homework #7
Due Friday, March 23, 5pm @240 Cory
EECS141
PROBLEM 1. Static CMOS Logic
A logical path is shown in the schematic above. The first stage is unit-size inverter
(0.72um/0.36um). Use static CMOS to implement gate X, Y, & Z. Size them such that
the worst-case pull-up delay is equal to the worst-case pull-down delay. All gates in
parallel have the same size. In addition, keep all NMOS transistors of gate X the same
size; keep all PMOS transistors of gate Y the same size. Use parameters found in
g25.mod, use Vdd=2.5V, gamma=1.
(a) What is the logical effort (g) of gate X, Y, & Z? What is the normalized intrinsic
delay (p) of gate X, Y, Z? p is the intrinsic delay normalized to a unit size inverter.
(b) What is the total branching effort (B), path logical effort (G), path electrical effort (F),
and path effort (H)? What is the optimum effort per stage (h) to minimize delay? To find
F, you need to calculate gate capacitance of the first stage.
(c) Find the transistor width for both nmos and pmos of gate X, Y, Z. (The width of each
transistor does not have to be integer multiples of lambda=0.12um.)
(d) What is the delay from input to output through with path? The intrinsic delay of unit
size inverter, tp0=20ps
(e) Verify the delay you calculated in part (d) with HSPICE. (You do not have to specify
AD AS PD PS in SPICE deck, using the SPICE default value is fine. For accurate
transient simulation, use 0.5ps for both rise time and step size)
PROBLEM 2. Ratioed Logic
As shown in the schematic above, a unit-size inverter (0.72um/0.36um) is driving a
Peusdo-NMOS inverting stage. The external load capacitance, C L=50fF. Assume the
unit-size inverter has an equivalent capacitance of Cunit, an equivalent output resistance of
Runit. Also assume the equivalent output resistance of Pseudo-NMOS stage Req=Runit/S
(a) Keep the Wp/Wn ratio of the Pseudo-NMOS stage 2:1, find the delay for a low-to-high
transition at the output, tpLH, in terms of Cunit and Runit.
(b) Use Cunit=2fF, find the optimal S that minimize the low-to-high delay by taking
derivative of your result in part (a).
(c) Use tp0=0.69*Runit*Cunit=20ps, calculate the minimum delay for low-to-high
transition at the output, tpLH.
(e) Suppose that the probability for input being 0V, α0=50%; the probability for input
being 2.5V, α1=50%. Ignore short circuit current, what is the average power dissipated
by this circuit? Use Vdd=2.5V, fclk=3GHz.
PROBLEM 3: Pass Transistor Logic
The function F = A XOR B is to be implemented in pass transistor logic according to the
diagram below.
(a) How would you implement the pass transistor logic with NMOS-only switches?
Assume both true and complimentary input signals are available.
(b) What is the minimum voltage at which this circuit will operate correctly (and why)?
For the NMOS switches use VTH0 = 0.5V, γ = 0.4V, 2φF = 0.6V. Assume that the inverter
has an ideal VTC that switches when its input is at VDD/2.
(c) A level restoring PMOS transistor is now added as shown in the figure below. If the
level restoring PMOS transistor has VTH0 = -0.5V and W/L = 4 and μN = 3μP, what is the
minimum W/L for the NMOS switches in order for the circuit to function properly?
(Assuming all inputs are driven by ideal voltage source)
PROBLEM 4: Dynamic Logic, Charge Sharing & Leakage Current
(a) Assuming that all inputs of the circuit shown below are initially 0 during the precharge phase and that all internal nodes are at 0V, calculate the voltage drop on Vo, if A
changes to VDD during the evaluate phase. It is given that Vtn0=0.5V, 2φF=0.6V and
γ=0.4V0.5. Hint: Don’t forget the body effect.
(b) Now calculate the voltage drop on Vo if both A and B change to VDD (under the
above conditions)
(c) If we do not want Vo to drop more than 10% VDD, how big should we make CL
(d) What is the maximum number of transistors that can be connected in series to M1 and
M2 (including M1 and M2, excluding M0) if the output should not fall below 0.5V
during the evaluate phase? Assume that each one of the new transistors has the same
intrinsic capacitance (to ground) as M1 and M2 (C=5fF).
(e) Now there is a static CMOS inverter with VM=1.5V attached to Vo. Also, node V has
a constant current leakage of 1nA. Ignore charge-sharing (C1 = C2 = 0F), how long could
Vo stay valid, such that the inverter will output the correct result.