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International Journal of Advanced Research in Engineering and Technology
(IJARET)
Volume 7, Issue 4, July-August 2016, pp. 17–29, Article ID: IJARET_07_04_003
Available online at
http://www.iaeme.com/IJARET/issues.asp?JType=IJARET&VType=7&IType=4
ISSN Print: 0976-6480 and ISSN Online: 0976-6499
© IAEME Publication
BI-DIRCTIONAL THREE-LEVEL FRONTEND CONVERTER FOR POWER QUALITY
IMPROVEMENT
P. N. Tekwani
Senior Member–IEEE
Department of Electrical Engineering
Institute of Technology,
Nirma University, Ahmedabad - 382481, India
M. T. Shah
Department of Electrical Engineering,
Institute of Technology,
Nirma University, Ahmedabad - 382481, India
ABSTRACT
Multi-level converters are intensively used in various high-power
applications like induction motor drive, wind farm integration, HVDC
transmission etc. This paper presents three-phase three-level flying capacitor
converter as front-end topology with current error space phasor based
hysteresis controller applied to it. The controller is self-adaptive in nature,
and detect the vector, region and sector based on the position of reference
voltage vector. This keeps current error space phasor within the prescribed
hexagonal boundary. During the emergencies, proposed controller takes the
converter in overmodulation mode to meet the load demand and once the need
is satisfied, controller brings back the converter in normal operating range.
Simulation results are presented to validate behaviour of controller to meet
the said contingencies. By assuring the switching of only adjacent voltage
vectors, the proposed controller is able to eliminate the random switching as
observed in case of conventional hysteresis controller. Capacitor voltage
unbalance is the major limitation of flying capacitor converters. To overcome
the same, capacitor voltage balancing scheme for three-level flying capacitor
front-end converter is also designed and simulated under various dynamic
conditions. Results of unity power factor and low total harmonic distortion
(THD) in grid current are presented under various steady state and dynamic
conditions to validate the performance of the proposed controller.
Key words: Current Error Phasor; Current Controller; Front-End Converter;
Three-Level Converter, Total Harmonic Distortion; Unity Power Factor
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P. N. Tekwani and M. T. Shah
Cite this article: P. N. Tekwani and M. T. Shah, Bi-Dirctional Three-Level
Front-End Converter For Power Quality Improvement. International Journal
of Advanced Research in Engineering and Technology, 7(4), 2016, pp 17–29.
http://www.iaeme.com/IJARET/issues.asp?JType=IJARET&VType=7&IType=4
1. INTRODUCTION
IGBT based two-level converters as active front-end converter are very popular due to
their bi-directional power flow capability, which is required by many industrial
applications like grid integration of renewables, various motor drive applications,
micro grid, uninterruptable power supply (UPS) etc. [1,2,3]. However, for high-power
industrial applications, two-level converters require higher forward and reverse
voltage blocking capacity i.e. higher switch rating, which puts limitations on
switching frequency and cost of the overall system [4]. Multi-level converter as frontend topology offers advantages of bi-directional power flow capability, reduced
device rating and lower device stress, which makes them suitable for high-power
applications [5]. Most of the high-performance converters employ current controlled
PWM (CC-PWM) techniques for fast dynamic response [6]. Hysteresis current
controller are easy to implement and offers good dynamic response. But on the other
hand, this controller suffers from drawbacks as random switching of voltage vectors,
limit cycle oscillation, overshoot in current error and random switching of voltage
vectors [7,8]. To overcome the said limitations of conventional hysteresis controller,
current error space phasor based hysteresis controller is proposed in this paper to
control three-level flying capacitor (FC) the front-end converter (FEC) with capacitor
voltage balancing scheme. Proposed technique enables the use of zero voltage vector
along with eighteen active voltage vectors of the front-end converter which helps in
avoiding random switching. Simulation analysis of operational range of three-level
converter, including overmodulation region, is analysed and presented in this paper.
Results for unity power factor and low total harmonic distortion (%THD) in grid
current are reported in presented work. The control strategy is versatile, and hence can
be applied any three-level converter topology used for FEC.
2. ANALYSIS OF FRONT-END CONVERTER WITH PROPOSED
CONTROLLER
The space vector based hysteresis current controllers use the concept of the current
error space phasor, which represents the combined effect of the current errors in the
individual phases [9]. The block diagram of proposed current error space phasor
based controller for three-level FEC is as shown in fig. 1. To make the input current
sinusoidal in waveshape with low harmonics distortion, voltage control loop and
current control loop are designed. In the outer voltage control loop, reference dc-link
Vdcref is compared with actual dc-link voltage Vdc and then that voltage error is
processed through Proportional Integral (PI) controller. The output of PI controller is
then multiplied with envelope of grid voltage to take corrective actions to maintain
the dc-link voltage constant at set value, by generating adequate reference current for
each phase. Generated reference currents are again compared with actual grid current
of phase – A, B and C respectively. In space phasor based hysteresis controller,
current errors are monitored along three axes j , j and j which are 120° apart and
perpendicular to the A, B and C phase respectively [10].
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Bi-Dirctional Three-Level
Level Front-End
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2.1. Principle of Current Error Space Phasor based Hysteresis Controller
For Front-End
End Converter
The current error space phasor is kept within a hexagonal boundary by applying a
suitable converter voltage vector among the three adjacent voltage vectors for the
given position of supply voltage vector. This will bring-in the current error space
phasor
Figure 1 Control and power
ower block schematic of the proposed converter
whenever it hits the hexagonal boundary. The space phasor structure of three-level
three
converter has 19 voltage vectors , and and
and 24 triangular sectors with
different redundancies in switching states for generating the same number of voltage
b
vectors based on iselected
converter topology.
The three-phase
phase supply voltage vector ‘ ’ and three-phase
phase supply current vector
‘ ’, are defined in (1) and (2), respectively. The reference current space phasor ‘i*’
and current error space phasor ‘Δi’
‘
can be defined as (3) and (4) respectively [11].
[1 If
Δia, Δib and Δic are the instantaneous current errors along the A, B and C phases
respectively, then the current error space phasor can be viewed as the vector sum of
these individual current errors as in (5).
The voltage equation for the FEC can be written as shown in (6),
(6), neglecting the
internal resistance of inductor and line conductors. Substituting (4)) in (6) gives (7).
The
he converter reference voltage vector ∗ can be expressed as shown in (8), when the
supply current vector will be same as reference current vector i*. Hence, converter
voltage vector can be written as shown in (9). If the converter voltage vector,
equals to ∗ at every instant, the actual supply current will be same as the
reference current, without any deviation. But since the converter can generate only
one of the nineteen distinct voltage vectors ( to
, and
, it would
wou result in a
∗
current error phasor deviation based on (10). For a desired , the Δi
Δ moves in
different directions for different converter voltage vectors, as reflected from (11).
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P. N. Tekwani and M. T. Shah
=
+
(1)
+
Where,
= $ + $% +
&∗ = $ ∗ + $ ∗ +
(2)
$∗
(3)
(4)
∆& = ∆$ + ∆$ +
∆$
(5)
*
+
*+
(6)
d∆&
*&∗
+ L)
+
dt
*+
(7)
= L)
*&∗
+
*+
(8)
= L)
d∆&
+
dt
∗
*∆&
=
*+
−
∗
= L)
= L)
∗
L)
!"
#
$
− &∗
∆& =
=
*∆&
=
*+
−
L)
(9)
(10)
∗
(11)
2.2. Region and Sector Detection Logic
To make the appropriate selection of sector and region, proposed controller uses two
sets of comparators and two look-up tables. Based on (11), current error space phasor
can take movement along GI, GK or GJ depending on the switching of voltage vector
, , or
respectively when ∗ is in sector-7 having a position as OG, as shown in
fig. 2(a).
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Level Front-End
Front End Converter For Power Quality Improvement
(b)
(a)
Figure 2 (a) Voltage space phasor structure of the three-level
level FEC, (b) Regions for odd and
even sectors
Similarly, when ∗ having position of OH in sector-8,
8, the current error space
phasor moves in one of the directions
direction HK, HL or HJ based on switching of voltage
vector , , - or
respectively. This is applicable to all odd and even sectors of
respectively.
three-level
level voltage space phasor structure. There will be the triangular boundary
∆XYZ
XYZ for odd sectors and ∆ X/ Y/ Z2 for even sectors as shown in fig. 2(b) [12]. ∆XYZ
and ∆ X/ Y/ Z2 are further divided in to three regions as R1, R2 and R3 for odd sector and
222
2222 and 22
R6 , R
R228 for even sectors, as reflected in fig. 2(b). To detect the region,
comparators
omparators are placed on all the six axis j , j , j , j , −j and j to make the
boundary equidistant
uidistant along all sides and to keep the current error in prescribe limit.
This eventually leads to overall hexagonal boundary for current error space phasor.
phasor
As per the comparator status of respective axis, region is detected to select appropriate
voltagee vector, which brings the current error space phasor back in to hexagonal
boundary.
The second pair of comparators,
comparators which are placed little further from the first pair
of comparators along all six axis, detect the sector change. Whenever ∗ crosses from
one sector to the next sector,
secto the current error phasor increases along the particular
axis, which is perpendicular to the boundary of those sectors.
sectors This is identified from
the status of the outer comparators and look-up
look
table as shown in Table – 1 [13]. If ∗
crosses from sector 1 to sector 2, current error increases in the direction of thej
the axis,
which is perpendicular to the boundary of sector 1 and sector 2. When current error
phasor hits the outer boundary placed at j axis,, sector change is detected by the status
of outer comparator. A look-up
look up table created with this logic is shown in Table – 1.
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Table 1 Sector identification through look-up table and outer comparator
Sector
From
The direction in which current error increases and turns
ON the outer comparator and corresponding new sector to
be considered
j
j
j
j
j
j
1
*
8
2
*
*
*
*
*
*
11
3
*
3
4
*
14
*
*
*
4
*
*
*
*
17
5
5
20
6
*
*
*
*
6
*
*
*
1
*
23
23
*
24
6
8
*
*
*
*
*
‘*’ means continue with present sector.
7
*
*
2
24
3. CAPACITOR VOLTAGE BALANCING SCHEME
Proposed controller is implemented on three-level flying capacitor topology as shown
in fig. 3(a). The switching states for the one leg of selected topology are as shown in
Table – 2, in which ‘1’ indicates ON status of the switch and ‘0’ indicates OFF status
of the switch. Flying capacitor topology suffers from capacitor voltage unbalance and
same is also observed during the simulation analysis. As shown in Table – 2, this
topology has two redundant switching states for zero voltage, which result in to the
charging and discharging of inner capacitors. Equivalent circuit of charging and
discharging of inner capacitor C3 during these zero switching states for phase – A is
as shown in fig. 3(b) and 3(c) respectively for particular direction of converter
current. Exactly opposite effects will be produced by these states on charge of
capacitor C3 if the direction of converter current reverses. Making use of these zero
voltage switching states, capacitor voltage balancing scheme is designed and
proposed in this paper.
Actual voltage at inner capacitor C3 is sensed as Vc3 and compared with half of the
9
dc-link voltage ( :;<=> ). The error ΔVc3 is processed to voltage hysteresis controller
having band of ± 1 V as shown in fig. 3 (d) for the selection of zero voltage vector.
For the given direction of converter current, if ΔVc3 is greater than 1 V, which
indicates discharging of capacitor C3, so switches S12 and S14 are switched ON to
make capacitor
C3 to charge as shown in fig. 3(b). Same way, when capacitor C3 is overcharged,
i.e. when ΔVc3 becomes negative, then switches S11 and S13 are switched ON to make
capacitor C3 to discharge as per fig. 3(c). The same approach is used to maintain
capacitor voltage of other two inner capacitors C4 and C5.
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Level Front-End
Front End Converter For Power Quality Improvement
(b)
(a)
(c)
(d)
level flying capacitor converter,
converter, (b) Equivalent circuit to make inner
Figure 3 (a) Three-level
capacitor charged by turning ON S12 and S14, (c) Equivalent circuit to make inner capacitor
discharged by turning ON S11 and S13, (d) Capacitor voltage balancing scheme.
scheme
Table 2 Switching table of three-level flying capacitor converter
onverter
VaN
+Vdc/2
0
0
-Vdc/2
S11
1
0
1
0
S12
1
1
0
0
S13
0
0
1
1
S14
0
1
0
1
4. SIMULATION RESULTS AND
A
DISCUSSIONS
Following parameters are taken for the simulation analysis:
analysis
Input supply voltage = 230 V (peak phase voltage),
Line side boost inductance = 1 mH,
Resistive load = 100 Ω,
DC-link
link capacitor = 4700 µF.
To check the behavior of the proposed
p
controller under variable loading
conditions, considering constant dc-link
dc link voltage requirement of load as 650 V, load
change is given at 0.2 s and 0.4 s as shown in fig. 4 (a). Output voltage remains
constant with less than 1% ripple voltage which depicts good load regulation offered
by the proposed controller. Converter voltage maintains its waveform during the load
loa
change also as shown in fig. 4 (b) which demonstrates
tes the robustness of proposed
controller. At supply side, power factor is maintained at unity irrespective of load
variation at output side as shown in fig. 4 (c). Adopted capacitor voltage balancing
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scheme is able to maintain the capacitor voltage at ? ⁄2 during variable loading
conditions also as shown in fig. 4 (d). To satisfy the load demand and to maintain the
input - output power balance, reference current rises with increase in load as reflected
in fig. 4 (e). The proposed controller keeps the current error space phasor within
hexagonal boundary and offers the line side current %THD 2.73% as shown in fig. 4
(f).
Switching ‘ON’ and ‘OFF’ of heavy load, causes sag and swell at grid side. To
demonstrate performance of proposed controller under this situation, sag and swell are
created at line side as shown in fig. 5 (a). Under this situation also, the proposed
controller is able to maintain unity power factor with sinusoidal waveshape as shown
in fig. 5 (b). The sector change logic automatically adjusts time need for each sector
to satisfy the load demands, as shown in fig. 5 (c), sector change pattern is differ in
terms of time spent by reference voltage vector in each sector during the sag and swell
at grid side. During the sag and swell also, load is able to get constant dc-link voltage
as shown in fig. 5 (d). The proposed controller is able to satisfy the load demand by
operating converter in overmodulation if the dc-voltage is reduced suddenly. To
simulate this situation, Vdcref is suddenly reduced from 650 V to 400 V with same
loading condition.
(b)
(a)
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(c)
(d)
Three-phase reference currents
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(f)
(e)
Figure 4 Controller behavior under variable loading conditions: (a) During variable loading,
output voltage is maintained at constant value, (b) Converter voltage waveform during
variable load, (c) Unity power factor is maintained during load variation, (d) Capacitor
voltage maintained at Vdc/2 with selected capacitor voltage balancing scheme, (e) Three-phase
reference current during load change to satisfy the load demand, (f) Hexagonal boundary
form by current error space phasor and %THD of grid current.
To meet this contingencies, thee-level converter started operating in
overmodulation as seen from fig. 6 (a) with unity power factor at line side as shown in
fig. 6 (b). Many practical applications require bi-directional power flow capability of
the converter. IGBT based three-level flying capacitor converter is simulated to check
the said behavior of the proposed controller during reverse power flow condition.
During reverse power flow, the output current phase becomes negative (i.e., in reverse
direction) from 0.1 s to 0.2 s as shown in fig. 7 (a). Supply current and voltage are still
in phase but with the phase shift of 180° as expected, as shown in fig. 7 (b).
(b)
(a)
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(c)
(d)
Figure 5 (a) Undervoltage and overvoltage created at line-side, (b) Unity power factor is
maintained at supply side during sag and swell conditions (c) Sector change logic
automatically adjusted due to magnitude variation of supply voltage (d) Converter voltage
and constant dc-link voltage during this situation.
(a)
(b)
Figure 6 (a) Three-level converter operating in overmodulation during contingencies, (b)
Unity power factor at line-side during overmodulation.
(a)
(b)
Figure 7 (a) DC output current during reverse power flow condition, (b) Unity power factor
is maintained at line-side with phase shift of 180° during reverse power flow.
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5. CONCLUSION
Proposed current error space phasor based hysteresis controller is simulated and
analyzed with three-level flying capacitor converter with capacitor voltage balancing
scheme. The proposed capacitor voltage balancing scheme is able to maintain the
capacitor voltage at desired level under dynamic conditions also, and results are
presented to validate the same. The proposed controller is able to maintain unity
power factor at line side and %THD is 2.73%, which less than 5%, in grid current
under variable line side and load side conditions. It also deliver constant output
voltage with ripple voltage less than 1%, which demonstrates good load regulation
offered by the controller under dynamic conditions too. During the emergencies, the
controller automatically takes the converter in to the overmodulation region to meet
the load demand and brings back the converter in the normal linear range of
modulation once the need is satisfied, which demonstrate the self-adaptive nature of
proposed controller. Under all dynamic and steady state conditions, the proposed
controller assures switching of only adjacent voltage vectors, which eliminate the
random switching of voltage vectors as observed in case of conventional hysteresis
controller.
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