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ECE 3110: Introduction to Digital Systems
Chapter 6
Combinational Logic Design Practices
Circuit Timing
Previous…
 Drawing Layouts
Flat
Hierarchical
 Buses
Signal/bus flags for inter-pages
 Complete Schematic Diagrams
IC types
Reference designator (unit number)
Pin numbers
 Pinouts for SSI ICs in standard DIP (74 series)
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Timing Diagrams
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A timing diagram illustrates the logical behavior of signals as a function of
time.
Causality: which input transitions cause which output transitions.
Different through a circuit paths may have different delays.
A signal timing diagram may contain many different delay specifications.
Delay depends on: Internal circuit structure, Logic Family type, Source Voltage,
Temperature
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Timing Diagram for Data signals and Buses
DATA IN
WRITE_L
CLEAR
COUNT
Logic
Circuit
(Memory)
Logic
Circuit
(Counter)
DATAOUT
t1
STEP[7:0]
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Propagation Delay
 The delay time between input transitions and the output transitions
due to the propagation delay of the logic gates.
 tp of a signal depends on the signal path inside the logic circuit
 For a logic gate tpLH may not equal tpHL, (e.g. in TTL)
 tp is specified in the manufacturer data sheets of the IC’s
 Example: The delay for 74x00 in nanoseconds for TTL & CMOS
Families: LS, HCT,AHCT
 To find tp for a signal, add the propagation delays of all gates along
the path of the signal
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Timing specifications
 A timing table may specify a range of values for each delay for a
device.
 Maximum: longest possible delay
 Typical: under near-ideal condition
 Minimum: smallest. Many manufactures don’t specify this values in
most moderate-speed logic families (74LS,74S TTL). Set to zero or
1/4~1/3 of typical delay if not specified.
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Delays for selected SSI parts
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Delays of SSI parts
 All inputs of an SSI gate have the same
propagation delays to the output.
 TTL gates usually have different delays for LOWto-HIGH and HIGH-to-LOW transitions, while
CMOS gates usually don’t.
 The delay from an input transition to the
corresponding output transition depends on the
internal path taken by the changing signal.
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Delays for selected MSI parts pp. 366
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Timing analysis
Study logical behavior of SSI/MSI devices
Worst-case delay:
Maximum of tpLH and tpHL for each component
Sum of the worst-case delays through the
individual components, independent of the
transition direction and other conditions.
Tools
CAD and simulators: Xilinx, MAXPLUS
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Exercise Example:
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Next…
Combinational PLDs
Reading Wakerly CH-6.3,6.4
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