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Transcript
4. Logic Gates 3 ï´ 3NAND 2 ï´ 4NAND 1 ï´ 8NAND 2 ï´ 2OR 4 ï´ 2XOR ï¼ ÐÐ4 ÐÐ1 ÐÐ2 ÐÐ1 ÐÐ5 ï¼ 10 20 30 32 86 ï¼ 5 â Package Ð Plastic DIP (dual in line package) with vertical pins Glass-metal DIP with vertical pins Ceramic DIP with vertical pins J Flat pack Nonpacked M C Ð,Ð Ð N D W Typical single-gate performance specifications are named in the table below. Family Power dissipation mW/gate TTL Standard (74) 10 H (74H) 25 L (74L) 1 S (74S) 20 AS (74AS) 8 LS (74LS) 2 ECL (100K) 50 I2L 0.01 â 0.1 MOS TL 0.5 CMOS TL C (4000B) 0.001/1kHz HC (74HC) 0.005/1kHz Propagation Speed-power delay product ns pJ 10 6 30 5 4 10 1.2 100 â 10 100 100 150 30 100 30 20 60 1 50 â Noise immunity V 0.8 0.8 0.8 0.5 0.5 0.5 0.3 0.05 2â3 1â2 Number of logic inputs 2â5 Pyramiding factor 10 2â5 2â3 2â5 2â5 10 â 20 3â5 50 50 100 25 The values of parameters in the table are rather tentative; it is not necessary to memorize them, but it is necessary to know which family is the best according the selected parameter and which family is the bad one. 48
