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4. Logic Gates
In the third circuit of NMOS switch depletion-mode
+E
NMOSFET is in the role of transistor-load VT1. This transistor
VT1
is always ON or slightly ON.
UOUT
Let low level is in input of the switch, and transistor VT2
is OFF. Let VT1 is ON. Then all power supply voltage E falls
VT2
on the very large resistance of closed VT2, and UOUT  U1 
E. UOUT  UGVT1  E. But USVT1  E, and control voltage of UIN
VT1 USG  0. Output characteristics of depletion-mode
NMOSFET show that in this case VT1 is saturated. When USG
 0 and USD  0, operating point of the transistor is in an I
D
initial part of the characteristics where output resistance of
UGS  0
transistor is very small. The presumption that VT1 is ON is
confirmed.
– 0.5 V
Let high level is in input of the switch, and transistor
–1V
VT2 is ON, and UOUT  U0. Let VT1 is only slightly
open, and voltage drop on this transistor is the great part of
– (E–U o)
E: UDSVT1  E – U0. The same voltage is the control
E–Uo U
voltage of transistor VT1: UGSVT1  E – U0. This voltage 0
DS
nearly closes the transistor, but it can not make the
transistor OFF, because this voltage is created by current through this transistor. Output
characteristics of transistor show that in this case output resistance of transistor is very large.
The presumption that VT1 is only slightly ON is confirmed.
Analysis of three switches' circuits shows that the term "passive load" is rather
conditional: though transistor-load is not directly controlled by logic signals in input of switch,
these signals change operation point and resistance of the transistor.
Switch with active load – CMOS switch
In CMOS (complementary MOS) logic family all switches are made from complementary pairs
of enhancement-mode n-channel and p-channel MOSFETs. Input signals control both
transistors of the gate, both transistors are active.
+E
Let low level U0  0 is in input of the switch, and
VT1
transistor VT2 is OFF. p-channel VT1 is ON, because its control
UOUT
voltage UGSVT1  – E. Then all power supply voltage E falls on
VT2
the very large resistance of closed VT2, and
UOUT  U1  E.
Let high level U1  E is in input of the switch, and U
IN
transistor VT2 is ON. p-channel VT1 is OFF, because its control
voltage UGSVT1  0. Then all power supply voltage E falls on the
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4. Logic Gates
very large resistance of closed VT1, and UOUT  U0  0.
The merits of the CMOS switch are:
1. In both states (when input signal is 0, and when input signal is 1) one of two connected
in series switch transistors is OFF; there is no current through these transistors and there is no
power consumption.
2. Low level in output always is 0 V, it does not depend on the resistance of channel; it
means that dimensions of channels and dimensions of transistors can be minimal; it
compensates increasing square, when transistors with both n- and p-channels are formed.
3. Logic swing has highest possible value – it equals E; large logic swing guarantees
great interference immunity.
4. In NMOS or PMOS logic power supply voltage E  (3 – 4) Uthr ; in CMOS logic E 
Uthr (we will make sure of that soon); it means that according power supply voltage CMOS
logic is compatible with TTL logic.
Now we will analyze the transfer characteristics of CMOS switches. There are three
possible versions and they differ in value of power supply voltage.
Take notice that threshold voltage of VT1 always starts from the value of E.
When E  2Uthr, there is a region of transfer characteristic, when both transistors are ON.
It means that during short switching time large pulse of power supply current flows through
both transistors. These pulses charge and discharge
UOUT
E  2Uthr capacitances with high speed, therefore the gates with
VT1 and VT2
such power supply voltage are fast, but not economical
are ON
U1 E
in power consumption.
When E  2Uthr, there is no region with both
VT2 is ON,
transistors ON. During short switching time both
VT1 is OFF
transistors are OFF. It means that capacitances are
E/2
charged and discharged by very small reverse currents
VT1 is ON,
VT2 is OFF
of PN junctions in cut off state. The gates with such
power supply voltage are slow, but very economical in
UIN
power consumption.
U0  0
U1  E
E/2
The gates with
Uthr VT1
Uthr VT2
,
E  2Uthr
power supply voltage E U OUT
 2Uthr have ideal U 1 E
U OUT V T1 and V T2 Uthr  E  2Uthr
interference immunity:
V T 2 is ON ,
are OFF
U 1 E
V T2 is ON ,
V T1 is OFF
U0  0
U thrV T1
44
10
E/2
U1  E
U thrV T2
01
Uint.im.  Uint.im.  E/2.
V T1 is ON ,
V T2 is OFF
U IN
4.2.2.
PMOS
Logic
V T 1 is OFF
E/2
V T 1 is ON ,
V T 2 is OFF
NMOS
and
Transistor U 0  0
U thr
V T2
U IN
U thr
V T1
E/2
U1  E
4. Logic Gates
NMOS and PMOS gate circuits differs only in polarity of power supply voltage and type of
MOSFETs. Therefore it is enough to analyze one version of logic, for example, NMOS.
NMOS transistor logic is more popular than PMOS because of:
– mobility of electrons - majority charge carriers in n-channel – is 3 times greater than
mobility of holes in p-channel, and NMOS logic is faster than PMOS;
– polarity of power supply voltage for NMOS logic is the same as for standard BJT
gates.
Circuits of MOSTL gates are the same as circuits of DCTL gates with BJTs. Basic gate
of MOSTL is NOR gate. The difference from circuit of DCTL NOR gate is such, that in
MOSTL common load in collectors' circuit is not resistor, but transistor-load. Every version of
analyzed passive transistor-loads is possible. In circuit of 2NOR gate the version of transistorload with UG  EG  E + Uthr is applied. The circuit of gate operates like the corresponding
DCTL gate and like the corresponding MOSFET switch.
The main merits of MOSTL:
1. Large scale integration because of
– there is no isolated areas for transistors;
+ EG
– no resistors.
+E
2. Low price as a result of large scale integration
VT1
and simple fabrication technology.
3. Very large input resistance and absence of input
A+ B
current guarantees
VT2
VT3
– good logic swing;
A
B
UIÐ
– good interference immunity;
U
UIN2
– large pyramiding factor.
IN1
The main disadvantages of MOSTL:
1. MOS transistors and MOSTL gates are not as
fast as BJTs and BJTs gates.
2. Large value of power supply voltage and great logic swings make MOSTL
incompatible with standard logics with BJTs.
3. The silicon dioxide layer, that isolates the gate from the substrate, is so thin that it can
be burned-through from electrostatic discharges.
4.2.3. CMOS Transistor Logic
It is useful to memorize the rule: if logic transistors of the gate are connected in parallel,
complementary transistors must be connected in series; and the other way round – if logic
transistors of the gate are connected in series, complementary transistors must be connected in
parallel. The circuit of 2NOR gate is formed according this rule.
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4. Logic Gates
If there is logic 1 in one input of 2NOR gate at
least, n-channel logic transistor in this input is ON,
V T4
and its complementary p-channel transistor is OFF.
The logic 0 is in the output.
When there are logic 0s in both inputs, logic
V T3
B
transistors VT1 and VT2 are OFF and both
U IN 2
complementary transistors VT3 and VT4 are ON.
V T1
A + B Then and only then there is logic 1 in the output.
V T2
The main merits of CMOSTL:
U OUT
A
1. When logic levels in input are stable, gate
operates in static mode, and it does not consume
U IN 1
power supply energy in this mode. The current flows
through complementary pair of transistors only in
the moment when logic signals in inputs change logic level in gate's output, and only in the
case, when power supply voltage E  2Uthr. It means that power consuming of CMOSTL gate
depends on the power supply voltage and on the clock frequency of gate operating. When E 
2Uthr , and the clock frequency is not very high, CMOSTL is the most economical logic.
2. Scale of integration of CMOSTL is slightly less in comparison with MOSTL. The
reason is such that in CMOSTL both n-channel and p-channel MOSFETs are formed. Scale of
integration of CMOSTL is nearly the same as I2L, and much more than scale of integration of
other logics with BJTs.
3. Large scale of integration and simple technology of fabrication defines low price of
CMOS family IC.
4. U0  0, U1  E, maximum possible logic swing and in some cases maximum possible
interference immunity.
5. CMOSTL is compatible with standard logics with BJTs in value of power supply
voltage.
The main disadvantage of CMOSTL in comparison with BJT logics is less operation
speed; speed of operation decrease, when power consumption decrease.
+E
4.3. Comparing Logic Families
Digital system designers have a wide variety of digital logic to choose from. The main
parameters to consider include operating speed, power dissipation, availability, type of
functions, interference immunity, pyramiding factor. First and foremost, however, are the basic
speed and power consumption.
Now we will start from the marking of ICs, and then we will compare the parameters of
the most popular families of ICs.
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4. Logic Gates
In Russia
In USA
K П 133 ЛА1
MC 74 LS 00 N
2
5
3
2
1
4
3
4
5
1 – Producer
For example: F – Fairchild
KS – Samsung
LR – Sharp
MC – Motorola
MN – Panasonic
P – Intel
TI – Texas Instruments

2 – Usage
K
–
Commercial
74
Permissible ambient temperature from 0 till +75oC
Special, military
54
Permissible ambient temperature from –50 iki +125oC
3 – Family
133, 135
130, 131
134
1102
530, 531
533, 555
1530
1533
176, 561, 564
1561, 1564
Standard TTL
High speed TTL
Advanced Shottky TTL
Advanced TTL
Shottky TTL
Low power Shottky TTL
Advanced Shottky TTL
Advanced low power Shottky TTL
Complementary MOS TL (CMOS)
High speed CMOS
HC
Compatible with TTL CMOS
The first digit – additional information:
1, 5, 7 – semiconductor IC;
2, 4, 8 – hybrid; 3 – another
–
H
L
A
S
LS
AS
ALS
C
CT
4 – Logic function
ЛА3
ЛЕ5
ЛН1
ЛИ1
4  2NAND
4  2NOR
6  NOT
4  2AND
00
02
04
08
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4. Logic Gates
3  3NAND
2  4NAND
1  8NAND
2  2OR
4  2XOR

ЛА4
ЛА1
ЛА2
ЛЛ1
ЛП5

10
20
30
32
86

5 – Package
Р
Plastic DIP (dual in line package)
with vertical pins
Glass-metal DIP with vertical pins
Ceramic DIP with vertical pins J
Flat pack
Nonpacked
M
C
А,И
Б
N
D
W
Typical single-gate performance specifications are named in the table below.
Family
Power
dissipation
mW/gate
TTL
Standard (74)
10
H (74H)
25
L (74L)
1
S (74S)
20
AS (74AS)
8
LS (74LS)
2
ECL (100K)
50
I2L
0.01 – 0.1
MOS TL
0.5
CMOS TL
C (4000B)
0.001/1kHz
HC (74HC) 0.005/1kHz
Propagation Speed-power
delay
product
ns
pJ
10
6
30
5
4
10
1.2
100 – 10
100
100
150
30
100
30
20
60
1
50
–
Noise
immunity
V
0.8
0.8
0.8
0.5
0.5
0.5
0.3
0.05
2–3
1–2
Number
of logic
inputs
2–5
Pyramiding
factor
10
2–5
2–3
2–5
2–5
10 – 20
3–5
50
50
100
25
The values of parameters in the table are rather tentative; it is not necessary to memorize
them, but it is necessary to know which family is the best according the selected parameter and
which family is the bad one.
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4. Logic Gates
CONTROL QUESTIONS AND PROBLEMS
4.1. Bipolar Transistors Logic Gates
4.1.1. Formulate the requirements for switches. How do BJT switches fulfill these requirements?
4.1.2. Draw a simple circuit of BJT switch and explain its operation.
4.1.3. Draw a load line of BJT switch on the family of BJT output characteristics. Explain possible regimes of
operation of BJT in switch circuit.
4.1.4. Show the values and polarity of voltages between electrodes of BJT in regime of saturation.
4.1.5. What power is dissipated on BJT, when it operates in cut off and saturation regimes.
4.1.6. Explain the external and internal processes, that determine a speed of operation of BJT switch.
4.1.7. Draw a transfer characteristic of BJT switch. What parameters of switch are determined by this
characteristic?
4.1.8. Draw a circuit of DCTL gate 2NOR. Explain the operation of unloaded gate.
4.1.9. Explain the values of U1 and U0 in the output of loaded
U 0= 1V , U 1= 4V
1k 
DCTL gate.
A
A
F1
1k 
4.1.10. Explain the main disadvantages of DCTL.
B
B
4.1.11. Fill in volts the truth tables of the circuits on the figure.
1k 
C
2k 
F2
2k 
C
4.1.12. Draw a circuit of DTL gate 3NAND and explain its
operation.
a
4.1.13. Explain destination of diodes VT4 and VT5 in the circuit
of DTL gate. Are both of these diodes indispensable?
4.1.14. Name and explain advantages and disadvantages of DTL comparing with TTL.
4.1.15. Draw the circuit of the most simple TTL gate 3NAND and explain it's operation.
4.1.16. Explain the main advantage of TTL gate with totem-pole
output stage.
R2
4.1.17. Fill in the table of voltages in different points of the
standard TTL gate on the figure for two cases:
R1
V T1 d
V T2
a) for Ua  0,2 V;
b) for Ua  Ub  Uc  3,6 V.
a
e
4.1.18. Calculate the input currents of TTL gate on the figure for bc
two cases:
g
a) for Ua  0,2 V;
b) for Ua  Ub  Uc  3,6 V.
4.1.19. Calculate the highest possible value of output current of
TTL gate on the figure when there is high logic level at gate
output. R3  100  .
b
\b
+ 5V
R3
V T3
j
h
k
V TD4
V
f
4.1.20. Name and explain advantages and disadvantages of Schottky TTL comparing with standard TTL.
4.1.21. Draw a topology and cross-section of Schottky BJT – integrated device.
4.1.22. Explain the reasons that determine the maximum speed of operation of ECL.
4.1.23. Are the emitter followers in outputs of ECL gate indispensable?
49
4. Logic Gates
4.1.24. Explain, is it possible to make the IIL gate from discrete components.
4.1.25. Explain the origin of name of Integrated Injection Logic.
4.1.26. Explain the reasons that determine the maximum scale of integration of ECL.
4.2. Field Effect Transistors Logic Gates
4.2.1. Draw graphic symbols of all types of FET's. Name all electrodes of FET. Name the similar electrodes of
BJT.
4.2.2. When the transistor-load of MOSFET switches is active, and when it is passive?
4.2.3. Draw a circuit of MOSFET switch with passive load for case when voltage of gate of transistor-load
UG  +E  UD. Explain operation of the switch when input voltage is high, and when input voltage is low.
Draw a transfer characteristic of the switch.
4.2.4. Draw a circuit of MOSFET switch with passive load for case when voltage of gate of transistor-load
UG  + EG  E +Uthreshold . Explain operation of the switch when input voltage is high, and when input voltage
is low. Draw a transfer characteristic of the switch.
4.2.5. Draw a circuit of MOSFET switch with passive load when transistor-load is MOSFET with built in
channel. Explain operation of the switch with high input voltage, and with low input voltage. Draw a transfer
characteristic of the switch.
4.2.6. Draw a circuit of CMOS switch and explain it's operation.
4.2.7. Draw and explain transfer characteristics of CMOS switch for three cases:
a) E  UthrVT1 + UthrVT2 ,
b) E  UthrVT1 + UthrVT2 ,
c) E  UthrVT1 + UthrVT2 .
4.2.8. Draw a cross-section of CMOS switch – integrated device.
4.2.9. Draw a circuit of any nMOS gate 3NOR and explain it's operation.
4.2.10. Draw a circuit of nMOS gate 2NAND and explain it's operation.
4.2.11. Name and explain the main advantages and the main disadvantages of MOS gates comparing with BJT
gates.
4.2.12. Name and explain the main advantages and the main disadvantages of nMOS gates comparing with
pMOS gates.
4.2.13. Draw a circuit of CMOS gate 3NOR and explain it's operation.
4.2.14. Draw a circuit of nMOS gate 3NAND and explain it's operation.
4.2.15. Name the main advantages of CMOS gates.
4.3. Comparing Logic Families
4.3.1. Explain the abbreviations in the marks of IC devices: H, L, A, S, LS, AS, ALS, C, HC, HCT.
4.3.2. Which parameter of IC devices characterizes their properties in the best way?
4.3.3. Explain sense of the parameter "static noise immunity". What form of transfer characteristic ensures the
best noise immunity.
4.3.4. Write in line standard TTL, Schottky TTL, ECL, IIL, MOSTL and CMOSTL, starting from the best one,
according such parameters:
a) power dissipation;
b) delay time;
c) noise immunity.
50