Download 1.2 A Programmable Device Power Supply AD5560

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Transcript
Data Sheet
AD5560
TIMING CHARACTERISTICS
HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, VREF = 5 V (TJ = 25°C to 90°C,
maximum specifications, unless otherwise noted).
Table 2. SPI Interface
Parameter 1, 2, 3
tUPDATE
t1
t2
t3
t4
t5
t6
t7
t8
t9 4
t10
t11
t12
t13
t14 5, 6
t15
LOAD TIMING
t16
t17
t18
t19
DVCC = 2.3 V
to 2.7 V
600
25
10
10
10
15
5
5
4.5
40
1.5
280
25
400
250
45
30
DVCC = 2.7 V
to 3.3 V
600
20
8
8
10
15
5
5
4.5
35
1.5
280
20
400
250
35
30
DVCC = 4.5 V
to 5.5 V
600
20
8
8
10
15
5
5
4.5
30
1.5
280
10
400
250
25
30
Unit
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs max
ns max
ns min
µs max
ns min
ns max
ns max
Description
Channel update cycle time
SCLK cycle time; 60/40 duty cycle
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time
24th SCLK falling edge to SYNC rising edge
Data setup time
Data hold time
SYNC rising edge to BUSY falling edge
BUSY pulse width low for DAC x1 write
BUSY pulse width low for other register write
RESET pulse width low
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
SYNC rising edge to SDO high-Z
20
150
0
150
150
20
150
0
150
150
20
150
0
150
150
ns min
ns min
ns min
ns min
ns min
LOAD pulse width low
BUSY rising edge to force output response time
BUSY rising edge to LOAD falling edge
LOAD rising edge to FORCE output response time
LOAD rising edge to current range response
1
Guaranteed by design and characterization, not production tested.
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
This is measured with the load circuit shown in Figure 2.
5
This is measured with the load circuit shown in Figure 3.
6
Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications.
2
TIMING DIAGRAMS
200µA
RLOAD
2.2kΩ
CLOAD
50pF
VOL
TO OUTPUT
PIN
CLOAD
50pF
07779-002
TO OUTPUT
PIN
IOL
VOH (MIN) – VOL (MAX)
2
200µA
Figure 2. Load Circuit for Open Drain
IOL
Figure 3. Load Circuit for CMOS
Rev. D | Page 13 of 68
07779-003
DVCC