Download Reverse Blocking IGCTs for Current Source

ABB Semiconductors AG
Reverse Blocking IGCTs for Current Source Inverters
Reverse Blocking IGCTs for Current Source Inverters
A. Weber, T. Dalibor, P. Kern, B. Oedegard, J. Waldmeyer and E. Carroll
ABB Semiconductors AG,
5600 Lenzburg, Switzerland
Tel: +41 (62) 888-6487; Fax: +41 (62) 888-6302; e-mail: [email protected]
Abstract - Today IGCTs (Integrated Gate
Commutated Thyristors) are widely used
for different applications especially voltage
source inverters (VSIs) for which reverse
conducting and asymmetric elements with
discrete freewheeling diodes have been
developed. For current source inverters
(CSIs), reverse blocking elements are
required and to this end symmetric 6 kV
IGCTs have been developed. Using reverse
blocking IGCTs in a CSI offers significant
benefits compared to present GTO or
thyristor solutions and allows higher
inverter ratings and switching frequencies.
In addition to the semiconductor switch,
the performance of the integrated gatedriver has been adapted to the demands of
the CSI. Status feedback signals for
protection purposes and LEDs for easier
commissioning of the drive have been
incorporated and the gate-driver is
optionally available with an AC power
supply input allowing further system cost
reductions.
I. Introduction
In the past five years, IGCTs with discrete or
integrated fast recovery diodes have been
optimised
for
use
in
VSIs.
Device
improvements have been achieved by
advanced lifetime engineering techniques [1]
as well as wafer design and process control.
In contrast to the VSI, the CSI requires
symmetric devices such as the thyristors or
GTOs in use today. However, both devices
have their limitations: thyristors, requiring large
commutation capacitors, have low switching
frequencies and GTOs, with their large
snubber circuits, incur significant losses.
There are only two devices available today for
high
switching
frequency
and
quasi
snubberless operation: the IGBT and the
IGCT.
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II. Device Structure
Reverse blocking devices can be realised in
two ways. The first is symmetric wafer
processing - creating two blocking junctions on
the same silicon wafer. For thyristors and
GTOs, symmetric processing is the state-ofthe-art. The second method is the series
connection of a diode with an asymmetric turnoff device such as an IGBT [2] or an
(asymmetric) IGCT. Since CSIs are used
predominantly in Medium Voltage Drives
(MVDs), the selected device technology must
allow series connection of several devices.
Where redundancy is additionally required, a
stable short-circuit failure mode becomes
necessary [3]. For these reasons, press-pack
devices are preferred and the IGCT with its
high blocking voltage and low losses becomes
the device of choice.
Symmetric processing of the silicon does not
allow the incorporation of a buffer layer [4]
necessitating thick silicon slices for high
voltage devices which in turn leads to high
dynamic losses. While this may be acceptable
at the low frequencies used in the past, it is a
major drawback for future high voltage and
high frequency applications. Attempting to
reduce dynamic losses by lifetime reduction
leads to an increase in conduction losses.
These drawbacks can be overcome by the
series connection of discrete GCT and diode
wafers. Since both wafers can be optimised for
minimal thickness, their on-state voltage drops
versus turn-off losses are very favourable. A
further problem, the lower turn-off capability of
symmetric devices [5], is also avoided.
For applications with low currents, both GCT
and diode wafer can be encapsulated in one
press-pack device whilst, for high power
applications, it may be advantageous to use
the same wafers discretely encapsulated, thus
allowing 50% more cooling.
Nürenberg, 6, 2000
ABB Semiconductors AG
Reverse Blocking IGCTs for Current Source Inverters
III. Test circuit
A current source inverter is schematically
shown in Fig. 1. Each of the positions can be a
single switch or a series connection of several
switches with small RC snubbers for voltage
sharing.
delay, DUT2 is turned off forcing the current to
commutate to DUT1 with a di/dt given by the
snubber of DUT2 (RS, CS) and the
commutation inductances (2 x LC ). When
DUT2 is gated on again, DUT1 undergoes
reverse recovery with high di/dt given by the
commutation inductance LC (“diode operation”)
and sustains full reverse voltage.
Thus this circuit tests the devices under
conditions close to CSI operation and, in
particular, issues of timing between DUT1 turnoff and DUT2 turn-on can be investigated.
L DC
Fig. 1
Basic circuit of current source inverter.
C DC
Testing of devices in an inductively clamped
circuit based on the design of a voltage source
inverter is not satisfactory as the waveforms
are dissimilar and interpretation of results with
respect to losses, SOA etc. is problematic. For
this reason the special test circuit of Fig. 2 was
built to evaluate devices under conditions close
to those of the CSI application.
The circuit of Fig. 2 consists of DC capacitor
CDC , DC link inductance LDC , two commutation
inductances LC and two DUTs, each with RC
snubbers.
For the device 5SHZ 08F6001 rated for a
maximum turn-off current ITGQM = 800 A, the
conditions used were: LC = 3µH, Rs = 10 Ω and
Cs = 0.1 µF. The test circuit is placed in a
climatic chamber so that the DUTs can be
tested
from
–25 °C
to
125 °C.
All
measurements shown in this paper were
performed at 125 °C.
The circuit allows the investigation of turn-on
and turn-off under forward bias in position
DUT2. This mode is called “GCT operation”
because it requires gate-controlled turn-off. In
the position of DUT1 however, turn-on and
turn-off occur under negative anode-cathode
bias. This mode is referred to as “diode
operation”. These are the two commutation
modes of a CSI.
A typical measurement cycle is described
below.
Initially DUT1 and DUT2 are in the off-state.
The DC capacitance CDC is charged, DUT2 is
turned on and DUT1 blocks reverse voltage.
The current ramps up in the load inductance
LDC with low di/dt. After reaching the test
current level, DUT1 is gated on and after some
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DUT 1
RS
DUT 2
CS
LC
Fig. 2
LS
Circuit to test IGCTs in conditions close to
those of a CSI.
IV. Characteristics and Ratings
IV.1. Thermal Impedance
Detailed investigation of the thermal resistance
and impedance of a two-wafer design shows
that when the total power dissipation in both
wafers is considered, the thermal resistance is
only slightly greater than that of a single wafer
press-pack, as long as double-side cooling is
used (see Fig. 3). It is advantageous, however,
to utilise two wafers rather than just the one:
the division of diode and GCT functions in
separate wafers allows an overall reduction of
losses. Furthermore, the diode’s static and
dynamic losses are about 30 % higher than
those of the GCT and this is allowed for in the
two-wafer approach by designing such that the
diode wafer has a lower thermal resistance to
anode-side than that of the GCT to cathodeside.
The thermal model for a two-wafer device is a
little more difficult to accurately describe than
with a single thermal resistance or impedance
function. It can however be formulated exactly
by a matrix of four thermal resistance or
impedance terms, reflecting self and crossheating of the two junctions. The two selfheating terms are only marginally larger than
Nürenberg, 6, 2000
ABB Semiconductors AG
Reverse Blocking IGCTs for Current Source Inverters
0.5 x PTOTAL
IV.2. Dynamic Properties
Single wafer press-pack
-silicon wafer;
IV.2.1. Turn-off into Forward Voltage
-molybdenum
During turn-off under forward bias, the GCT
wafer sustains voltage as its current falls (both
positive). The series diode (being forward
biased) generates no losses.
Let us consider DUT2 conducting and DUT1
blocking:
Fig. 5 shows anode voltage of DUT2 rising as
anode current commutates to the snubber.
Once the anode voltage of DUT2 exceeds the
voltage of capacitor CDC, current commutates
to DUT1, (until now reverse-biased), provided
it was previously gated on.
-copper pole-piece
ANODE
CATHODE
PDIODE + PGCT (Fig. 3b) = PTOTAL (Fig. 3a)
P DIODE
PGCT
Two-wafer press-pack
For an accurate calculation of GCT junction
temperature it is necessary to know the losses
in the GCT and the diode. The exact junction
temperature of both wafers can then be
derived. For the GCT we find:
t
t
0
0
&
&
TjGCT (t) = TjGCTstart + ∫ PGCT (τ )Z
thGG( t − τ) dτ + ∫ PDiode (τ )Z thDG (t − τ)d τ
1
t
0
0
Thermal Resistance [K/W]
&
&
TjDiode ( t) = TjDiodestart + ∫ PDiode (τ) Z
thDD (t − τ)dτ + ∫ PGCT (τ )Z thGD( t − τ )dτ
PCIM
1
0
0
0
5
10
time [µ s]
Fig. 5
Turn-off of DUT2: 800 A against 3700 V
We now consider the current established in
DUT1 with the GCT receiving a small
“backporch” gate current (which keeps the
cathode-gate voltage positive). Turning on
DUT2 commutates the current from DUT1 to
DUT2 with a high di/dt, forcing reverse
recovery of DUT1. The reverse current through
the GCT will at first flow into the gate-driver
and reduce the gate-cathode voltage until the
gate cathode junction avalanche voltage is
reached and the current flows through the
device from anode to cathode. The energy loss
in the GCT wafer is, however, negligible since
the GCT gate-cathode region sustains only 20
1.0E-02
1.0E-03
1.0E-04
0.01
0.1
1
10
time [s ]
Fig. 4
0.4
IV.2.2. Turn-off into Reverse Voltage
1.0E-01
0.001
0.6
0.2
where ZthGG describes the self heating of the
GCT wafer and ZthDG describes the mutual
heating of the GCT wafer by dissipation in the
diode. A similar formula can be derived for the
junction temperature of the diode wafer:
t
6
5
4
3
2
0.8
IA [kA]
Legend:
Fig. 3b
Evaluation of the complete set of equations
requires detailed information about the
distribution of losses in the GCT and diode
wafer under operation. This is soluble and
allows optimal design (minimal margins) but is
complex. A simpler but conservative approach
is to assume that all the losses are generated
in the wafer with the higher thermal impedance
which results in the curve of Fig. 4.
VD [kV]
ANODE
0.5 x PTOTAL
Fig. 3a
CATHODE
for a single-wafer device and the cross-heating
terms do not contribute to Tj rise for short
times, i.e. for surge current cases.
Thermal resistance of reverse blocking
IGCT type 5SHZ 08F6001
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Nürenberg, 6, 2000
ABB Semiconductors AG
Reverse Blocking IGCTs for Current Source Inverters
IF [kA]
0.5
0
-0.5
-1
95
100
105
110
1.0
-1
115
IV.2.3. Turn-on
The reverse blocking IGCT can either be
turned on from:
(1) the forward-biased state by a positive gate
pulse (following negative gate-bias),
2
4
1.5
3
1
2
0.5
1
0
0
10
15
time [µ s ]
Fig. 7
PCIM
-3
0
5
10
-4
time [ µ s ]
Fig. 8
Turn-on of DUT1: 800 A against 3700 V
However, since DUT1 has to be turned on to
allow for current commutation, this mode is
important with respect to timing delays
between turn-off of DUT2 and turn-on of DUT1.
Turning off DUT2 while DUT1 is not gated will
lead to over-voltage and device failure and it is
therefore a part of the control sequence of a
CSI that a device be gate-biased on in
advance of a complimentary device being
turned off (in this case: DUT1 on before DUT2
off).
V. Cosmic Ray Induced Failures
In the design of VSIs, cosmic ray withstand
capability is an important design criterion
because of the high continuous DC voltage to
which the semiconductors are exposed. In the
CSI, there is no constant voltage applied to the
devices which allows a degree of loss
(thickness) optimisation for a given blocking
voltage (V DRM, VRRM). The semiconductors here
are subjected to an alternating voltage and
since cosmic ray failures have an exponential
dependence on applied voltage, a slightly more
complex calculation must be performed (and
two separate cases considered) if the system
has both a line-side as well as a load-side
inverter.
VD [kV]
IA [kA]
or from:
(2) the reverse-biased state by current
commutation from the complimentary
device (following positive gate-bias).
In the test circuit, both turn-on modes are
investigated.
5
-2
0.4
0.0
Reverse recovery waveforms of DUT1 for
800 A turn-off into 3700 V.
The commutation di/dt is 1000 A/µs.
0
0.6
0.2
time [µs]
Fig. 6
0
0.8
V [kV]
D
0
-1
-2
-3
-4
-5
-6
I [kA]
A
1
The first mode is investigated on DUT2 in
Fig. 7 where turn-on from 3.7 kV is shown. The
current peaks to 1.8 kA due to reverse
recovery of DUT1 and discharge of the local
snubber resulting in just under 1 J of turn-on
energy.
The second mode is similar to diode forward
recovery since the device is already gated on.
Fig. 8 shows the reverse voltage of DUT1
slewing from –3700 V to 0 V, at which point
current can rise at a rate given by the
inductances LC and the fall time of DUT2
anode current. The turn-on losses are small for
this mode (0.15 Ws for the case of Fig. 8
VD [kV]
of the 5000 V peak appearing in reverse (Fig.
6) - the remaining 4980 V are sustained by the
diode wafer which thus generates virtually all
the dynamic losses of this phase.
Depending on the application, a turn-off
command may be sent to DUT1 during or
shortly after this reverse recovery phase.
It should be noted that no additional diode is
required anti-parallel to the asymmetric GCT to
by-pass reverse current as has been
suggested [5].
Turn-on of 800 A from 3700 V
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Nürenberg, 6, 2000
ABB Semiconductors AG
Reverse Blocking IGCTs for Current Source Inverters
Blocking voltage [V]
Let us consider an “active front-end” (line-side)
connected to a 2300 VRMS line. With ± 10 %
line tolerance, the peak voltage is 3600 V. At
unity power factor, we have pure rectifier
operation with the device blocking in reverse
direction an approximately sinusoidal voltage
of 3600 V peak during 66 % of the time (Fig. 9)
and sees no forward blocking voltage. On the
load side, the situation is reversed and the
device sees no reverse blocking voltage at
unity power factor.
Applying Fig. 9 to the now well-established
cosmic ray induced Failures-In-Time (FIT)
models under DC voltage [6] for the two wafers
used, the FIT rates listed in Table 1 are
calculated for the 5SHZ 08F6001 symmetric
IGCT.
The IGCT is a switch which makes no pretence
at modulating rise and fall times. As such, it
has only two states and its gate-driver is
device and not circuit specific. This allows
standard gate units to be supplied with the
GCT (hence IGCT) in keeping with the market
demand for higher integration.
However, the IGCTs introduced 3 years ago [7]
were designed for VSIs and, as described
above, logic changes have now been
implemented to allow for these new CSI
applications. Thus a new generation of IGCT
gate-drivers has been developed, suitable for
both CSIs and VSIs. The new drivers
additionally provide LED gate-status for
simpler commissioning and diagnostics as well
as an optical feedback for supervision of:
• Gate-drive supply voltage
• Gate-to-cathode status
• Optical link status
Optionally, factory tuning of IGCT turn-on and
turn-off time delays can be provided to
minimise the spread of these times for quasi
snubberless series connection. An AC powersupply input is planned to be optionally
available in order to further reduce system
costs. With a switching frequency of 750 Hz
and an average turn off current of 400 A, the
power consumption of the gate drive will be
about 40 W, most of which needed for turn-off.
4000
3500
3000
2500
2000
1500
1000
500
0
0
20
40
60
80
100
Percentage of time
Fig. 9
Blocking voltage for the calculation of the
FIT rate due to cosmic radiation.
Condition:
unity PF VDM=3600 V
Line-side
Load-side
FIT rate
10
50
Table 1
VII. Ratings of the 5SHZ 08F6001
The characteristics and ratings of the new
5SHZ 08F6001
derived
from
the
measurements made in the circuit of Fig. 2, are
shown in Table 2.
Fit rate due to cosmic raY failures.
VI. New Gate-driver
Parameter
Repetitive peak off-state voltage
Repetitive peak reverse voltage
Maximum controllable turn-off
current
On-state voltage
Turn-off switching energy
Symbol
VDRM
VRRM
ITGQM
Rating
6000
6500
800
Unit
V
V
A
VT
EOFF
6.3
5
V
J
Reverse recovery energy
ERR
6.5
J
Standard gate supply voltage
Planned optional
Typ. gate unit power consumption
VIN
VIN
19..21
24..40
40
V
V
W
Table 2
PCIM
PIN_MAX
Condition
Neg. gate supply voltage connected
Neg. gate supply voltage connected
VD = 3000 V, L S = 200 nH, C S = 0.1 µF,
RS = 10 Ω, TJ = 125 °C, L C = 3 µH
IT = 800 A, TJ = 125 °C
IT = 800 A, VD = 3000 V,
di/dt = 1000 A/µs, Tj = 125 °C
IT = 800 A, VD = 3000 V,
di/dt = 1000 A/µs, Tj = 125 °C
DC
AC voltage, square wave, 0-to-peak
IT AVG = 400 A, fPWM = 750 Hz
Ratings of 5SHZ 08F6001
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Nürenberg, 6, 2000
ABB Semiconductors AG
Reverse Blocking IGCTs for Current Source Inverters
VIII. Conclusion
After 5 years of service and within only 3 years
of market introduction, the IGCT has
established itself as a polyvalent power switch
for Energy Management (Power Quality),
Traction and Industrial Drives in both VSI and
CSI topologies.
The thrust for both component and platform
standardisation has been taken a step further
by realising the two-wafer press-pack. This
allows for optimisation of both GCT and diode
with high production yields, standardisation of
wafer
production
processes
and
standardisation of gate-drivers and housings.
Thus the same wafers, gate-units and
housings are used for series (including
redundance) and non-series connection in
both VSI and CSI topologies.
An emerging application for symmetric IGCTs
lies in the field of Power Quality AC breakers.
So far, these have been realised with antiseries connected reverse-conducting devices
[8]. However, where the ratio of fault current to
load current must be increased, an antiparallel connection of reverse blocking devices
will be preferred.
[7] E.Carroll, S.Klaka. S.Linder, “Integrated
Gate-Commutated Thyristors: A New
Approach to High Power Electronics“,
IEMDC, Milwaukee, 1997
[8] W.Raithmayr,
P.Daehler,
M.Eichler,
G.Lochner, , E.John, K.Chan, “Customer
Reliability Improvement with a DVR or a
DUPS“, Power World 98, Santa Clara,
1998
References
[1] N.Galster,
M.Frecker,
E.Carroll,
J.Vobecky, P.Hazdra, “Application-Specific
Fast-Recovery
Diodes:
Design
and
Performance”, PCIM, Tokyo, 1998
[2] P.Puttonen, M.Salo, J.Mokka, H.Tuusa, “A
Current-source
PWM-converter
for
Variable Speed Wind Energy Drive“, PCIM
Europe 1999
[3] H.R.Zeller, “High Power Components:
From the State of the Art to Future
Trends“, PCIM Europe, 1998
[4] A.Weber, N.Galster, E.Tsyplakov, “A New
Generation of Asymmetric and Reverse
Conducting GTOs and their Snubber
Diodes”, PCIM Europe, 1997
[5] K.Satoh,
M.Yamamoto,
K.Morishita,
Y.Yamaguchi, H.Iwamoto, “High Power
Symmetrical GCT for Current Source
Inverter”, ISPSD, Toronto, 1999
[6] H.R.Zeller, Solid-State Electronics, 38,
2041-2046, 1995
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Nürenberg, 6, 2000