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Harmonic Distortion Reduction Technique for Uninterruptible Power Supplies with DC Voltage Boost Technique Juei Lung Shyu Department of Electrical Engineering, Kao Yuan University No.1821,Chung Shan Rd., Lu Chu Hsiang, Kaohsiung County 821,Taiwan R.O.C. Abstract—This paper presents a new control strategy for UPS inverter, which is based on the addition of the DC voltage boost compensation for keeping the fundamental output voltage at the preset value and suppressing the generation of low-order harmonics caused by nonlinear load. This solution involves the combination of a total harmonic distortion (THD) reduction controller and a power factor correction (PFC) controller, such that the harmonics contaminated in the output voltage can be eliminated despite the highly distorted load current while maintaining an acceptable dynamic performance. Thus, the proposed strategy is viewed as a refinement term added to the outer voltage control loop. Besides, the DC voltage of the inverter under linear loads is adaptively reduced so that low switching losses is achieved, when compared with conventional constant DC voltage approaches. The new strategy is quite simple and requires only the measurement of the output voltage to compute the THD. Simulation results are presented to exhibit the improved performance of the proposed approach especially under rectifier loads. Keyword—UPS, total harmonic distortion, power factor correction. I. INTRODUCTION Uninterruptible power supplies are widely used as standby power for critical loads in case of utility power failure, such as computers, medical/life support systems, and communication systems. Among different UPS topologies, on-line UPS system has been commonly adopted since it can provide continuous power to the load with seamless transition from normal mode to backup mode during utility power failures and vice versa. Generally, the UPS is designed to produce high quality AC voltage with low distortion, particularly under nonlinear loads and sudden change in load. But the UPS system has high THD for nonlinear loads, for example, the rectifier load drawing a rectangular-shaped current causes voltage dips and notches in the AC output. In practice, even though it is filtered, the actual output voltage may still be distorted due to nonlinear load injected harmonic current. In order to achieve fast dynamic response and eliminate output voltage distortion under nonlinear loads, many improved control systems have been proposed such as sliding mode control, multi-loop, optimal state feedback, repetitive-based control, deadbeat control, and many others [1]-[7]. Although such types of feedback control approaches have fast transient response, the distortion is still not compensated completely for load disturbances. The disadvantage is that the maximum PWM voltage area of the pulse is limited by the computation and sampling time. This limitation results in relative large harmonic components occurring for nonlinear loads. In addition, all such control strategies are slightly complex to implement. For conventional PWM methods with constant DC input voltage, this can cause the inverter output voltage to contain large amounts of low order harmonics and significantly affect the inverter performance. Hence, a large PWM voltage area of each pulse is required to keep the distortion of output voltage low. This issue is completely ignored in previous works. In this paper, a simple THD reduction technique with addition of DC voltage boost compensation is proposed. In this technique, a DC voltage boost signal which is proportional to the THD value of the inverter output voltage is injected into the conventional PFC outer voltage loop. Then, the switching instance can be determined that the PWM voltage areas of the inverter are proportional to the instantaneous THD value. The THD value is obtained at every sampling cycle from the feedback of inverter output voltage. The desired DC voltage boost signal is determined through THD reduction control loop. As a result, the proposed control scheme leads to improve the THD of the inverter output voltage while keeping an acceptable dynamic response. 643 c 2008 IEEE 978-1-4244-1742-1/08/$25.00 Authorized licensed use limited to: IEEE Xplore. Downloaded on February 16, 2009 at 07:28 from IEEE Xplore. Restrictions apply. S outage snormal LS PFC Re ctifier VDC C DC is vs vDC Lo Inverter Co vo vPWM io iL vB buck / boost char ger Nonlinear Load Fig. 1(a). Circuit configuration of the single-phase on-line UPS system. v DC is* GPV (s ) G pi (s ) Voltage Controller v DC _ FDBK is vcp Current Controller vtri vPWM d p (t ) vo Fig. 1(b). Conventional PFC multi-loop control block diagram. v GiV (s ) * o vo iL* Voltage Controller Gii (s ) vci 'VTHD d i (t ) Current iL Controller vtri Fig. 1(c). Basic multi-loop control scheme of inverter. To further achieve a good transient response performance, an inner current loop is introduced to regulate the inductor current and generate necessary PWM signals. With such a multi-loop arrangement, the PWM inverter possesses the features of easy implementation, good transient response, and insensitivity to the load variation. Moreover, by the addition of DC voltage boost compensation, the DC voltage supplied to inverter at various loads is automatically compensated and lower switching loss is achieved for resistive load. Compared to previous works, a new approach is used to develop the DC voltage boost control, which results in a new feed-forward signal that has an additional term proportional to the THD of the inverter output voltage. The additional DC voltage boost signal is shown to be capable of reducing total harmonic distortion significantly, especially nonlinear load. The performance of the proposed control approach will be validated by simulation results. II. SYSTEM DESCRIPTION A. Description of the Circuit Topology Fig. 1(a) shows the typical schematic diagram of the on-line UPS system. The multi-loop control schemes are adopted in the designed UPS system. The UPS can be operated in two modes: one is the normal mode, and the other is outage mode. In the normal mode, the PFC rectifier converts the AC supply voltage into DC voltage 644 Fig. 1(d) Key waveforms of a conventional inverter without DC voltage boost compensation. for the inverter and battery charging. Moreover it generates input current with low THD as well as nearly unity power factor. The buck/boost battery charger is operated to provide backup energy in the outage mode. Meanwhile, to produce a stable power with high reliability during outage mode, the inverter should be modulated such that the output voltage is regulated well with low THD. Besides, bypass switches ( Snormal , Soutage ) change the operating mode in accordance with the line condition. As to the conventional PFC control system shown in Fig. 1(b), there are two control loops for PFC rectifier, one outer voltage loop and one inner current loop. The outer voltage loop uses the sensed DC voltage vDC as a feedback signal, which is compared with reference signal v*DC . The output of the voltage controller G pv ( s ) is then multiplied by a unity supply voltage vs to produce a control voltage is* as a reference signal for the inner current loop. Current error is then used to produce vcp through the current a control voltage controller G pi ( s) . The PWM generator generates required PWM signals to regulate the DC output voltage with the line current shaping. For an UPS inverter system with sinusoidal PWM technique, the output voltage vo is given by vo (d i cos Z o t )V DC (1) Where d i is the duty ratio of a pulse-width modulation (PWM) switching sequence at a relatively high frequency, which varies between 0 and 1. Zo is the output frequency. To guarantee a good tracking performance 2008 13th International Power Electronics and Motion Control Conference (EPE-PEMC 2008) Authorized licensed use limited to: IEEE Xplore. Downloaded on February 16, 2009 at 07:28 from IEEE Xplore. Restrictions apply. 'vboost vDC v *DC sinZt is* GPV (s ) Voltage Controller is vDC _ FDBK vcp G pi (s ) Current Controller d p (t ) vtri Fig. 2 (a) Block diagram of the proposed DC voltage boost compensation with THD reduction. * VTHD 'VTHD PI Limit Controller VTHD _ FDBK 'vboost vo THD Computation Fig. 2 (b) THD reduction control scheme. x2 RMS vo von vo1 Fundamental x2 y vTHD _ FDBK x2 Fig. 2 (c) Block diagram for THD computation. of inverter output voltage towards its pure sinusoidal reference command, the DC voltage should be increased properly if d i reaches to upper limit. A general multi-loop control block diagram, as shown in Fig. 1(c), consists of two loops. The outer voltage loop is mainly responsible for the output voltage regulation, which is achieved by comparing the voltage feedback signal vo and reference command vo* .The error signal is then generated as a reference command for the inner current loop. However, if a UPS inverter is digitally implemented with a microprocessor system, the maximum duty ratio is inevitably limited by A/D sampling and the required computation time to determine the pulse width of switching. As shown in Fig. 1(d), if the inverter with constant DC-link voltage connected to a nonlinear load, saturation of the duty ratio d i (t ) results in large distortion of the output voltage. Hence, it is necessary to increase the DC voltage to respond to the higher THD instantaneously and reduce the harmonic distortion through varying the PWM voltage area of each pulse. B. Control Strategy In order to provide precise voltage control of inverter, any harmonic distortion must be properly compensated. However, conventional PFC control with constant DC voltage can not achieve good performance under nonlinear loads disturbance. By introducing the DC Fig. 2 (d) Key waveforms of inverter with DC voltage boost compensation. voltage boost technique in the conventional voltage control loop of PFC rectifier, the performance of the single-phase PWM inverter can be optimized so that the output voltage is controlled with low THD. The proposed DC voltage boost scheme with improved steady-state performance is shown in Fig. 2(a). An extra THD reduction control loop in Fig. 2(b) is then added at the input of the conventional PFC voltage-loop to yield satisfactory inverter performance. In this technique, instead of a fixed DC voltage, a boost DC voltage 'vboost which is proportional to the THD value vTHD _ FDBK is injected at the input of the PFC rectifier. The output voltage vo of the UPS inverter is sampled and calculated to a detected THD value vTHD _ FDBK that is required for THD reduction control loop. The error * and signal between the THD threshold value vTHD detected THD value vTHD _ FDBK is then passed to a PI controller and the desirable boost signal 'vboost is thus generated. Due to the negative feedback in the THD reduction loop, the boost signal 'vboost changes in such a manner that the inverter output voltage is modulated so that the minimum THD is obtained. Finally, DC voltage boost signal is combined with voltage command v DC of conventional PFC control to form the new command signal v*DC . From the description above, one can derive the following key equations for resistive load and nonlinear load, respectively: 2008 13th International Power Electronics and Motion Control Conference (EPE-PEMC 2008) Authorized licensed use limited to: IEEE Xplore. Downloaded on February 16, 2009 at 07:28 from IEEE Xplore. Restrictions apply. 645 (a) (a) (b) (b) (c) (c) (d) (d) Fig. 3 Simulated results of rectifier load operation without compensation. (a) THD of output voltage (b) DC voltage v DC waveform (c) output voltage vo io waveform. (time: 01s/div) waveform (d) load current Resistive Load: v*DC v DC and 'vboost 0, if vTHD _ FDBK * d vTHD (2) Nonlinear Load: v*DC v DC ' vboost , if vTHD _ FDBK * t vTHD (3) Total harmonic distortion (THD) is an important figure of merit used to quantify the level of harmonics in voltage or current waveforms. THD can be defined as the ratio of the root-mean-square value of total harmonic voltage and fundamental voltage, as indicated in formula (4): THD vo2,rms vo21,rms vo21,rms f 2 ¦ von n 2 vo21 (4) where n is the harmonic order. v o,rms is RMS value of output voltage. v o1,rms -RMS value of fundamental component of output voltage and v on is the harmonic order n component. The THD is obtained by the calculations with samples of the output voltage vo at sample frequency equal to integer multiple of the nominal frequency of vo . THD computation block is 646 Fig. 4 Simulated results with compensation when load changes from rectifier load to resistive load. (a) THD of output voltage (b) DC voltage v DC waveform (c) output voltage vo waveform (d) load current io waveform. (e) Inverter output voltage v PWM waveform. (time: 01s/div) described in Fig.2(c). Fig. 2(d) shows key waveforms of the UPS inverter during a load step transient. As can be seen from Fig.2 (d), at t t1 , as sensed distorted output voltage, THD value experiences a positive step change, exceeding the * threshold value vTHD . The 'vboost is then summed up with vDC and generate a new voltage command v*DC at the input of the voltage loop. Since the desired voltage boost command 'vboost is determined by comparing the * with measured THD reference command vTHD value vTHD _ FDBK , thus, as expected, any waveform distortion in the output voltage leads to immediate 'vboost increase within one switching cycle. As shown in Fig. 2(d), the boost voltage 'vboost is proportional to 2008 13th International Power Electronics and Motion Control Conference (EPE-PEMC 2008) Authorized licensed use limited to: IEEE Xplore. Downloaded on February 16, 2009 at 07:28 from IEEE Xplore. Restrictions apply. (b) (a) (1) output voltage vo (100V/div) (2) load current io (50A/div) (3)Tracking error(20V/div) (1) output voltage vo (100V/div) (2) load current io (50A/div) (3)Tracking error(10V/div) * Fig. 5 Nonlinear load operation. (a) VTHD * 0.01 (b) VTHD TABLE I 0.05 . (time: 0.01ms/div) THD PERFORMANCE FOR NONLINEAR LOAD * vTHD 1% 2% 3% 4% 5% v DC 220V 216V 212V 208V 203V the error voltage 'VTHD . After the DC voltage is increased at t t1 , because of an immediate increase of the PWM voltage area of pulse, the THD of the output voltage caused by the nonlinear load is can be significantly reduced. Clearly, a high performance UPS inverter could * is chosen. It should be be obtained, if a smaller vTHD noted that the DC voltage supplied to inverter does not increase immediately after the THD sudden change because of the assumed low bandwidth of the voltage loop. III. SIMULATION RESULTS To verify the performance of the proposed control technique, some simulated results were carried out with Matlab/Simulink programming language. The proposed UPS inverter was tested without and with DC voltage boost technique. Nominal values of circuit parameters are listed as: vs 110 Vrms , VDC 200 V vo 110 Vrms C DC 940 PF Ls 3 mH , Lo 1 mH , C o 30 PF , and switching frequency f s 18 KHz .The performance of the UPS inverter with and without are shown in Fig. 3 and Fig. 4, respectively. As can be seen from Fig. 3, the output voltage THD is higher up to 7% while keeping DC voltage constant. Fig. 4 shows the key waveforms with compensation for load step change. For the transient response test, the DC voltage was stepped from 200V to 220V while nonlinear load applied, and then stepped back to 180V at resistive load. As can be seen from Fig. 4, the maximum THD during transient response is approximately 8%, whereas the corresponding THD under steady state is below 3% with compensation. As shown in Fig. 4(d), DC voltage experiences a positive step change. However, because of slow voltage control loop, vDC starts going up slowly some time after load change. The simulated results indicate that the proposed control scheme offers low THD with output voltage well regulated even under a highly distorted condition. By the addition of the THD reduction control loop, the DC voltage required for resistive load is much lower than that for nonlinear loads in terms of the THD. Since the switching loss of the UPS inverter is proportional to the DC voltage, it is easily seen that higher efficiency for resistive load is obtained with the proposed control scheme. On the other hand, the proposed approach does not increase more voltage stress of the power switches for inverter implementation. Table I shows the simulated DC voltage at same * . The nonlinear load with different threshold values vTHD harmonic distortion for nonlinear load could be reduced if an extra DC voltage boost compensation is added to the control strategy. As expected, the DC voltage * is increased. increases as vTHD Fig. 5 compares the output voltage waveforms of the inverter that is controlled by the proposed method for * was set at 0.01 and 0.05. same nonlinear load when vTHD * value can achieve This clearly shows that lower vTHD excellent steady-state performance with acceptable tracking error of output voltage. The dynamic response of the system for a step change in the reference voltage * vTHD between 0.01 and 0.05, under same rectifier load, are shown in Fig. 6. It shows that the dynamic response is seen to be reasonable with THD feedback vTHD _ FDBK * reaching to the reference command vTHD fast. IV. CONCLUSIONS A simple and effective control strategy for the THD reduction of inverter output voltage is proposed. To improve the performance of the UPS inverter, a DC voltage boost technique is added to significantly suppress the output voltage distortion caused by nonlinear load and thus nearly sinusoidal output voltage waveform is obtained. Transient response to load step changes is presented to indicate that good output voltage regulation 2008 13th International Power Electronics and Motion Control Conference (EPE-PEMC 2008) Authorized licensed use limited to: IEEE Xplore. Downloaded on February 16, 2009 at 07:28 from IEEE Xplore. Restrictions apply. 647 (b)THD value vTHD _ FDBK (a) DC voltage v DC * Fig. 6 THD step response when vTHD changes from 0.01 to 0.05. (time: 01s/div) with low THD are obtained simultaneously. Besides, the steady state performance is rather insensitive to DC voltage fluctuation and load variations. The present work is still on-going. The author is encouraged to ask for additional information on experimental results. REFERENCES [1] A. Kawamura and T. Haneyoshi, “Deatbeat controlled PWM inverter with parameter estimation using only voltage sensor,” IEEE Trans. Power Electron., vol. 3, no. 2, pp. 118-125, Apr. 1988. [2] T. Kawabata, T. Miyashita, and Y. Yamamoto, “Deat beat control of three phase PWM inverter,” IEEE Trans. Power Electron., vol. 5, no. 1, pp. 21-28, Jan. 1990. [3] S. –L. Jung, H.-S. Huang, M.-Y. Chang, and Y.-Y. Tzou, “DSP-based multi-loop control strategy for single-phase inverters used in AC power sources,” in proc. IEEE Power Electronics specialists Conf., 1997, pp. 706-712. [4] N. M. Abel-Rahim and J. E. Quaicoe, “Analysis and design of a multiple feedback loop control strategy for single-phase voltage-source UPS inverters,” IEEE Trans. Power Electron., vol. 11, no. 4, pp. 532-541,Jul. 1996.. K. Zhang, Y. Kang, J. Xiong, and J. Chen, “Direct repetitive control of SPWM inverter for UPS purpose ” IEEE Trans. Power Electron., vol.18, no. 3, pp. 784-792, May. 2003. [5] 648 [6] Heng Deng, Ramesh Oruganti, and Dipti Srinivasan, “ Analysis snd Design of Iterative Learning Control Strategies for UPS Inverters,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1739-1751, Jun.2007.. [7] Gustavo Willmann, Daniel Ferreira Coutinho, Luis Fernando, and Fausto Bastos, “Multi-Loop H-Infinity Control Design for Uninterruptible Power Supplies,” IEEE Trans. Ind. Electron., vol. 54, no. 3, pp. 1591-1602, Jun.2007. 2008 13th International Power Electronics and Motion Control Conference (EPE-PEMC 2008) Authorized licensed use limited to: IEEE Xplore. Downloaded on February 16, 2009 at 07:28 from IEEE Xplore. Restrictions apply.