Download In-plane gate transistors fabricated by focused ion beam

In-plane gate transistors fabricated by
focused ion beam implantation in
negative and positive pattern definition
Dissertation
zur
Erlangung des Grades
„Doktor der Naturwissenschaften“
an der Fakultät für Physik und Astronomie
der Ruhr-Universität Bochum
vorgelegt von
Mihai Drăghici
geboren in Bukarest
Bochum
2006
1. Gutachter ...................................... Prof. Dr. Andreas D. Wieck
2. Gutachter ....................................... Prof. Dr. Michael K. Sostarich
Datum der Disputation ..................... 05.02.2007
To my wife, Clari
Contents
List of abbreviations...............................................................................................................VI
List of symbols ...................................................................................................................... VII
Introduction .............................................................................................................................. 1
Chapter 1 – Short introduction to focused ion beam implantation ..................................... 4
1.1 Focused ion beam................................................................................................ 4
1.2 The liquid metal ion source ................................................................................. 6
1.3 Interactions of ions with solids............................................................................ 8
1.4 Channeling......................................................................................................... 13
1.5 The implantation dose ....................................................................................... 16
1.6 The performance of a focused ion beam system ............................................... 21
Chapter 2 – Samples preparation ......................................................................................... 24
2.1 Molecular beam epitaxy .................................................................................... 24
2.2 Rapid thermal annealing.................................................................................... 30
2.3 Photolithography ............................................................................................... 31
2.4 Ohmic contact deposition, alloying and bonding.............................................. 33
Chapter 3 – Field-effect transistors - theoretical aspects.................................................... 35
3.1 MOSFET ........................................................................................................... 35
3.2 MESFET............................................................................................................ 41
3.3 JFET .................................................................................................................. 42
3.4 Modulation-doped heterostructures................................................................... 43
3.5 MODFET........................................................................................................... 44
3.6 Other MODFET related devices........................................................................ 45
Chapter 4 – In-plane gate transistors fabricated by focused ion beam implantation
in negative pattern definition ........................................................................... 49
4.1 Depletion region of a 2D p-n junction............................................................... 49
4.2 Realization, basic device characteristics ........................................................... 50
4.3 Theoretical aspects – simple models ................................................................. 53
4.4 Depletion and enhancement modes of the IPG transistor ................................. 69
4.5 The IPG transistor at both RT and low temperatures –
comparison ........................................................................................................ 70
IV
Contents
Chapter 5 – In-plane gate transistors fabricated by focused ion beam implantation
in positive pattern definition ............................................................................ 78
5.1 Fabrication of IPG transistors in positive pattern definition ............................. 78
5.2 Theoretical aspects – basic device characteristics............................................. 80
5.3 In-plane gate transistors fabricated on p-doped heterostructures...................... 90
5.3.1 n-channel in-plane gate transistors........................................................ 93
5.3.2 p-channel in-plane gate transistors........................................................ 95
5.4 In-plane gate transistors fabricated on n-doped heterostructures...................... 96
5.4.1 n-channel in-plane gate transistors........................................................ 98
5.4.2 p-channel in-plane gate transistors........................................................ 99
5.5 Different geometries of the channel – comparison ......................................... 100
5.6 The source–drain current dependence on the geometrical
dimensions of the channel ............................................................................... 104
Chapter 6 – Applications of the in-plane gate transistors ................................................ 107
6.1 An electron pump realized with two IPG transistors ...................................... 107
6.2 Logic circuits with in-plane gate transistors.................................................... 114
6.2.1 Inverter fabricated with in-plane gate transistors in
negative pattern definition.................................................................... 114
6.2.2 Logic circuit NOR / AND with IPG transistors implanted
with FIB in positive pattern definition.................................................. 115
6.2.3 Logic circuit NAND / OR with IPG transistors implanted
with FIB in positive pattern definition.................................................. 117
Conclusions ........................................................................................................................... 119
Appendix A - Fundamental physical constants ................................................................. 124
Appendix B – The mask layouts.......................................................................................... 125
Appendix C – The samples processing ............................................................................... 129
Appendix D – Different types of FETs ............................................................................... 130
Appendix E – The electron pump gate controller ............................................................. 131
Appendix F – Physical parameters of AlxGa1-xAs.............................................................. 132
References ............................................................................................................................. 135
Acknowledgements ............................................................................................................... 146
Curriculum Vitae.................................................................................................................. 148
V
List of abbreviations
Abbreviation
1D, 2D, 3D
2DEG
2DHG
DCFET
DHFET
FET
FIB
FWHM
HEMT
HFET
HIGFET
IGFET
IPG
IPGJFET
JFET
LMIS
MBE
MESFET
MISFET
ML
MOCVD
MOD
MODFET
MOS
MOSFET
MOST
NPD
PPD
QW
RHEED
RTA
SATFET
SDTH
SHFET
SISFET
SPS
SRIM
TEGFET
UHV
Meaning
One-, Two- and Three-Dimensional, respectively
Two-Dimensional Electron Gas
Two-Dimensional Hole Gas
Doped-Channel Field-Effect Transistor
Double-quantum-well Heterojunction Field-Effect Transistor
Field-Effect Transistor
Focused Ion Beam
Full Width at Half Maximum
High-Electron-Mobility Transistor
Heterojunction Field-Effect Transistor
Heterojunction Insulated-Gate Field-Effect Transistor
Insulated-Gate Field-Effect Transistor
In-Plane Gate
In-Plane Gate Junction Field-Effect Transistor
Junction Field-Effect Transistor
Liquid Metal Ion Source
Molecular Beam Epitaxy
Metal-Semiconductor Field-Effect Transistor
Metal-Insulator-Semiconductor Field-Effect Transistor
Monolayer
Metal-Organic Chemical Vapor Deposition
Modulation-Doped
Modulation-Doped Field-Effect Transistor
Metal-Oxide-Semiconductor
Metal-Oxide-Semiconductor Field-Effect Transistor
Metal-Oxide-Semiconductor Transistor
Negative Pattern Definition
Positive Pattern Definition
Quantum Well
Reflection High-Energy Electron Diffraction
Rapid Thermal Annealing
Saturable-Charge Field-Effect Transistor
Selectively Doped Heterojunction Transistor
Single-quantum-well Heterojunction Field-Effect Transistor
Semiconductor-Insulator-Semiconductor Field-Effect Transistor
Short Period Superlattice
Stopping and Range of Ions in Matter
Two-dimensional Electron Gas Field-Effect Transistor
Ultra-High Vacuum
VI
List of symbols
Symbol
a
aTh - F
a0
A
B
B
C ion
d
d sph , d chr
D
e
E
E
EC , EV
EF
r r
Fel , Fmagn
Description
Half of the geometrical width of the channel
Thomas – Fermi screening radius
The first Bohr’s model radius
Implanted area
Magnetic field
Beam diameter
The charge of the ion species
Step size
The spherical and chromatic aberrations
Dose of implantation
Electron charge
Ion energy
Electric field
Conduction and valence band edge, respectively
The Fermi level
Electric and magnetic force, respectively
gD
gm
The channel conductance
The transconductance
g msat
The transconductance in the saturation regime
The transconductance corresponding to the theoretical maximum of
the drain current
The width of the depletion region
The width of the depletion region at negative drain voltages
Reduced Planck constant, h = h ( 2p )
g
max
m
h
hh
h1 , h2
1
2
h ,h
I
J x2D
ID
I
The depletion region at source and the drain, respectively
The depletion region width at the source and the drain, respectively
and for negative drain voltages
Ion current
2D-current density in the x direction
Drain current
sat
D
The saturation drain current
max
D
The maximum drain current
I
IP
k, K
kB
Pinch-off current
Multiples / constants
Boltzmann constant
VII
List of symbols
Symbol
l
l
L
L
L0
L1
Leff
M
n, p
N0
N 2D
N A , ND
ni
q
r
R
ur
ri
r
Rp
s
S n ( E ) , Se ( E )
t
T
u , u1 , u2 , uc
v
vs
Description
The depletion region width in either p- or n-type material of a 2D
p-n junction
Number of discrete points implanted along a line of length L
The length of the implanted line
The total depletion width
The geometrical length of the channel
The coordinate in the channel corresponding to the velocity
saturation in two-region model
The effective length of the channel
Ion mass
The electron and hole density, respectively
Number of ions implanted in the target
The 2D carrier concentration for a 2D p-n junction
Acceptor and donor carrier concentration, respectively
Intrinsic carrier concentration
Ion charge
Ion range
The distance vector between the collision of the ion with the atoms
i and i+1.
The projected range defined as the projection of the range on the
initial direction of the ions
Fitting parameter
Nuclear and electronic stopping cross-sections, respectively.
Implantation time
Temperature
Normalized depletion widths
Ion velocity
Carrier saturation velocity
V ( x)
The voltage in the channel at coordinate x
VAcc
Vbi
VD
Acceleration voltage of the focused ion beam system
Built-in potential
Drain voltage
VDsat
V
The saturation drain voltage
The voltage for which the current reaches the maximum (according
to the presented models for IPG transistors VDmax < VDsat )
VG
VP
VT
VTh - F
Gate bias
Pinch-off voltage
Threshold voltage
Thomas – Fermi potential
W
The width of the channel of an IPG transistor / IPGJFET
Weff
The effective width of the channel
Wgeo
The geometrical width of the channel
max
D
VIII
List of symbols
Symbol
Description
xn , yn
XA, XB
Z
Z1 , Z 2
Normalized coordinates by standard deviation
Atomic concentration of the elements A and B in a binary compound
MOSFET/MESFET/JFET channel width
Atomic numbers
DR p
e
e0
Standard deviation of the projected range
The reduced energy
The vacuum permittivity, e 0 = 8.85 ´10-12 F m
er
l
mn , m p
The relative dielectric constant
Fitting parameter
The electron and hole mobility, respectively
The carrier mobility (of either electrons or holes) of a 2D p-n
junction
Frequency
The reduced path length
The standard deviation(s) of the Gaussian distribution of the
implanted ions
Conductivity in the channel at coordinate x
The potential at coordinate x
Bulk and surface potentials, respectively
The metal work function
The semiconductor electron affinity
The angle under the ion enters into the channel measured with
respect to the channel axis
The band-bending
m 2D
n
r
s , sx, sy
s 2D ( x )
f ( x)
f B , fS
fm
c
ψ
y
IX
Introduction
Introduction
The in-plane gate (IPG) transistors fabrication [1] based on the electric field-effect of
planar surface gates using the focused ion beam (FIB) technique predicted the possibility to
fabricate a cheaper and more attractive field-effect transistor. The simplicity of the fabrication
process, as no alignment is necessary between source, drain and gate, is also one of the
advantages these devices offer. The very low capacitance demonstrated theoretically [2, 3]
and experimentally measured [4] makes this device a promising one for high speed operation.
The breakdown voltages for the in-plane p-n junction geometry are higher than for a 3D-one
because the electric field within the depletion region is almost independent of the applied
voltage [5]. Considering all these aforementioned advantages, it is not surprising that the low
dimensional transport properties of these two-dimensional field-effect transistors have been
intensively investigated for possible future electronic and optoelectronic applications. Since
their invention, different geometries, materials and techniques were proposed for devices
based on the same in-plane gate principle. The most of these papers have as subject IPG
transistors fabricated using the FIB technique “writing” insulating lines into a semiconductor
heterostructure, which has a two-dimensional electron gas (2DEG). Even if there is no report
on IPG transistors realized on heterostructures with a two-dimensional hole gas (2DHG), it
would be theoretically possible to use as starting material p-type wafers. These insulating
lines define a one-dimensional channel whose effective width can be controlled with the gate
bias. This method is also known as negative mode pattern definition. Still, this method has the
disadvantage that depending on the heterostructure doping, only one type of carriers governs
the electrical transport properties of these devices. The result is the impossibility to fabricate
complementary transistors on the same sample. The complementary method, the positive
pattern definition supposes that the regions implanted with FIB are also conducting and the
n- and p-doped regions are obtained using, for example, Si2+ and Be2+ respectively. Hirayama
[6] was the first who obtain n- and p-type channel transistors using semi-insulating substrate
as highly resistive region between gate(s) and channel. The difficulty of this method consists
in the different depth and broadness distribution of the implanted ions in material. Sasa et al.
[7] fabricated 2DEGs in GaAs/AlxGa1-xAs quantum well heterostructures implanting Si2+ ions.
At T= 4.2 K the measurements proved that the transport properties are dominated by the
successful formation of a good quality 2DEG in the quantum well, but at the same time
proved also the existence of a second 2DEG at an interface of the heterostructure forming a
parallel conducting channel. In 2002, Reuter et al. [8] proposed another method to obtain a
2DEG with no parallel conducting channel both at 4.2 K and room temperature in a p-doped
GaAs/In0.1Ga0.9As/Al0.35Ga0.65As heterostructure which is usually used for high electron
mobility transistors. They used this pseudomorphic heterostructure, which was grown by
molecular beam epitaxy intentionally undoped, instead of the semi-insulating substrate used
by Hirayama. The doping was realized with a FIB machine creating a 2DEG in the undoped
1
Introduction
heterostructure. The advantage of this technique is obvious: the fabrication of a 2DEG with a
much higher mobility than in original method proposed by Hirayama. But one should
consider the different implantation depths of the dopants in the same wafer, a supplementary
alignment and a refocusing step that are necessary when changing the ion species. All these
technological difficulties made Reuter et al. [9] to propose in 2004 another change from the
original technique that requires the implantation of only one type of dopant. According to this
technique, one uses as substrate p-type GaAs/InyGa1-yAs/AlxGa1-xAs heterostructures and
implants only Si2+, the 2DEG formation being based on local overcompensation doping. The
main advantage consists in the fact that it is easier to grow the heterostructure, so that to set
the depth of the 2DHG at the corresponding depth of the maximum ion distribution, i.e. the
alignment between 2DHG and 2DEG. In other words, because only one type of ion is
implanted, the heterostructure is designed to correspond to the necessary depth of the ion
distribution given by the implantation parameters. The implantation patterns, which should be
aligned during the implantation process with two ion species, together with the refocusing
step are eliminated. This method opened the possibility of fabrication of two-dimensional
n- and p-type IPG transistors from the same heterostructure.
The aim of this work is to realize a rigorous study of many different types of IPG
transistors fabricated by FIB implantation in both negative and positive pattern definition, and
finally, to propose several applications based on these transistors. Thus, the first chapter
presents the main aspects of the FIB technique, theoretical aspects of the interaction ion-solid
are shortly reviewed, numerical simulations for the ion distribution in solid after implantation
and the corresponding dose for lines and areas are performed and explained. The second
chapter describes in details the sample preparation methods and techniques. The third chapter
consists of a short introduction to the field-effect transistors. Starting with metal-oxidesemiconductor field-effect transistor and continuing with metal-semiconductor and junction
field-effect transistors, the focus moves to modulation-doped field-effect transistors. Several
devices based on selectively-doped heterostructures are presented and discussed.
The fourth chapter presents the results obtained on IPG transistors fabricated by FIB
implantation in negative pattern definition. The fabrication and a comparison between the I-V
characteristics obtained from IPG transistors fabricated on different heterostructures are
described. Then, different theoretical models for I-V characteristics are analyzed in detail for
both positive and negative drain voltages. The enhancement and depletion modes are also
reviewed. A comparison between room temperature and liquid helium temperature I-V
characteristics for the same IPG transistor is largely examined. Finally, the differences
between theoretical models and the experimental results are considered.
The fifth chapter consists of both theoretical and experimental considerations of IPG
transistors fabricated by FIB implantation in positive pattern definition. The theoretical
models presented for IPG transistors fabricated in negative pattern definition from Chapter 4
are reconsidered. For the first time, a formula analogue to the Lehovec-Zuleeg one, which was
deduced for junction field-effect transistors, is calculated for IPG transistors with twodimensional abrupt p-n junctions. Numerical simulations for the I-V characteristics are also
performed. A supplementary model, two-region model is discussed. Because the positive
pattern definition technique allows the fabrication of both n- and p-type channel transistors for
2
Introduction
p- and similar for n-type heterostructures, the fabrication of IPG transistors was divided in
four different cases. Every case is separately treated, but it has to be pointed out that the
fabrication of p- and n-type channel transistors for n-type heterostructures is for the first time
reported. An ample analysis of different implanted geometries of the channel is also
accomplished. Finally, the source-drain current dependence on the geometrical dimensions of
the channel is discussed.
The sixth chapter proposes different applications of the IPG transistors. For the first
time an electron pump with two IPG transistors is reported. Different logic circuits (NOT,
NOR, AND, NAND, OR) realized with IPG transistors either in negative or positive pattern
definition are described.
The conclusions and a summary of the main results obtained on the devices studied for
the first time, like the IPGJFETs fabricated on n-doped quantum well heterostructures or the
electron pump with two IPG transistors, as well as the main aspects of the theoretical models
proposed and developed along all the chapters are given in the last section of this work – the
conclusions chapter.
3
– Chapter 1 –
Short introduction to focused ion beam implantation
The focused ion beam implantation process is, by far, the main technique used in this
work, so that a short introduction into this field is necessary. This chapter will present a
typical focused ion beam system, it will briefly review the interactions between accelerated
ions and the solid, and will also discuss the simulations of the different implantation processes
(line, area implantation) and the corresponding dose calculations which are performed. In the
end, an evaluation of the performance of a focused ion beam system is done.
1.1
Focused ion beam
Ion implantation is a process in which ions, accelerated
at relatively high-energy between 10 – 200 keV, are injected
into the near-surface region of a target. In comparison with
other doping techniques, the ion implantation has many
advantages: a better control of the dose of the implanted ions,
a much better control of the depth of the implant, a better
lateral doping profile than the one obtained, for example, by
diffusion method [10] and the doping parameters in ion
implantation practically do not depend very much on the target
properties, but only on the energy and the species of the
implanted ions. Also, an important advantage is that the usual
temperatures of the thermal processes which follow the ion
implantation are lower than those used in diffusion technique.
The ion implantation is a vast branch of the
semiconductor doping field and this work will refer only to an
ion implantation realized by a machine, which uses a finely
focused beam of ions. A focused ion beam (FIB) machine
operates in a similar fashion as a scanning electron microscope
with the exception that a beam of ions replaces the beam of
electrons.
4
Figure 1.1: (a) diffusion and (b)
ion-implantation techniques for the
selective introduction of dopants
into the semiconductor substrate
(Ref. [10]) (c) Maskless FIB
implantation realized by moving a
beam of ions in (x, y) plane.
Chapter 1: Short introduction to focused ion beam implantation
A typical FIB column is presented in Figure 1.2 and can be thought as composed of
three main components: the ion source, the ion optics column and the sample stage.
Liquid-metal ion source
Extractor
Condenser lens (CL) 1
CL – Alignment
Condenser lens (CL) 2
CL – Aperture
Aperture
Beam blanking plate set
E x B mass filter
OL Aperture
Aperture
Faraday-cup
OL – Alignment
Stigmator plates
Objective lens (OL)
Beam deflector
Sample
Stage
Figure 1.2: Diagram of the focused ion beam system EIKO 100 E. This equipment possesses
two condenser lenses and can provide an acceleration voltage of 100 kV.
5
Chapter 1: Short introduction to focused ion beam implantation
The instrument can be used for implantation, sputtering, deposition, micro-machining
and ion beam lithography. The application of the FIB is also strongly correlated with the dose
of implantation:
·
Implantation: the dose is less than 1013 ions/cm2 – only punctual defects are generated
which can be healed by a heating process (rapid thermal annealing step which follows
immediately after the implantation). This is also our range of interest since the GaAs
doping is performed in this range. Different material modification of GaAs-AlxGa1-xAs
systems may be produced like: formation of high resistive regions in n-type GaAs [11,
12] – one of the first steps which led to the invention of the in-plane gate (IPG)
transistor [1] and the in-plane-gated wires [13], local intermixing of GaAs-AlxGa1-xAs
superlattices [14, 15], which was used to fabricate quantum-well-wire structures [16],
and to obtain complementary type conduction region by “overcompensating” the
heterostructure doping with FIB [6], which permitted the fabrication of IPG transistors
in positive mode pattern definition [6, 17].
·
Amorphisation: for doses higher than 5 ´1013 ions/cm2 - the rapid thermal annealing is
not efficient in healing the defects agglomerates that form during the implantation
process.
·
Sputtering: for doses higher than 1017 ions/cm2 – atoms from the target are removed.
This regime can be effectively used for GaAs dry etching.
In our group, Lehrstuhl für Angewandte Festkörperphysik, Ruhr-Universität Bochum,
there are currently six different FIB machines, all of them using liquid metal ion sources. The
acceleration voltages of these machines are in the 30 – 100 kV range and the diameter of the
beam, depending on the machine, is 30 – 100 nm.
1.2
The liquid metal ion source
The FIB technology with high impact in semiconductor field and high resolution
( < 1 µm beam diameter) primarily uses the liquid metal ion source (LMIS), a very bright,
stable, field emission ion source. FIBs using LMIS are characterized by beam diameters in the
5 – 500 nm range with target current densities up to a few A/cm2. Unresolved issues include a
relatively broad ion energy distribution and the impossibility to produce inert ion species such
as Ar, reactive ion species such as O and light species such as H. Still, a large variety of ion
species (Ga, Si, Au, Be, etc.) is available.
The practical application of the LMIS in a focusing column was demonstrated, first by
Seliger et al. [18] in 1979 and shortly thereafter by many others. This was one of the most
important steps in the rapid growth of FIB applications based on the LMIS technology.
Allowing the possibility of beam diameters less than 10 nm, LMISs made FIBs to be more
effectively applied in scanning ion microscopy, and surface analysis. It was also one
important step in the development of micromachining, direct ion implantation, and
high-resolution ion lithography, among other uses.
6
Chapter 1: Short introduction to focused ion beam implantation
A major effort to study LMISs and their applications for doping of semiconductor
devices and lithography was started by Namba, Gamo and co-workers [19, 20]. These
researchers studied the source fabrication, especially for alloy sources such as Au-Si and
Au-Si-Be ion beams, and the development of a mass-separating focusing column [21].
a)
b)
c)
d)
e)
Figure 1.3: a) Sketch of a LMIS; b) – c) Picture of an Au-Si-Be LMIS from Eiko FIB system at room
temperature and during implantation, respectively; d) – e) Picture of an Au-Si-Be LMIS from
Denka FIB system at room temperature and during implantation, respectively. During implantation
the temperature of these two LMIS’s reaches aprox. 350 °C and one can see the ion plasma formed
at the tip. Courtesy of A. Melnikov.
A LMIS consists in a container in which the metal, or metallic alloy, is heated above
the melting temperature or eutectic point of the alloy components. In the middle of the
container there is a very sharp needle of tungsten and the molten alloy wets this needle and
flows to the tip [22]. From this point they are “extracted” with a high electric field produced
using an extraction voltage of 4 – 6 kV. The liquid metal is pulled into a cone named Taylor
cone, by the balance between electrostatic and surface tension forces [23, 24]. One could
consider that the tip of this cone is the source of ions. The apex radius of the cone is only
about 5 nm [25, 26]. The most common LMIS uses Ga, which has the melting point at 29 ºC
and it is the most stable with the longest lifetime ion source in the present FIB technology.
Another source used is an eutectic compound, Au65Si27Be8, which makes possible the
emission of all three species of ions using a mass separator, i. e., a Wien filter. Being in fact a
velocity selector, the Wien filter serves as a mass filter, as the velocity n of an ion is
determined by the mass M by the v = ( 2qVAcc M )
1/ 2
, where VAcc is the beam accelerating
voltage and q the ion charge. The Lorentz force Fmagn, which a magnetic field B exerts on an
ion, normal to the optical axis, is Fmagn = qvB . This is counterbalanced by the electric field E
r r
r
produced by the voltage applied to the electrodes in the filter, so that, F = Fel + Fmagn = 0 . That
is equivalent with q ( E - vB ) = 0 , therefore the magnetic and electrostatic forces balance only
when
( 2qVAcc
v = E /B .
M)
1/ 2
Considering
the
aforementioned
= E / B , one can obtain:
7
expression
for
the
velocity
Chapter 1: Short introduction to focused ion beam implantation
M
æB ö
= 2VAcc ç ÷
ion
C e
èE ø
2
(1.1)
where C ion is the charge of ion species (for our Au-Si-Be LMIS C ion = {1, 2} ) and e is the
electron charge.
The left term contains only ion(s) specific
quantities, while the right-side term contains the
magnetic and electric fields and the acceleration
voltage, which is usually kept constant during the
implantation. It becomes obvious that controlling
the electric and magnetic field one can choose the
ion species for the implantation.
The complete trajectory of an ion
extracted from the LMIS until it reaches the
target is the main focus of the ion optics. Ion
optics is a branch of the charged particle optics, Figure 1.4: Mass spectrum for an Au-Si-Be
LMIS.
and covers the calculation of electric and
magnetic fields produced by electrodes or pole pieces with various geometries, the calculation
of trajectories of charged particles through these fields, the description of the fields as lenses
in terms of geometrical or wave optics, and the effect of lens aberrations on the particle
trajectories.
The ions impinge on the substrate with kinetic energies 4–5 orders of magnitude
greater than the binding energy of the solid target and therefore, practically, any element can
be injected into the near-surface region of any solid.
1.3
Interactions of ions with solids
When ions enter the target material they will collide with both the nuclei and electrons
of the target. The ion-solid interactions can be classified in two main distinct processes:
elastic interactions with the nuclei, which produce the displacement of lattice atoms, surface
sputtering or the formation of defects and inelastic interactions with electrons, which are a
source for secondary electrons, X-rays and optical photon emission. Between two successive
interactions with the nuclei, ions interact also with the electrons, but because of the big
discrepancy between the ion and electron masses, the ions will not change their trajectory,
which can be considered linear. The trajectory of the ions is only changed as the result of a
collision with an atom.
The distance between the point from where the ion enters into the target and the point
r r r
r
r
where it stops is called range R = r1 + r2 + ... + rn , where ri is the distance vector between the
collision of the ion with the atoms i and i+1. The projection of the range on the initial
r
direction of the ions is called the projected range R p (Figure 1.5 (b) - (c)). The spatial
distribution of the implanted ions is called implantation profile. The first ions, which enter
into the crystal lattice, produce a series of defects so that the following ions will move under
8
Chapter 1: Short introduction to focused ion beam implantation
different conditions. The interaction of ions with a crystal can be analyzed considering that in
the crystalline solid, atoms form a periodic lattice, i.e. rows of atoms and empty spaces
depending on the viewing direction. This means that the crystal properties are different for
different crystallographic axes, and the ion movement is strongly direction dependent,
because the densities of the atoms and electrons depend on the direction. In this case a series
of supplementary effects may appear, e.g. channeling. One method to study the interaction of
ions with matter is to consider in the first approximation an amorphous solid.
Figure 1.5: (a), (b) the interaction between a light and respectively heavy ion with a solid; (c) the range
r
R , the
r
r
R p and the transverse straggling distance Rt ; A SRIM simulation for Be+ and Si+
projected range
which enter perpendicularly into AlxGa1-xAs with the incident energy of 30 keV. According to the
simulation
+
+
R pBe = 120 nm and R psi = 35 nm .
The theory which studies the range and the spatial distributions of ions in amorphous
solids is known as Lindhard–Scharff–Schiøtt [27] or LSS-theory. The main purpose of the
theory is to find a mathematical expression for the implantation profile as a function of the ion
energy. Because of the statistical character of the ion movement, the range and the projected
range of the ions will be ion dependent, so that the interest is in fact to find the mean value:
+¥
Rp
ò
=
ò
0
xN ( x)dx
+¥
0
(1.2)
N ( x)dx
where x is the coordinate measured from the semiconductor surface and N ( x) the
implantation profile function, the target being considered of infinite depth.
Of practical interest is also the standard deviation of the projected range defined by:
9
Chapter 1: Short introduction to focused ion beam implantation
+¥
2
DR p = é ò ( x - R p ) N ( x)dx
ëê 0
ò
+¥
0
1
2
N ( x)dx ù
ûú
(1.3)
which is called projected straggle.
The LSS-theory was developed having as basis the Bohr model of atomic collision.
Ions lose their energy due to the collisions with the nuclei and electrons, so that the total
stopping power dE dx , defined as the energy loss per unit path length of the ion, can be
defined as:
dE æ dE ö
æ dE ö
=ç
+ ç
÷
÷
dx è dx ønuclear
è dx øelectronic
(1.4)
usually this equation is also written as:
dE
= N 0 éë S n ( E ) + Se ( E ) ùû
(1.5)
dx
where N 0 is the number of scattering centers per unit volume, i.e. target atom density
(atoms/cm3), S n ( E ) and Se ( E ) are the nuclear and electronic stopping cross-sections,
respectively.
The range of ions can be written as:
R
E0
dE
1 E0
dE
(1.6)
R = ò dx = ò
=
ò
0
0 æ
dE ö N 0 0 S n ( E ) + Se ( E )
ç÷
è dx ø
In order to determine the stopping cross-sections one should consider the mechanism
of ion-nucleus and ion-electron interactions. For low energies the nuclear energy loss is very
complex, for medium energies the interaction is described well by a screened Coulomb
scattering, and at high energies the interaction is mostly due to Rutherford scattering. In the
case of heavy ions with not too high kinetic energies the electron clouds screen the nuclei
from each other. The nuclei cannot come so close so that Rutherford scattering occurs, and
instead of an unscreened Coulomb potential, one should use in calculations a screened
potential. A good approximation for the screened potential is the Thomas – Fermi potential:
VTh-F ( R) =
Z1Z 2 e 2 æ R ö
xç
÷
R
è aTh - F ø
(1.7)
Here Z1, Z2 are the atomic numbers, e is the electron charge and aTh - F is the Thomas – Fermi
screening radius aTh - F = a0 × 0.8853 ( Z12 3 + Z 22 3 )
-1 2 (*)
with a0 = 4p h 2e 0
( e m ) = 0.529 Å
2
e
being the first Bohr’s model radius. Expressed in Ångströms the screening radius becomes
aTh - F ( Å ) = 0.468 ( Z12 3 + Z 22 3 )
-1 2
and has an usual magnitude of 0.1-0.2 Å. The function
x ( R aTh - F ) is called Fermi function. An useful approximation is the Thomas – Fermi power
potential:
(*)
The number
(
0.8853 = 9p 2
)
13
2 -7 3 is the Thomas – Fermi constant [27].
10
Chapter 1: Short introduction to focused ion beam implantation
s -1
Z Z e 2 k s æ aTh - F ö
(1.8)
VTh - F ( R ) = 1 2
ç
÷ ,
R
s è R ø
where s is a fitting parameter, and ks is a constant. For large values of aTh - F R , s = 1 and
k s = 1 ; for smaller values of aTh - F R , s = 2 or 3.
A major simplification of the calculus may be obtained introducing two dimensionless
parameters, the reduced path length r and the reduced energy e [27, 28]:
4p ( 0.885 ) a02 N 0 M 1M 2
2
r=R
e =E
(Z
23
1
+ Z 22 3 ) ( M 1 + M 2 )
(1.9)
2
0.885a0 M 2
e 2 Z1Z 2 ( Z12 3 + Z 22 3 )
12
(1.10)
( M1 + M 2 )
In these conditions equation (1.4) becomes:
æ de ö
de æ de ö
=ç
+ ç
÷
÷
d r è d r ønuclear
è d r øelectronic
(1.11)
Figure 1.6: Theoretical nuclear and electronic stopping power curves, as a function of the
reduced variables r and e. For the electronic stopping, a family of lines (one for each
combination of projectile and target) is obtained. The horizontal doted line labeled S 0
represents the constant stopping-power approximation suggested by Nielsen [29].
Making
-
the
notations
æ de ö
= - sn ( e ) ,
ç
÷
è d r ønuclear
æ de ö
= - se ( e )
ç
÷
è d r øelectronic
one
obtains:
de
= sn ( e ) + se ( e ) which is similar with equation (1.5).
dr
One of the main advantages of the reduced parameters r and e is that the nuclear
energy loss can be written only as a function of e and a good approximation gives [24]:
sn ( e ) =
0.5ln (1 + e )
e + 0.14e 0.42
(1.12)
11
Chapter 1: Short introduction to focused ion beam implantation
At higher energies, because electrons can follow fields up to optical frequencies, electronic
collisions dominate the total energy loss. The LSS-theory gives a general formula for the rate
of electronic energy loss per unit depth:
0.0793Z11 2 Z 21 2 ( M 1 + M 2 )
æ de ö
12
= ke
(1.13) where k = x e
ç
÷
34
è d r øelectronic
( Z12 3 + Z 22 3 ) M13 2 M 21 2
32
, x e @ Z11/ 6
For most combinations of projectile and target the values for k are in the 0.1 ¸ 0.25
range. From Figure 1.6 one can see that the nuclear stopping is important at low energies,
reaches a maximum value around e = 0.35 , and then falls off. For higher energies the period
of time for which the ion passes in the vicinity of the nucleus becomes shorter and the energy
transfer becomes less. So, the nuclear scattering is not strong at high ion velocity and becomes
efficient only when the ion slows down.
The electronic stopping increases linearly with velocity over a wide range and
becomes the dominant process for energies greater than e » 3 . For very high energies the
electronic stopping also passes through a maximum and then falls off as a function of e -1 . For
this very high-energy region the ion velocity exceeds that of the orbital electrons and has been
investigated by nuclear physicists, but is far beyond the energy range of interest in most ion
implantation processes.
Figure 1.6 also shows the constant total stopping power S0. This approximation was
first published by Nielsen [29] and at very low energies overestimates the nuclear stopping
(and consequently underestimate the range), and at high energies underestimates the
electronic stopping. Still, for medium energies, 0.05 < e < 10 it provides a rule of thumb for
predicting the heavy ion ranges with an accuracy of about 30 %. In these conditions using
equations (1.9) and (1.10) the Nielsen equation ( r = 3.06e ) becomes [30]:
R (Å) =
130 E ( keV ) 1 + M 2 M 1
N0
Z12 / 3
(1.14)
Finally, in order to determine the projected range one can use the approximate relation
between R and R p proposed in Ref. [31]:
M2
R 1é
1+ m
1- m ù
1
= ê - 1 - 3m + ( 5 + m )
arccos
.
(1.15)
ú @ 1 + m , where m =
R p 4 êë
1 + m ûú
3
M1
2 m
which is valid considering a Thomas–Fermi power law approximation (1.8) of nuclear
scattering with s= 2 and neglecting the electronic stopping. For small µ (up to ~1) and any
value of s [27]:
R
s2
@ 1+ m
.
Rp
4 ( 2s - 1)
If the target is a binary compound formed by the elements A and B with atomic
concentration XA and XB, supposing that the energy loss mechanism is the same for both
elements, the ion range becomes:
1 XA XB
=
+
, where RA and RB are the range of ions in the pure A and B solids.
R RA RB
12
Chapter 1: Short introduction to focused ion beam implantation
In order to determine the standard deviation of the projected range defined by equation
(1.3) a Gaussian distribution for the range of ions is considered
é ( x - R )2 ù
D
p
ú,
N ( x) =
exp ê (1.16)
ê
2DR p2 ú
2p DR p
ë
û
where D is the dose of implanted ions.
In Ref. [28] it was demonstrated that the standard deviation can be calculated using
2 ( M 1M 2 )
DR p @ 0.4 R p
M1 + M 2
12
.
(1.17)
One of the most efficients way to rapidly find the range of ions in semiconductors (for
our purpose Si+, Si2+, Be+ in AlxGa1-xAs) is the software SRIM (Stopping and Range of Ions
in Matter) [32] which one can use to make a three dimensional Monte–Carlo simulation of the
ions penetration into the matter. Even if the results are not extremely precise due to some
effects that are not considered, the discrepancy between a complicate simulation that would
consider all these effects and the output of SRIM is insignificant.
1.4
Channeling
The LSS-theory previously discussed gives good predictions for the projected range
and straggle of the implanted ions in amorphous targets. Gallium arsenides, and also silicon,
behave like amorphous semiconductors if the ion beam is not oriented on a low-index
crystallographic direction. If the incident ions are aligned with a low-index crystallographic
direction they are guided between the rows of atoms in the crystal and this effect is known as
channeling.
(a)
(b)
Figure 1.7: A GaAs crystal viewed along: (a) <110> crystallographic direction and (b) <234> direction.
13
Chapter 1: Short introduction to focused ion beam implantation
Channeling can dramatically increase the range of ions. For example, in a Si target the
implanted As ions can have a 50 times longer projected range when channeling occurs. The
explanation for the channeling effect is that if the incident ion makes a small angle with a row
of atoms from the crystal then the ion is guided by successive collisions produced under a
small angle with many atoms, which form the “wall of the channel”. The main condition for
this effect to be produced is that the channeled ion should not come too close to the atoms
from the crystal and the successive ion-atom collisions to be under a very small angle. For
channeled ions the only energy loss mechanism is electronic stopping. For ions implanted
with low-energies the term of nuclear energy loss is important. Because channeling supposes
a minimum ion-atom interaction in the target, ion-channeling effect becomes critical for
low-implantation energies and heavy ions.
Considering that the ion enters into
the channel under a small angle ψ made
with the channel axis, as one can see in
Figure 1.8, its transversal kinetic energy is:
M 1v 2 sin 2 ψ
= E sin 2 ψ .
2
Figure 1.8: The trajectory of a channeled ion.
This kinetic energy is changing into potential
energy V(y) when the ion, in its movement,
is closing to the row of atoms. If y0 is the maximum amplitude of the ion movement along the
E1 =
channel then E sin 2 ψ = V ( y0 ) and considering the approximation for small angles sin ψ ; ψ ,
one obtains
V ( y0 )
.
(1.18)
E
In Lindhard’s model [33] it is considered that the interaction between the channeled
ion and the row of atoms from crystal is continuous, i.e. the ion at rmin interacts with a large
r
number of atoms. Under these circumstances min > d . The Thomas-Fermi potential given by
ψ
ψ=
equation (1.7) is considered as interaction potential. For high energies the electronic stopping
power becomes dominant x ( R aTh - F ) ; 2 , so that
2Z1Z 2 e 2
.
d
This potential does neither depend on the kinetic energy of the ion, nor on the
Thomas-Fermi screening radius aTh - F . Introducing the potential expression in equation (1.18),
Vmax =
one finds out that the incident angle should be smaller than
1/ 2
æ 2Z1Z 2 e 2 ö
ψ < ψ1 = ç
÷ .
è Ed ø
In the case of low energies the potential VTh-F(R) depends on the screening radius and
2
æ R ö æ aTh - F 3 ö
xç
÷ .
÷ = çç
R ÷ø
è aTh - F ø è
14
(1.19)
Chapter 1: Short introduction to focused ion beam implantation
Considering also equations (1.7) and (1.18) one obtains for this situation:
1/ 2
1/ 2
æ aTh - F 3 ö
æ aTh - F ö
ψ < ψ 2 = çç ψ1
÷ ; ç ψ1
÷ .
d
d ø
2 ÷ø
è
è
The incident particles and therefore the implantation profile can be divided in three
distinct regions:
· The first region situated in the vicinity of the semiconductor surface corresponds to the
ions which are not influenced by the crystal lattice of the solid, their distribution being
very close to that calculated for amorphous solids (Region A, Figure 1.9);
·
The second region (Region B) corresponds to the ions which due to the successive
collisions lost their direction, i.e. the crystallographic direction along the channel;
·
The third region corresponds to the slowing down of the channeled ions.
Figure 1.9: (a) Trajectories for various angles of incidence ψ . Curve A corresponds to an incident angle greater
than the critical angle, B and C correspond to a ψ smaller than the critical angle. (b) Trajectories for parallel
incidence as a function of impact position. (c) The depth distribution of implanted atoms in a crystal when the
beam is oriented along a low-index crystallographic direction.
Because the main mechanism for the energy loss is the electronic loss it can be proved
[33] that the projected range for the channeled ions can be written as
Rmax = a R E
(1.20)
where a R is a constant which depends on the ion species and the target material. If the
diffusion processes can be neglected, then Rmax gives the depth where, for a practical
example, a junction can be formed into a semiconductor material. Knowing the depth for a
certain energy of the implanted ions, one can find out the depth at which the junction is
formed for other energies.
15
Chapter 1: Short introduction to focused ion beam implantation
1.5
The implantation dose
One of the most important parameters of the implantation process is the dose of
implantation which is defined as the number of ions implanted per unit area:
nr. of ions
I ×t
é 1 ù
Dose =
=
(1.21)
ion
area
A × C × e êë cm 2 úû
Here I is the ion current, e is electron charge, A is the implanted area, Cion the charge of the
ion species, t the implantation time
I ×t
N 0 = ion
(1.22)
C ×e
is the number of ions implanted in the target.
Sometimes, the dose is also defined as the implanted charge per unit area:
charge I × t é C ù
Dose =
=
(1.23)
area
A êë cm 2 úû
The ion distribution can be very well described by a circular(*) Gaussian function:
æ r2 ö
n(r , s ) = n0 exp ç - 2 ÷ ,
è 2s ø
where n0 is given by the number of implanted ions in the target and s is the standard
deviation of the Gaussian distribution. In order to determine n0 one can solve the equation:
N 0 = n0 ò
2p
0
n( r , s ) =
ò
¥
0
æ r2 ö
exp ç - 2 ÷ rdrdq obtaining
è 2s ø
æ r2 ö
N0
exp
ç- 2 ÷.
2ps 2
è 2s ø
(1.24)
Usually, the beam diameter is considered to be the full width at half maximum
(FWHM) of the Gaussian distribution [34], where:
FWHM = 2 2 ln 2s @ 2.35 s
(†)
(1.25)
The electronic hardware permits only discrete values for the deflection voltage, so that
the movement of the ion beam along the X and Y axis will be realized in steps. The smallest
step d(nm) is machine dependent, and for a FIB system it is a well known constant. The
software controls the movement of the beam as a multiple k of this constant and the user can
also set how long the beam stays in one point (the dwelling time) by setting the frequency n.
(*)
A two-dimensional Gauss function is defined as: f ( x, y ) =
A circular Gauss function is obtained when the deviations
(†)
1
2
2
exp é - ( x - x0 ) 2s x2 - ( y - y0 ) 2s y2 ù .
ë
û
2ps xs y
sx =sy .
The mathematical expression for FWHM is correlated with the definition of the function. For example, if the
Gaussian
function
were
defined
as
æ r2 ö
n(r , s ) = n0 exp ç - 2 ÷ ,
è s ø
FWHM = 2 ln 2s = 1.665s .
16
then
the
FWHM
would
be
Chapter 1: Short introduction to focused ion beam implantation
There are three different situations when the dose of implantation is of interest: when
the beam is fixed in one point, so that the ions are implanted in a spot, when the beam is
moving along a line or when the beam is swept over an entire area.
The dose of implantation for a spot
In this situation the implanted area will be in fact the area of the beam. One should
evaluate then only the number of ions from this area
N FWHM = ò
2p
0
ò
FWHM / 2
0
N FWHM = N 0 ò
ln 2
0
æ r2 ö
N0
N0
exp
ç - 2 ÷ rdrdq = 2
2
s
2ps
è 2s ø
ò
2ln 2s
0
æ r2 ö
exp ç - 2 ÷ rdr
è 2s ø
æ 1ö N
exp ( -u ) du = N 0 ç1 - ÷ = 0
è 2ø 2
(1.26)
The number of ions N 0 , according to equation (1.22) is: N 0 =
I ×t
.
C ion × e
2 It
(1.27)
C ep B 2
The dose of implantation in this case depends strongly on the definition of the beam
size. If one considers a beam of double FWHM then the number of ions from this area is
0.94 × I × t
0.94 It
N 2 FWHM =
and the dose D 2 FWHM = ion
, which is more than two times less the
ion
C ×e
C ep B 2
dose corresponding to a beam size equal to FWHM.
If B is the beam diameter, the dose will be: D FWHM =
ion
The dose for a line
For a line, the number of implanted ions can be calculated considering that the length
L of the line is in fact given by the number l of discrete points, situated at the distance k·d, so
that L = l × k × d , and the implantation time is given by t = l n . Considering that the line is
along the Ox-direction, the distribution of the ions is a sum of Gaussian-shape spots given by
(1.24), which written in Cartesian coordinates yields:
é æ y ö2 ù l
é æ x - ik d ö2 ù
N0
n ( x, y , s ) =
exp ê - ç
÷ ú × å exp ê - ç
÷ ú,
2ps 2
êë è s 2 ø úû i =0
êë è s 2 ø úû
(1.28)
where it was considered that the implantation started at x0 = 0 , y0 = 0 .
Introducing the normalized coordinates by standard deviation, xn = x s , yn = y s :
n ( xn , yn , s ) =
2
é 1æ
N0
ikd ö ù
æ 1 2ö l
exp
y
exp
x
ê ç n
n ֌
ç
÷ ú the step with which the
2ps 2
2
s
è 2 ø i =0
è
ø ûú
ëê
kd
. Because the purpose is to implant a line
s
with an uniform dose one should carefully choose the multiple k, so that the sum of Gaussian
beam is moving on normalized x coordinate is
17
Chapter 1: Short introduction to focused ion beam implantation
distributions should not decrease along the line. In order to evaluate the values for k a starting
point is the equation:
N
line
tot
N0
= l N0 =
2ps 2
æ ( x - ikd )2 ö
æ y 2 ö +¥ l
exp ç ÷ dx , so that:
2
ò-¥ exp çè - 2s 2 ÷ødy ò-¥ å
ç
÷
2
s
i =0
è
ø
+¥
æ ( x - ikd )2 ö
exp ç (1.29)
÷ dx = l 2ps
ò-¥ å
ç
2s 2 ÷ø
i =0
è
The purpose is to determine the k values for which the distribution of ions along the
line is practical a constant. Considering in equation (1.29) the integrand as being a constant K
+¥ l
along the line of length (l kd ) and zero in rest one has: K × (l kd ) = l 2ps , where
2p
s
(1.30)
kd
The overlap of the Gaussian functions becomes practically visible for K ³ 1 , which
corresponds to a normalized step size:
kd
£ 2p
(1.31)
s
whereas the superposition of the Gaussian distributions becomes practically constant having a
fluctuation of less than 0.01 % [35], only when:
kd
£ 1.5
(1.32)
s
K=
For a normalized step size, which is 1.5 £ (kd s ) £ 2p , the sum of Gaussian
functions is an oscillating function having the mean value given by (1.30). Defining the
normalized ion distribution as N n = 2ps 2 n N 0 = K exp ( - y 2 2s 2 ) , when kd s £ 1.5 , along
the line y=0, the normalized ion distribution is equal to K. For the normalized step size of 1.5,
the constant is K =
2p
= 1.671 . Extending the domain for K one can write:
1.5
ì 2p
s
ï
K = í kd
ïl 2ps
î
The condition
kd
£ 1.5
s
for kd = 0
for 0 <
kd
2 2 ln 2kd
£ 1.5 is equivalent with
£ 1.5 and can also be written in
s
FWHM
a simplified form as:
Beam diameter
k £ 0.637
smallest step size
(1.33)
For example, our Orsay Physics FIB machine has d = 7.71 nm (for an acceleration
voltage of 30 keV) and, for a beam size of 150 μm, the maximum multiple k to obtain a
uniform dose during implantation process is 12, but for a beam size of 30 μm the maximum
value of k is 2.
If the step kd / s > 7 one obtains instead of a line an array of implanted spots.
18
Chapter 1: Short introduction to focused ion beam implantation
Figure 1.10: Three dimensional ion distribution of a line implanted along Ox-direction for various normalized
distances between two successive pixels (kd/σ): (a) kd/σ = 7; (b) kd/σ = 3; (c) kd/σ = 1.5; (d) comparison between
the lines of constant ion distribution (the color map corresponds to that from (c) ) and beam diameters defined as
FWHM of the distributions (green circles), when the normalized distance between two successive pixels is 1.5.
Figure 1.11: (a) The ion distribution along the implanted line. The overlap effect “starts” to become visible for
K=1, i.e. kd / s = 2p (equation (1.31) ), but can be clearly seen for a normalized step size less than 2. The
constant line corresponding to kd/σ = 1.5 (equation (1.32) ) has a value of 1.671. (b) A transversal section of the
implanted line. When the individual Gaussian distributions overlap, the height and width of the total ion
distribution change in such a manner that the FWHM remains constant.
19
Chapter 1: Short introduction to focused ion beam implantation
Even if the line is uniformly implanted, the exact calculus for the implantation dose is
not as simple as it appears, because not the total number of ions, which are implanted into the
Il
line
target, N tot
= l N0 =
, should be considered, but only the ions implanted in an area of
n C ion e
length L = l kd and width equal with the beam diameter:
N
line
FWHM
N0
=
2ps 2
æ ( x - ikd )2 ö
æ y 2 ö +¥ l
exp ç ÷dx
2
ò exp çè - 2s 2 ÷ødy -¥ò å
ç
÷
2
s
i =0
2ln 2s
è
ø
+ 2ln 2s
-
é 1 + 2ln 2s
æ y2 ö ù
line
N FWHM
= N 0l ê
exp
ç - 2 ÷dy ú ; 0.76 N 0l
ò
è 2s ø úû
êë 2ps - 2ln 2s
In this case:
0.76 N 0l
0.76 I l n
0.76 I
D line =
=
=
ion
B(l kd ) B (lk d ) C e Bk dn C ion e
(1.34)
The dose when the implanted region is an area
When the implanted region is an area one can consider the implanted region to be a
sum of lines very close one to another. In this case the number of implanted ions can be
calculated considering that the area given by the number l x × l y of discrete points, situated at
the distance k × d , is A = l x ( k d ) × l y ( k d ) = k 2 d 2l xl y and the time of implantation is given by
t=
l xl y
n
.
The ion distribution will be a sum of Gaussian-shape spots given by (1.24), which
written in Cartesian coordinates will be:
N0
n ( x, y , s ) =
2ps 2
é æ x - ik d ö2 ù l y
é æ y - jkd ö2 ù
exp ê - ç
å
÷ ú × å exp ê - ç
÷ ú.
i =0
êë è s 2 ø úû j =0
êë è s 2 ø úû
lx
(1.35)
Again, introducing the normalized coordinates by standard deviation, xn = x s , yn = y s
one obtains
n ( xn , yn , s ) =
N0
2ps 2
2
2
l
é 1æ
é 1æ
ikd ö ù y
jkd ö ù
exp
x
×
exp
y
ê ç n
ê ç n
å
÷ ú å
÷ ú.
s ø úû j =0
s ø úû
i =0
êë 2 è
êë 2 è
lx
area
Considering that the total number of ions from the target is N tot
=
(1.36)
I ×l x ×l y
n × C ion × e
and
comparing to equation (1.29) one can write
l
æ ( x - ikd )2 ö
æ ( y - jkd )2 ö
+¥ y
exp ç ÷ dx = l x 2ps and ò å exp ç ÷ dy = l y 2ps .
2
2
ò-¥ å
-¥
ç
÷
ç
÷
2
s
2
s
i =0
j =0
è
ø
è
ø
For a step kd / s < 1.5 the normalized ion distribution becomes practically constant
with a value of 2.792. Decreasing further the normalized step size this value increases, but the
distribution preserves the constant-like character.
+¥
lx
20
Chapter 1: Short introduction to focused ion beam implantation
Considering that the implanted area A = k 2 d 2l xl y is sufficient large to neglect the
number of ions from edges (Figure 1.12 (c) ) the dose of implantation becomes
I
D area = 2 2 ion .
nk d C e
(1.37)
Figure 1.12: (a) Three dimensional ion distribution of an implanted area when the normalized distance between
two successive pixels is 1.5; (b) comparison between the lines of constant ion distribution (the color map
corresponds to that from (a) ) and beam diameters defined as FWHM of the distributions (blue dot circles), when
normalized distance between two successive pixels is 1.5; (c) The overlap effect of the ion distribution can be
clearly seen for a normalized step size less than 2. The constant line corresponding to kd / s = 1.5 has a value of
2.793. For smaller step sizes this value increases. (d) Normalized ion distribution along a fixed line ( y / s = 5 ).
One can see that the maxima for a normalized step size kd / s = 5 are higher than those corresponding to a
smaller normalized step size of 3.5 because the maxima of the Gaussian functions are not situated on the line
which corresponds to kd / s = 3.5 .
1.6
The performance of a focused ion beam system
The performance of the FIB column is usually given by the size of the focused ion
beam. As simple as it would appear to be, the determination of the beam size was the subject
for many published papers. The most simple, but inaccurate method for the calculation of the
beam size is called addition of aberrations in quadrature. According to this method the
focused beam size is calculated as the sum of square contributions due to the source size and
the lens aberrations:
21
Chapter 1: Short introduction to focused ion beam implantation
2
2
d 2 = d sph
+ d chr
+ d so2 ,
(1.38)
where:
1
DE
d sph = CSa 3 , d chr = CC
a and d so = M d and CS and CC are the spherical and
2
E
chromatic aberrations, respectively, DE is the width of the energy distribution, E the beam
energy, a is the beam-limiting aperture half angle, M is the magnification and d is the source
size. Because the method does not take into account the actual current density distribution at
the target plane, but assumes that it is uniform, the predictions of the method are often
inaccurate. Sato and Orloff [36, 37] have shown that the current density distribution changes
rapidly with the change in focus condition so that in a more precise calculation one should
also consider the geometrical optics with third-order aberration theory.
The FIB columns are used not only for imaging, as in the case of the scanning electron
microscopes, therefore the definition of performance should also take into account the
purpose for which the system is being used. Two definitions of performance are currently
used:
(i) if the purpose of the FIB system is imaging then the resolution of the FIB optics can be
defined in terms of the optical transfer function and defines the contrast as a function of
the spatial frequency response of the optical system. This is given by the two-dimensional
Fourier transformation (Hankel transformation) of the current density distribution of the
beam [36]. The optical transfer function is a measure of the maximum spatial frequency at
which a given amount of contrast is discernible. In this case the beam size ( f 0.1-1 ) is defined
as the reciprocal of the spatial frequency at which the amplitude falls to 10 % of its
maximum which corresponds to Rayleigh’s criterion [38]. The Rayleigh criterion can be
interpreted in terms of the ability of the optical system to resolve spatial frequency, that is,
how the contrast produced in an image changes as the details in the object get finer and
finer.
(ii) The second definition of performance refers to
a FIB system which is used in
micromachining, lithography, deposition, or
implantation and considers more appropriate to
use the integral of the current density
distribution as it would be measured by
sweeping the ion beam across a knife edge
[39]. The corresponding beam diameter may be
defined from the current profile given by the
integral of the current distribution as the
distance ( D15-85 ) from 15 % to 85 % of the
current (Figure 1.14).
The Figure 1.13 shows the characteristics
of the beam sizes, as defined above, which were
calculated from the current density profile and
from the spatial frequency response as a function
22
Figure 1.13: Characteristics of the beam sizes
D15-85 which corresponds to the beam current
from 15% to 85% measured by a knife edge, and
f0.1-1 defined from spatial frequency response,
compared with intensity at the beam center I center,
as a function of focusing position (Ref. [36]).
Chapter 1: Short introduction to focused ion beam implantation
of focus position. A comparison with the axial intensity of the beam for the case of large
aberrations is also plotted. It is worth to be noticed, that the focusing positions for minimum
beam size according to the two definitions are different because the distance D15-85 is
determined by the shape of the beam tail, while the value of f 0.1-1 is mainly determined by the
sharpness of the central distribution.
It was also demonstrated [36] that in an optical system with a large amount of
spherical aberrations the best resolution, as defined by the spatial frequency response of the
system, will be found in a plane where the current distribution has a maximum of intensity on
the axis. This plane shows the best resolution, so that when focusing the optical system, the
eye will naturally choose it. The problem which arises is that the area covered by the tails, can
be so large compared to the central peak, that they will contain a significant fraction of the
total beam current. Figure 1.15 shows that, when one optimizes the spatial resolution, the
current distribution tails are very long. The main conclusion is that for FIB systems used for
processes for which a small current density distribution is needed (milling, deposition,
implantation), it is necessary to focus the beam in such a way that the rise distance ( D15-85 ) is
a minimized, which also means the tails are minimized.
Figure 1.14: Two different approaches for estimating the
beam size from calculated current distribution of beams.
(Left) An estimation from the current profiles given by
integral distribution as the beam is swept over a knife edge;
(Right) An estimation from the spatial frequency responses
which are given by the Fourier transformation of the current
distribution of the beams (Ref. [36]).
Figure 1.15: The calculated current density
distribution for a FIB system when minimizing
the rise distance of the beam across a knife
edge D15-85 and optimizing the spatial
resolution f0.1-1 (Ref. [39]).
In conclusion, the “resolution” for deposition, milling or implantation, which
corresponds to the beam size defined by D15-85 may be much worse than the “resolution” for
imaging which corresponds to the beam size defined by f 0.1-1 . When the total current is
important it might be necessary to consider the implications of the beam current density
profile and a careful analysis of the optical system should be performed because the best focus
that minimizes the tails would not correspond to the visually-adjusted best focus of the beam.
23
– Chapter 2 –
Samples preparation
2.1
Molecular beam epitaxy
The state-of-the art semiconductors growth technique, molecular beam epitaxy (MBE)
is defined as the epitaxial growth onto a substrate from the condensation of directed beams of
molecules or atoms in a vacuum system. The term epitaxy is derived from the Greek words
epi (meaning “on”) and taxis (meaning “arrangement”) [40] and describes the crystalline
growth of one material on the same (homoepitaxy) or on a different material (heteroepitaxy).
The origin of MBE use in the epitaxial growth of compound semiconductors is difficult to
assess because, on one hand, the technique was not well defined in the earlier works, and on
the other hand, because the experimental conditions were not clearly specified. W. Hänley
and Günter [41] were probably the first who described the technique and Schoolar and
Zeemel have grown epitaxial PbS on NaCl, using for the first time molecular beam ovens.
Although Günter and co-workers had significant contributions to the development of growing
both the III–V and II–VI compounds using multiple ovens, the epitaxy of GaAs was achieved
by Davey and Pankey [42]. Arthur [43] studied the reaction kinetics of Ga and As2 on GaAs
surface that led to the understanding of the growth mechanism. Films of GaAs and related
compounds of superior quality and extreme smoothness were obtained in the following years
by Arthur and LePore [44], Cho [45, 46] and Esaki and co-workers [47, 48].
In spite of the simplicity of the starting ideas about how this method should work, it
took years until complete understanding of the physics and chemistry, which this technique
implies, was achieved. A modern MBE consists usually of an interconnected system of
ultra-high vacuum (UHV) chambers with different purposes: the main chamber – the chamber
in which the growth occurs, a buffer chamber – generally used to store the wafers, but in some
MBE systems this chamber has also the necessary equipment for the sample characterization,
and the loading chamber – the chamber involved in transferring the wafers in and out of the
vacuum environment, hence giving the possibility to keep the vacuum in the other two
chambers intact during this operation. A main chamber for MBE depositions is presented in
Figure 2.1. The UHV (~10-11 Torr), one of the most important conditions for the entire
process, is realized with turbomolecular and ion pumps. The epitaxy materials, stored in the
effusion cells are independently heated until the desired material flux is achieved. Computer
controlled shutters are positioned in front of each of the effusion cells, being able to block the
flux reaching the sample within a fraction of a second. Within the ultra-high vacuum, the free
24
Chapter 2: Samples preparation
atoms emitted from the heated effusion cells have a long mean-free path, so that the atoms are
able to travel in a straight line until they collide with the substrate material. The UHV
environment in the growth chamber might also be one of the attractive points of this method
as it allows the application of various in-situ measurement techniques to study the
fundamental processes governing crystal growth.
The controlled epitaxial growth of the new layer under UHV conditions is performed
by using very low rates of impinging atoms, migration on the surface and subsequent surface
reactions. In simple words: every atom reaching the surface of the heated substrate has
enough time to migrate around and find its place to build up a new crystal lattice. In order to
monitor in-situ the growth process, an accurate, quick and direct measure of the growth rates
is given by the reflection high-energy electron diffraction (RHEED). RHEED can be used to
calibrate growth rates, to observe removal of oxides from the surface, to calibrate the
substrate temperature, to monitor the arrangement of the surface atoms, to determine the
proper arsenic overpressure, to give feedback on surface morphology, and to provide
information about growth kinetics.
Usually,
a
RHEED
measurement system consists of
an electron gun, a fluorescent
screen and an image processing
hardware. The electron gun is
designed with a typical focal
length of about 0.5 m, combined
with a very low divergence of the
beam [49]. This ensures a small
spread
of
the
diffraction
conditions for the electrons and
the sampling of a small and
therefore relatively homogeneous
area of the sample. In the ideal
case, the beam consists of
electrons that propagate in the
same direction with the same
Figure 2.1: A typical MBE system growth chamber
energy and hit the sample at the
same location. Typical acceleration voltages for the electrons range from 10 kV to 30 kV.
This high energy is necessary to image a sufficiently large area of the reciprocal space into a
relatively small solid angle of the fluorescent screen. The angle at which the electron beam
strikes the sample surface is 0.5º–2º, this being the main reason for the extremely high surface
sensitivity of the method. The reflected electrons strike then a phosphorescent screen, where
the reflection and diffraction pattern, give information about the surface crystallography. In
order to analyze the information RHEED gives, a charge-couple device (CCD) camera
monitors the screen and can record instantaneous pictures with the necessary time resolution
or measure the intensity of a given pixel as a function of time.
25
Chapter 2: Samples preparation
When molecules arrive at the substrate, they can adsorb, migrate on the surface,
interact with other atoms, incorporate into the crystal, or desorb (Figure 2.2). The primary
controllable factors that affect this process are the surface, the temperature of the substrate,
and the incident fluxes. At substrate temperatures used for the growth of GaAs
(~580 ºC - 650 ºC) one should consider all processes that may occur, in order to obtain good
quality samples. For example, arsenic desorbs from surface of GaAs preferentially, requiring
an As overpressure to prevent the surface from becoming Ga rich. The growth rate can
depend also on many other factors some of them being: temperatures of the effusion cells, the
sticking coefficients, As overpressure, the substrate temperature, or the alloy composition.
A measure of the growth rate in the MBE chamber is given with a very good precision
by the RHEED intensity oscillations, as the oscillation frequency corresponds to the
monolayer growth rate [50]. Considering that the growth is initiated on a smooth GaAs
surface, a monolayer (ML) is the thickness of one full layer of Ga and one full layer of As
atoms. At the very beginning, the layer is smooth, the specular spot is bright, so one obtains a
maximum. Then, the layer nucleates, islands form on the surface, the specular spot dims, so
that the intensity decreases. When a new layer is completely grown, the islands coalesce into a
flat layer, and the specular spot intensity increases again. The process is illustrated in
Figure 2.3.
Figure 2.2: The main surface processes occurring during the
epitaxial growth. The atoms from the source can be adsorbed
(a) and diffuse on the surface as adatoms (b), they can meet
and lead to the formation of islands (c) or attach to preexisting
islands (d) and steps (g) or deposit on the island (f). The atoms
belonging to islands or terraces can detach and diffuse again (e)
or desorb (h). (The dark blue color represents the atoms, which
are not in direct contact with the substrate represented by red).
Figure 2.3: Monolayer growth controlled by
RHEED intensity oscillations. The scattering
becomes maximum for either half ML
coverage ( θ = 0.50 ) or when a new ML is
completed ( θ = 1.00 ).
A major advantage of the method consists in the fact that no complicated chemical
reactions take place at the surface. This facilitates the analysis of growth processes like
surface migration and dopant incorporation.
There are three possible different mechanisms for the crystal growth of the new layer,
a classification used worldwide today, being given since 1958 by Ernst Bauer [51], who
26
Chapter 2: Samples preparation
named each one after the investigators associated with their initial description: Frank-van der
Merwe [52] or layer-by-layer growth mode, Stranski-Krastanow [53] or layer-plus-island
growth mode and Volmer-Weber [54] or island growth mode (Figure 2.4).
In layer-by-layer growth mode the interaction between the substrate and the layer
atoms is stronger than between neighboring atoms. Each new layer starts to grow, only when
the last one is completed. If, on the contrary, the interaction between neighboring atoms is
stronger than the overlayer-substrate interaction, the particles will rather form aggregates over
the surface that grow in size and eventually coalesce during film growth. This is named the
island growth mode. The layer-plus-island growth mode is an intermediate case where the
film starts to grow layer-by-layer in a first stage and at certain coverage begins the formation
of island agglomerates.
Frank-van der Merve
(layer-by-layer)
Stranski-Krastanow
(layer + island)
Volmer-Weber
(island)
Figure 2.4: Illustration of the three heteroepitaxial crystal growth modes of a material A (blue) on a material B
(red) for different stages of deposition: the surface is covered with an incomplete monolayer, q < 1; the first layer
is complete and the second layer is forming, 1 < q < 2 (for layer + island and island mode the number of atoms
which deposit on the third monolayer is not sufficient to completely fill the second monolayer); more than two
monolayers are already deposited, q > 2. The different blue colors represent the same material A, but different
monolayers (a guide for the eye).
The success of MBE in research and development of well-defined heterostructures on
nanometer scale has not only led to fundamentally new phenomena such as the quantum Hall
effect [55] and the fractional quantum Hall effect [56, 57], but has also revealed new
technologies, e.g. double heterojunction laser [58], higher electronic speed devices [59], and
“band gap engineering” of materials [60]. All these studies were based on high-quality layers
with very abrupt interfaces and good control of thickness, doping, and composition realized
by MBE. It is not surprising that MBE has experienced a tremendous development and
nowadays includes the growth of group IV, III-V and II-VI semiconductors, metals, magnetic
materials, oxides and fluorides using solid and gaseous as well as metal-organic sources.
27
Chapter 2: Samples preparation
The MBE has a major importance also for the present work because the base materials
used for the fabrication of the IPG transistors are p- and n-doped heterostructures grown in
our group by this technique.
The p-doped heterostructures used for positive pattern definition devices
The p-doped heterostructures were grown on GaAs (100) substrates and consist of the
following succession of materials (Figure 2.5): 50 nm GaAs, a superlattice of 10 × GaAs
(5 nm) / AlAs (5 nm) which plays the role of
smoothing the surface and prevents the
impurities to segregate from the substrate,
followed by a GaAs buffer layer of 100 nm.
Then, a quantum well defined by 3 layers was
grown: the first one being Al0.34Ga0.66As with
the thickness of 200 nm, the second a GaAs
layer of 15 nm, which also defines the width of
the quantum well, and the third a 20 nm layer of
Al0.34Ga0.66As. Then, during the MBE growth, a
C-delta doping step was performed. After this
Figure 2.5: The layer sequence for the p-doped
step, the heterostructure growth continued with: heterostructures (wafers: 11994, 12165, 12290 and
a 9 nm Al0.34Ga0.66As layer, a short period 12491).
superlattice (SPS) formed by 17 periods of GaAs (2 nm) / AlAs (1 nm) and finally a GaAs
C-doped cap layer. For these structures, at room temperature, in the dark the typical hole sheet
density is p= 8.3 × 1011 cm-2 and the corresponding mobility is about μp= 200 cm2/(Vs).
The n-doped heterostructures used for positive pattern definition devices
The n-doped heterostructure has the same material structure but the dimensions of
layers were adjusted according to a previously SRIM simulation so that the ions should reach
the quantum well. The sequence of layers is
(Figure 2.6): 50 nm GaAs, a superlattice of
10x GaAs (5 nm) / AlAs (5 nm), 100 nm GaAs,
200.7 nm Al0.34Ga0.66As, 15 nm GaAs, 20.1 nm
Al0.34Ga0.66As, Si–delta doping step which
assures the n-doping type of the heterostructure,
9 nm Al0.34Ga0.66As, SPS 35 × GaAs (2 nm) /
AlAs (1.1 nm), 5 nm GaAs Si-doped cap layer.
At room temperature, in the dark, the typical
electron sheet density is n= 6.0 × 1011 cm-2 and
the mobility is about μn= 7000 cm2/(Vs).
Figure 2.6: The layer sequence for the n-doped
heterostructures (wafer: 12341).
28
Chapter 2: Samples preparation
The n-doped heterostructures used for negative pattern definition devices
Using molecular beam epitaxy an 81.2 nm undoped buffer on a semi-insulating
GaAs (100) wafer was grown, followed by an AlAs/GaAs superlattice with a total thickness
of 72 nm and another buffer of 53 nm. The following two layers are a pseudomorphic 12.7 nm
In0.21Ga0.79As one and a 4 nm thick Al0.20Ga0.80As spacer both of them undoped. Then, a
57 nm Si (2 × 1018 cm-3) doped layer of Al0.20Ga0.80As, covered by a 5 nm cap layer of
Al0.20Ga0.80As follows. This leads to a high electron sheet density of n= 9 × 1011 cm-2 and a
mobility of μn= 5500 cm2/(Vs) at room temperature in the In0.21Ga0.79As quantum well.
Another heterostructure was also grown without InGaAs layer, for which the sequence of
layers can be seen in Figure 2.7.
Figure 2.7: The layer sequence for the n-doped heterostructures (left: wafer 1068, right: wafer 1091).
After preparation, the p-doped heterostructures were implanted with Si2+ ions while
the n-doped ones with either Be+ (wafer 12341) or Ga+ (wafers 1068 and 1091) ions. For the
samples implanted with Si2+ and Be+ the acceleration voltage was VAcc= 30 kV, which
corresponds to an energy of E= 60 keV for Si2+ ions and 30 keV for Be+ ones. As it was
already mentioned, the layers dimensions were calculated using the SRIM software, so that
according to the range of Si2+ and Be+ ions in corresponding type of heterostructure the ions
should reach the quantum well. For the samples implanted with Ga+ the acceleration voltage
was 100 keV. The ion beam diameter was in all situations about 100 nm.
Table 2.1 – Samples details
Heterostructures used for negative
pattern definition devices
n-doped heterostructures
Wafers: 1068, 1091
Implanted with Ga+ at 100 keV using
an EIKO-100 FIB machine.
The two-dimensional electron gas is
situated at about 65 nm (for sample
1068) and 105 nm (for sample 1091)
under sample surface.
Heterostructures used for positive
pattern definition devices
p-doped heterostruct. n-doped heterostruct.
Wafers: 11994, 12165, Wafer: 12341
12290, 12491 and
11929 (without SPS).
Implanted with Si2+ at Implanted with Be+ at
60 keV using an Orsay 30 keV using an Orsay
Physics FIB machine.
Physics FIB machine.
The two-dimensional The two-dimensional
hole gas is situated at electron gas is situated
85 nm under sample at about 145 nm under
surface.
sample surface.
29
Chapter 2: Samples preparation
2.2
Rapid thermal annealing
During the FIB implantation the accelerated ions produce dislocations in the crystal
and the electrical parameters of the implanted region would be altered. In order to obtain
regions with a good conductivity, one should perform a thermal annealing process, in order to
heal these defects and to electrically activate the ions. This thermal annealing should be
sufficiently fast not to damage the heterostructure by one of the following reported
degradation mechanisms: diffusion of the dopant atoms (Si) towards the heterointerface
[61-63], compensation of the Si doping due to As loss during the annealing or structural
changes which may occur in the layer structure [64]. For these reasons the conventional
furnace annealing is inappropriate for GaAs/AlxGa1-xAs heterostructures and is replaced by
rapid thermal annealing (RTA), which, usually lasts from few seconds until maximum few
tens of seconds. A typical sketch of a RTA furnace is presented in Figure 2.8. The electrical
activation has been obtained in Si-implanted GaAs using RTA with halogen lamps in a
flowing N2 [65]. This technique has already been applied to devices as metal semiconductor
field effect transistors (MESFETs) [66, 67]. In our case, for the IPG transistors obtained by
implanting conductive regions (IPG transistors written in positive mode pattern definition),
immediately after the implantation process, the samples were annealed at T= 750 ºC for 30 s
in an RTA furnace (produced by AST), which permits during this step to keep the sample in a
laminar nitrogen flow.
Figure 2.8: Schematic drawing of the (AST) RTA reactor unit .
The As loss which could occur at this high temperature is prevented by two factors,
the first one is the existence of the SPS [68] at the sample surface, the second is an
experimental technique to cover the samples “face-to-face” with a fresh GaAs wafer [69, 70].
The SPS alone prevents the As loss by two mechanisms: first, the out-diffusion of As atoms is
almost completely prevented due to the large number of interfaces in SPS, and the second the
binding energy for As is higher in SPS [68] than in Al0.34Ga0.66As.
30
Chapter 2: Samples preparation
2.3
Photolithography
Photolithography or optical lithography is the process used in semiconductor device
fabrication to transfer a pattern from a photomask to the surface of a substrate. The term
comes from the Greek “light-stone-writing” and is similar to the process of developing a
photographic film in the dark room.
The photomasks were either created using an advanced graphic software (like Corel
Draw, etc.) or CAD, the layout printed on DIN A0 paper, and with a photo camera transposed
on a glass substrate or industrially fabricated chrome masks. The last were especially used in
the fabrication of IPG transistors written in the negative pattern definition and are
high-resolution ultraviolet (UV) lithography masks. Complete details for all mask layouts
used in this work can be seen in Appendix B. A full description of the realization of the
photomasks can be found in Ref. [71], while a good reference for the lithography in general is
Ref. [72].
The mesa definition
The steps of the mesa definition are illustrated in Figure 2.9. Before the resist was
applied to the substrate, the surface was carefully cleaned with acetone in an ultrasonic bath
followed by another bath of isopropyl alcohol. Then, a positive photoresist (Shipley
Microposit SP25-10) was applied to the surface, and the structure was rotated with high speed
(3200 - 4000 rpm) for a period of 15 - 30 seconds using a spin-coating machine. The
preparation of the photoresist ended with a soft-bake, i.e. the wafer was heated in an oven for
15 minutes, at 100 °C, in order to evaporate the resist solvent and to solidify the photoresist.
·
Figure 2.9: The mesa definition steps: a) the positive resist (red) is applied to the substrate (green); b) the
sample and the mask are put in contact mode; c) illumination with UV; d) after developing process; e) after
etching; f) mesa definition – final state.
31
Chapter 2: Samples preparation
The next step consists in mask alignment and exposure, these being performed with a
Karl Süss MJB 3 photolithography machine which has a mercury lamp with emission in
middle UV (365 nm). The resolution (for our structures it was about 2 mm) is limited by the
diffraction limit and depends on the size of this wavelength used to illuminate the mask. First
the mask is aligned with the substrate, and then they are put in contact mode in order to
eliminate the diffraction at the edges of the mask features. Then the photoresist is illuminated
for 40 s through the mask. All over the exposed regions of the photoresist a chemical reaction
occurs. Depending on the chemical composition of the photoresist, it can react in two ways
when the light strikes the surface. The action of light on a positive resist causes it to become
polymerized in the exposed area and becomes soluble in a developer (Shipley Photoposit 160
Developer). A negative resist has the reverse property. After the developing process, a
positive/negative (depending on the type of the resist) of the mask remains as a pattern of the
resist on the substrate surface.
The last step is the post-baking, performed in the oven for 10 minutes at 100 °C,
which ensures that the resist strongly adheres to the substrate and also that the viscosity
parameters of the resist permit to start the etching with a good resolution. The conductive
regions left after etching, for which the transport properties will be studied are called mesa.
Etching
In order to finalize the aim of transposing the mask layout on the substrate, after the
photolithography process for defining the mesa structures, a chemical etching(*) was
performed. For the etching it was used a solution of H2O : H2O2 : H2SO4, which, depending
on the elements concentrations, provides different speeds for the etching rate.
·
Table 2.2 – The etching rates
Etching rate [ nm min ]
H2O : H2O2 : H2SO4
1000 : 8 : 1
50 : 1 : 1
30 : 1 : 1
30 : 1 : 2
35
75
125
140
The etching rates are
presented in Table 2.2. The etching
time was set so that to obtain a depth
of 200–250 nm below the two
dimensional electron or hole gas
from within the heterostructure, in
order to electrically isolate the mesa
from each other. For these etching
depths also the underetching can be
neglected in comparison with the Figure 2.10: The view of an etched mesa using the interferometer
microscope (Zygo). The etch depth is around 300 nm.
(*)
The etching process is believed to have been invented by Daniel Hopfer (circa 1470-1536) of Augsburg,
Germany, who decorated armour in this way, and applied the method to printmaking.
32
Chapter 2: Samples preparation
mesa dimensions.
The etching depth was checked with an interferometer microscope ZYGO
(Figure 2.10) and the values found were in good agreement with the expected ones. After this
checking was performed the samples were ready for the next step: photolithography for
contacts.
Photolithography for contacts
For contact definition the steps are similar (Figure 2.11) but two different resists were
applied as it will be explained in the following: after the cleaning the substrate surface, a
lift-off resist (Shipley Microposit LOL 2000) was first applied and its thickness was
homogenized on the spinner at about 3800 rpm for 30 seconds.
·
Figure 2.11:a) substrate with mesa structures (last step in mesa definition); b) substrate + lift-off resist + positive
resist; c) sample and mask are put in contact mode and illuminated with UV; d) The sample in the final state.
This lift-off resist was then baked in air, on a hot plate at 150 °C for 5 minutes. Then
the positive resist SP 25-10 was applied exactly in the same manner and all other steps
followed as it was aforementioned in the mesa definition paragraph.
2.4
Ohmic contact deposition, alloying and bonding
Because all contacts prepared in this work need to have an ohmic behavior, but the
heterostructures are n- or p-type doped, two different recipes (Table 2.3) for the contact
thermal evaporation were used. One recipe, based on Au-Ge-Ni [73, 74] was used for the
33
Chapter 2: Samples preparation
n-doped heterostructures and in the following sections these contacts will be referred to as
n-type contacts. The other recipe, based on Au-Zn [40, 75] was evaporated on p-doped
heterostructures and in the following sections these contacts will be referred to as p-type ones.
Table 2.3 – The receipts used to evaporate ohmic contacts on n- and p-doped heterostructures
n-doped heterostructure
(n-type contact)
Thickness
Layer nr.
Element
[nm]
1
Ni
10
2
Ge
60
3
Au
120
4
Ni
10
5
Au
100
p-doped heterostructure
(p-type contact)
Thickness
Layer nr.
Element
[nm]
1
Au
40
2
Zn
40
3
Au
200
The presence of the first Ni layer tends to hold the Au-Ge melt in intimate contact
with the substrate at the alloying temperature. The result is that the contact becomes more
uniform distributed over the surface of the semiconductor.
The order of the deposition of the following three layers depends on the temperature
required to attain a specified vapor pressure. That is the reason why Ge evaporates first (e.g.
1251°C at 10-2 torr) followed by Au (1465 °C) and then Ni (1510 °C). During the substrate
heating the Au and Ge alloy at the eutectic temperature, and because Ni has a low solubility in
Au-Ge alloying, the Ni layer remains intact and covers the Au-Ge on the substrate surface.
The last Au layer is then deposited having the purpose to protect the Au-Ge-Ni formed alloy
especially during the bonding (wiring) step.
Different models for the Au-Ge-Ni ohmic contact had been proposed [76], and the
measurements have shown that the tunneling is responsible for the ohmic behavior.
After the contacts were deposited, the samples were dipped in a NMP (1-methyl-2pyrolidon, C5H9NO) solution and kept for about 30 minutes in order to dissolve the lift-off
resist and to remove the unwanted evaporated metallic regions. Practically, only the metal
directly evaporated on the heterostructure remains, all other regions being removed together
with the lift-off resist. In order to contact the two-dimensional electron or hole gas an
annealing step followed. Depending on the contact recipe used, the contacts were annealed at
different temperatures as one can see in Table 2.4.
Table 2.4 – Annealing temperatures for the contacts
(n-type contact)
400 °C
(p-type contact)
385 °C
Because the temperature to anneal the n-type contacts is higher, it is important that
these contacts to be deposited and processed first.
The last step of the preparation procedure includes the sample mounting into a chip
carrier and bonding the necessary contacts to the chip carrier pins.
A diagram containing all processing steps for both positive and negative pattern
definition devices obtained in this work is provided in Appendix C.
34
– Chapter 3 –
Field-effect transistors - theoretical aspects
3.1
MOSFET
The principle of operation of the field-effect transistors is based on the control of the
electrical current flowing through the device by applying an electric field. The current flows
through a channel and the electric field controls the conductance of the channel. This current
that flows between one electrode usually named Source (S) and another named Drain (D) is
formed by majority carriers from the channel, so that only one type of carriers participate at
the conduction, and that is the reason for which the field-effect transistor (FET) is also known
as unipolar transistor. Depending on the majority carrier type from the channel there are two
types of FET’s: n- and p-type channel FET. The electrode, on which the control electric field
is applied, is called Gate (G).
Due to its low fabrication cost, small size and low power consumption the
metal-oxide-semiconductor FET (MOSFET) is the most important device for very-large-scale
integrated circuits. The MOSFET, the bipolar transistor, the p-n junction and the Schottky
barrier diode are estimated to be the most used active elements in electronics. The MOSFET
has many different acronyms: IGFET (insulated-gate FET), MISFET (metal-insulatorsemiconductor FET) or MOST (metal-oxide-semiconductor transistor).
MOS Structure
The channel formation in a MOSFET transistor is based on the existence of an
inversion layer at the oxide-semiconductor interface. In order to explain how this inversion
layer is formed it shall be considered in the following section an ideal MOS structure, as
shown in Figure 3.1. A MOS structure is considered ideal if three requirements are fulfilled:
1) The band is flat when no voltage is applied. This condition implies that the energy
difference between the metal work function(*) fm and the semiconductor work
function is zero when no voltage is applied.
2) Under any biasing condition, the charge that exists in the structure is the charge
from within the semiconductor and the charge equal but of opposite sign on the
metal surface, adjacent to the oxide.
(*)
The work function is the least amount of energy required to remove an electron from the surface of a
conducting material, to a point just outside the metal with zero kinetic energy. Therefore, the work function
is the energy difference between the Fermi level and the vacuum level [77].
35
Chapter 3: Field-effect transistors – theoretical aspects
Figure 3.1: Energy band diagrams for an ideal MOS structure, n- (left) and p-type semiconductor (right) at:
a) V= 0; b) accumulation; c) depletion; d) inversion.
36
Chapter 3: Field-effect transistors – theoretical aspects
3) There is no carrier transport through the oxide under direct biasing condition (the
resistivity of the oxide is infinite).
Figure 3.1 a) presents an ideal MOS structure. If we define the potential f ( x) as:
qf ( x) = EF - Ei ( x) ,
(3.1)
where EF and Ei ( x) are the Fermi and the intrinsic energy levels, respectively. For x ® ¥
i.e. deep in the bulk semiconductor, the potential is called bulk potential fB . For x= 0 the
potential is called surface potential fS .
The band-bending is defined as [78]:
y ( x ) = f ( x ) - fB
(3.2)
and represents the potential at the point x in the depletion layer with respect to its value in the
bulk. At the semiconductor surface the barrier height y S = fS - fB is the potential difference
between semiconductor surface and bulk, meaning that y S is the total band bending. In
Figure 3.1 the sign conventions are the general accepted ones [78]: an arrow pointing down
denotes a positive potential, an arrow pointing up denotes a negative potential.
The electron and hole concentrations can be written as functions of f ( x) :
æ E - Ei ( x) + Ei ( x) - EF
n( x) = N c exp ç - c
k BT
è
ö
æ EF - Ei ( x) ö
æ qf ( x) ö
÷ = ni exp ç
÷ = ni exp ç
÷ (3.3)
k BT
ø
è
ø
è k BT ø
æ E - Ei ( x) ö
æ qf ( x) ö
p ( x) = ni exp ç - F
(3.4)
÷ = ni exp ç ÷
k
T
k
T
B
B
è
ø
è
ø
It can be shown that the electron concentration as function of y for a MOS structure
with an n-type semiconductor [78] is:
æ qy ( x) ö
n( x) = N D exp ç
÷
è k BT ø
and analogous:
(3.5)
æ qy ( x) ö
p ( x) = N A exp ç ÷
è k BT ø
At the surface the equations will be:
(3.6)
æ qy ö
nS = N D exp ç S ÷
è k BT ø
(3.7)
æ qy ö
pS = N A exp ç - S ÷
(3.8)
k
T
B
è
ø
The flat-band condition (the first requirement for an ideal structure) can be written as:
E
æ
ö
fms = fm - ç c + g - fB ÷ = 0
2q
è
ø
(*)
(*)
Please note that according to the aforementioned sign convention fB < 0 for p-type semiconductors and
f B > 0 for n-type semiconductors.
37
Chapter 3: Field-effect transistors – theoretical aspects
where fms is the energy difference between the metal work function fm and the
semiconductor work function and c is the semiconductor electron affinity.
The flat-band condition is equivalent with: y S = 0 and fS = fB .
Figure 3.1 b) (left) presents the situation: fB > 0, fS > fB , y S > 0 . In this case, the
difference between the Fermi level in the semiconductor EFS and the intrinsic Fermi level Ei is
larger at the semiconductor-oxide interface than in the bulk, so that an excess of electrons will
form at this interface. Figure 3.1 b) (right) presents the situation when y S < 0 and an excess
of holes will appear at the semiconductor-oxide interface. This situation corresponds to the
so-called “accumulation” case.
If the applied potentials are reversed, the bandbending changes the sign, the majority carriers will be
depleted, since the Fermi level at the surface becomes
closer to the intrinsic Fermi level (Figure 3.1c).
When y S = -fB or fS = 0 from (3.7) and (3.8)
one obtains nS = pS the so-called intrinsic point at the
surface. Applying a larger bias, the bands bend even
more, so that at a certain voltage value, the intrinsic
level Ei at the surface crosses over the Fermi level EF
(Figure 3.1d). In this situation the number of minority
carriers at the surface is larger than that of majority
ones, so that at the surface an inverted charge layer will
form. Initially, the surface is in the weak inversion
condition. The criterion for the strong inversion
(Figure 3.2) to take place is that the concentration of
minority carriers coming to the interface should be
equal to the substrate doping level. Considering a MOS
structure with a p-type semiconductor this condition
Figure 3.2: Charge distribution under
becomes: nS = N A . Introducing the value for NA from
equation (3.6) in (3.4) and considering (3.2) one
obtains:
æ qf ö
N A = ni exp ç - B ÷
è k BT ø
Now substituting x = 0 in (3.3), one obtains:
strong inversion condition for a MOS
structure with a p-type semiconductor.
(3.9)
æ q (y S + f B ) ö
æ qf ö
nS = n(0) = ni exp ç S ÷ = ni exp ç
÷
k BT
è k BT ø
è
ø
From (3.9) and (3.10) one obtains the strong inversion case that corresponds to [79]:
(3.10)
2 k BT æ N A ö
ln ç
÷
q
è ni ø
Although strong inversion can be considered to occur for y S = -2fB this value of the
y S ( strong inv) = -2f B =
band bending is only approximate. Another criterion for the onset of strong inversion was
38
Chapter 3: Field-effect transistors – theoretical aspects
proposed by Lindner [80], who suggested that band bending at the onset of strong inversion
should make the minority carrier contribution to the surface field match the dopant ion
contribution.
MOSFET – Basic device characteristics
The structure of a MOSFET transistor fabricated on a p-type semiconductor substrate
is illustrated in Figure 3.3. One of the most used structures is based on silicon-thermally
grown silicon dioxide (Si-SiO2). The gate is the metal contact on the top of the insulator and
the device parameters are: the channel length L (the distance between the two n+-p junctions),
the channel width Z, the insulator thickness d, the junction depth rj and the substrate doping.
Connecting the source to the ground all potentials will be considered with respect to the
source. Now if no voltage is applied on the gate, between source and drain there are two p-n
junctions connected back to back, therefore, the current that flows between these two
electrodes, will be the reverse current (leakage current). When a sufficiently large positive
bias(*) is applied to the gate at the interface semiconductor-oxide an inversion layer is formed
between the two n+ regions. This layer will be in fact the channel that forms between source
and drain. Consequently, a large current, which can be controlled by the gate bias, starts to
flow between these two electrodes.
Figure 3.3: Schematic diagram of an n-type channel MOSFET.
(*)
The Fermi level is defined as [78]: E F = m - qy . The difference between the Fermi levels in a MOS
structure is equal to the applied voltage. In the following it will be used the terminology that the voltage or
bias is the difference between Fermi levels, while potential is the electrostatic part of EF.
39
Chapter 3: Field-effect transistors – theoretical aspects
It can be shown that the source-drain current is [40]:
ID =
ìïæ
V
Z
mnCo íç VG + 2fB - D
L
2
ïîè
2 2e S qN A é
3/ 2
3/ 2 ü
ï
ö
VD - 2fB ) - ( -2fB ) ù ý
(
÷ VD ë
û
Co
3
ø
ïþ
(3.11)
where Co = e ox / d is the gate capacitance per unit area, and fB < 0 for p-type semiconductor.
Analyzing equation (3.11) one can find two interesting distinct regions: the linear and
the saturation one (Figure 3.4). For small drain voltages (3.11) becomes:
Z
I D ; mnCo (VG - VT ) VD for VD << (VG - VT )
(3.12)
L
where VT is the threshold voltage given by:
2e S qN A ( -2fB )
VT =
Co
- 2fB
(3.13)
The channel conductance g D and the
transconductance g m are:
gD º
gm º
¶I D
¶VD
¶I D
¶VG
;
Z
mnCo (VG - VT ) (3.14)
L
;
Z
mnCoVD
L
VG = ct
VD = ct
(3.15)
In the saturation region one obtains for the
saturation drain voltage and current:
æ
2V
VDsat ; VG + 2fB + K 2 ç1 - 1 + G2
ç
K
è
Figure 3.4: Idealized characteristics of an n-type
channel MOSFET.
ö
e S qN A
÷÷ where K º
Co
ø
(3.16)
2
æ Z mnCo ö
I Dsat ; ç
(3.17)
÷ (VG - VT )
è 2L ø
For an idealized MOSFET the channel conductance is zero in the saturation region
while the transconductance is:
g msat º
¶I Dsat
¶VG
=
VD = ct
Z mne ox
(VG - VT )
dL
(3.18)
MOSFETs are classified in four classes depending on the existence of the channel at
zero gate bias and the type of the channel [81]. If at zero gate bias there is no channel or the
channel conductance is so low, that one should apply a positive voltage to the gate to enhance
the formation of the n-channel, then the device is called normally-off and works in
enhancement mode. If at zero gate bias the channel is already formed, one should apply a
negative bias on the gate to deplete the channel. This latter case corresponds to the so-called
normally-on devices, which are working in depletion mode. Because the channel can be n- or
p-type, there are finally obtained four different types of MOSFETs. The electrical symbols, a
cross section view, the output and transfer characteristics are presented in Appendix D.
40
Chapter 3: Field-effect transistors – theoretical aspects
3.2
MESFET
Unlike the MOSFET the metal-semiconductor field-effect transistor (MESFET) uses
for the gate electrode a metal-semiconductor rectifying contact instead of a MOS structure.
Another difference consists in the fact that the source and drain contacts of the MESFET are
ohmic, while for the MOSFET they are p-n junctions. Usually, MESFETs are made of n-type
III–V gallium arsenide, one reason for using these materials being their high electron
mobilities, which minimizes series resistances. Another important reason is their high
saturation velocities, which has as result a substantial increase in the cut-off frequency, so that
the MESFETs fabricated on GaAs have higher switching speeds than MOSFETs with
Si-SiO2. In order to minimize the parasitic capacitances practical MESFETs are fabricated by
using epitaxial layers on semi-insulating substrates as in Figure 3.5. Under normal operation
condition the source is grounded, the gate voltage is zero or reverse biased [82] and the drain
voltage is zero or forward biased [75], i.e. VG £ 0 and VD ³ 0 . Since the channel is of n-type
material, the device is also referred to as an n-channel MESFET.
When the drain voltage is small
the source-drain current varies linearly
with VD. The voltage along the channel
increases from zero, at the source, to VD
at the drain. Thus, the gate rectifying
metal-semiconductor contact becomes
more and more reverse biased as the
distance to the drain decreases. The
depletion region increases with VD, so
that the channel resistance also increases.
The consequence is that the source-drain
current will increase at a slower rate and
when the depletion region touches the
semi-insulating substrate one obtains the
saturation voltage VDsat . For this drain
voltage, the source and drain are
completely separated by the depletion
region, and the corresponding current is
called the saturation current. The point
where the depletion region touches the
semi-insulating substrate is referred as the
pinch-off point. Increasing further the
drain voltage, the depletion region Figure 3.5: (a) Schematic diagram of an n-type channel
MESFET; (b) Electrical circuit.
expands, the pinch-off point will move
toward source but the voltage at this point will remain constant VDsat . Consequently,
increasing VD the current will remain practically at the same value of the saturation
41
Chapter 3: Field-effect transistors – theoretical aspects
(Figure 3.6). Finally, by further increasing VD an avalanche breakdown of the diode gatechannel occurs, and the current suddenly increases. This is the so-called breakdown region.
Figure 3.6: Evolution of the depletion region as a function of drain voltage and gate bias.
3.3
JFET
The junction field-effect transistor (JFET) uses for the gate electrode a p-n junction
and basically the device can be described as a voltage-controlled resistor.
A typical JFET with two gates can be seen in Figure 3.7 and consists in a bulk
semiconductor (for example n-type) with two ohmic contacts, one acting as source, the other
Figure 3.7: (a) Single- and (b) dual-gate JFETs.
42
Chapter 3: Field-effect transistors – theoretical aspects
as drain (in vertical plane) and two gates realized by two p-n junctions (in horizontal plane).
The same working principle presented for MESFET (Section 3.2) is valid for JFET,
the only difference being that the depletion region(s) is(are) now formed at p-n junction(s)
that appear(s) between p-type gate(s) and n-type channel.
3.4
Modulation-doped heterostructures
The carrier transport parallel to the layers of a superlattice was for the first time
imagined by Esaki and Tsu in 1969 [83], but only after the MBE and MOCVD (Metalorganic
Chemical Vapor Deposition) techniques were developed and heterostructures, quantum wells
and superlattices became practical, this idea became true. Then R. Dingle, H. Störmer et al.
[84] introduced the concept of modulation-doped (MOD) heterostructure demonstrating the
enhanced mobility in the AlxGa1-xAs-GaAs modulation doped superlattice. Just one year later,
this effect was applied to field-effect transistors by Mimura et al. [85, 86].
The MOD-heterostructure principle consists in growing the following sequence of
layers: a very pure undoped GaAs layer, followed by a thin layer of undoped AlxGa1-xAs and
then a layer of moderately n-doped AlxGa1-xAs. In practice a thin capping layer of GaAs
completes the structure to prevent oxidation or other degradation of the AlxGa1-xAs. If the
GaAs and AlxGa1-xAs layers were disconnected, the Fermi energy level in the wide-band gap
AlxGa1-xAs material would be higher than that in GaAs layer. When the layers are contacted,
the electrons from n-doped AlxGa1-xAs liberated from donors due to temperature (or light) are
free to move and cross the heterojunction into GaAs layer. From there they cannot return due
to the high potential barrier, hence the electrons
are trapped in the GaAs layer and they are free to
move only in parallel directions to heterojunction.
A thin two-dimensional conducting layer, usually
called two-dimensional electron gas (2DEG), is
formed at the interface between GaAs and
AlxGa1-xAs (Figure 3.8). This 2DEG is spatially
separated from the n-doped AlxGa1-xAs by the
thin layer of undoped AlxGa1-xAs. The
consequence is that the carriers from 2DEG have
a very high mobility, because the number of
impurity scatterings is strongly reduced. At very
low temperatures, and in very pure materials, it
was found that the mobility of electrons at Figure 3.8: Energy band diagram of a
modulation (selectively) doped AlxGa1-xAs/
heterojunctions can exceed the values obtained
GaAs heterostructure. An undoped buffer layer,
for low-doped bulk material by a factor in excess typically 1 μm thick, is followed by an
of 1000 [87]. At room temperature, in the AlxGa1-xAs which has an undoped part at the
application of MOD heterojunctions to FETs, the interface in order to reduce the Coulomb
mobility of the electrons in pure GaAs is typically scatterings.
43
Chapter 3: Field-effect transistors – theoretical aspects
twice that of doped GaAs used in metal-gate FETs this having two implications for the
performance of high-speed transistors:
(i) The resistances are reduced, so that also the RC time constant is reduced and the
devices of a given size are faster;
(ii) The noise usually generated from scattering processes is much reduced.
3.5
MODFET
The modulation-doped field effect transistor (MODFET) is similar to MESFET except
that under the gate there is a heterojunction, which provides a conductive channel, which is, in
fact, a two-dimensional electron gas, so that electrons with high mobility and high average
drift velocity can be transported between source and drain. Because electron mobility
exceeding 107 cm2/Vs, at low temperatures, were reported by Pfeiffer et al. [88] and Foxon et
al. [89] for MOD structures, this device was also named high-electron-mobility transistor
(HEMT), two-dimensional electron gas field-effect transistor (TEGFET) or selectively doped
heterojunction transistor (SDTH). The MODFET has an enhanced high-frequency
performance (GaInAs MODFET has for example a cut-off frequency of 600 GHz at a gate
length of 50 nm). An actual review about MODFETs can be found in Ref. [90].
Figure 3.9: The perspective view of a MODFET (a); The energy band diagram for equilibrium (b1) and above
threshold voltage (b2).
Comparing Figure 3.9 (b2) with Figure 3.1 (d) one can see the similarities between
MOSFET and MODFET. If for the MOSFET applying a bias on the gate leads to the
formation of an inversion layer, in the case of the MODFET it leads to the formation of a
2DEG, carriers having an increased mobility due to the MOD-heterostructure. As for
MOSFETs two technologically interesting solutions can be achieved: normally-on and
44
Chapter 3: Field-effect transistors – theoretical aspects
Figure 3.10: The band diagram for normally-on and normally-off MODFETs.
normally-off GaAs channels (Figure 3.10). The latter situation can occur because the large
Schottky voltage (~ 1 eV) can completely deplete the AlxGa1-xAs layer and the GaAs channel
for thin enough AlxGa1-xAs layers. [91].
3.6
Other MODFET related devices
Inverted heterojunction field-effect transistor (inverted HFET)
The structure is presented in Figure 3.11 and one
can see that the AlxGa1-xAs layer and the undoped GaAs
are inverted, i.e. first is grown an n-doped AlxGa1-xAs
layer, then an undoped AlxGa1-xAs to separate the 2DEG
from the doped layer, and finally the undoped GaAs
layer is grown right under the gate. This structure
provides a more stable surface on which to form the
Schottky barrier and a better electrical isolation of the
Figure 3.11: Inverted HFET.
2DEG from the substrate. The drawback is a lower
mobility of 2DEG first attributed to the interfacial roughness or some background impurities
built up at the interface but no clear evidence has been obtained. Sasa et al. [92] have shown
that another important factor would be the diffused profile of doped Si impurities. A lot of
work to improve the mobility was performed [93] and the typical values obtained for mobility
of 2DEG in inverted heterostructure is about 5·105 cm2/(Vs) at 4.2 K (compared to values of
5·106 cm2/(Vs) obtained for normal structures).
·
Planar-doped heterojunction field-effect transistor (δ-doped HFET)
According to the rigorous definition [94] a one
dimensional doping profile in a semiconductor can be
considered to be a d-function if the thickness of the
doped layer is smaller than the electron de Broglie wave
length. The doping in the AlxGa1-xAs of the planar-doped
(d-doped, pulse-doped) layer is made practically in one
monolayer [95], so that either MBE or MOCVD
techniques can be implied in the fabrication of these
·
Figure 3.12: d-doped HFET.
45
Chapter 3: Field-effect transistors – theoretical aspects
devices. The d-doped FET (Figure 3.12) was realized for the first time by E. F. Schubert and
K. Ploog [96] and its advantages are:
(i) a high carrier density and high transconductance;
(ii) the proximity between electron channel and gate electrode;
(iii) a large breakdown voltage of the gate;
(iv) reduced short-channel effects;
(v) a lower threshold voltage.
Single-quantum-well heterojunction field-effect transistor (SHFET)
The single-quantum well HFET or doubleheterojunction FET (DHFET) is presented in Figure 3.13
and one can see that a narrow-band undoped GaAs layer
is grown between two wide-band AlxGa1-xAs layers,
which are undoped in the immediate vicinity of the
GaAs layer and n-doped in rest. In this way two parallel
2DEGs are formed at the heterojunctions between the
undoped GaAs layer and undoped AlxGa1-xAs layers.
Figure 3.13: DHFET
The advantage of this structure is evident, because the
maximum charge sheet and the current are doubled.
·
Superlattice heterojunction field-effect transistor (superlattice HFET)
If the thickness of the wide-band-gap
barriers layers is small enough the electrons
may tunnel through, and the situation
becomes similar to the one when individual
atoms are brought together in a crystal. In
this case, individual levels in the quantum
wells are split into bands (called minibands).
In a crystal, the periodic atomic potential
Figure 3.14: Superlattice HFET.
leads to band formation. In a superlattice, an
artificial, human-made periodical potential causes the formation of minibands. Superlattice
structures have been used in field effect transistors where several quantum wells provide one
or even more parallel conducting channels, in the latter case the net result being an increased
device current and, hence, output power.
In Figure 3.14 within the superlattice, the narrow-energy-gap layers are doped while
the wider-energy-gap layers are undoped. According to the results obtained by Arch et al.
[97] the advantages of this structure are:
(i) It eliminates traps related to the dopants in the AlxGa1-xAs layer.
(ii) By optimizing the position and the doping level of the quantum wells in the
superlattice, the desired dependence of the transconductance on the gate voltage may
be obtained.
·
46
Chapter 3: Field-effect transistors – theoretical aspects
(iii) Smaller variation of the threshold voltage with the temperature due to the elimination
of traps in the AlxGa1-xAs layer is achieved. Arch et al. reported a variation of the
threshold voltage of only 140 mV in the temperature range 77–300 K (in comparison
with 200–300 mV for a conventional MODFET).
Heterojunction insulated-gate field-effect transistor (HIGFET)
The most simple heterojunction insulated-gate
field effect transistor (HIGFET) is a MODFET, which
has both wide- and narrow-band energy materials
undoped (Figure 3.15). This structure allows an easy
fabrication of n-and p-channel devices on the same chip.
Because the materials are undoped the 2DEG is induced
only if a gate bias higher than the threshold voltage is
applied. Also the Hall measurements are impossible
Figure 3.15: HIGFET
since the channel is generated only in the presence of an
applied gate bias. In spite of these drawbacks, the advantage of a better threshold voltage
control [98] for complementary circuits in which n-channel and p-channel devices are
fabricated simultaneously is very important.
·
Doped-channel heterojunction field-effect transistor (DCFET)
The doped-channel FET (DCFET) is similar to a
HIGFET with the only difference that the narrowenergy-gap semiconductor is doped (Figure 3.16). The
structure loses the mobility enhancement due to
modulation doping and the operation is similar to a
MOSFET [98]. Relatively recent, other materials like
Si/SiGe were used for the DCFET fabrication with
uniform and d-doped SiGe p-type conducting channel
Figure 3.16: DCFET
[99]. Chen et al. [100] fabricated a DCFET using
In0.52Al0.48As/In0.53Ga0.47As with a high-transconductance, high-gate-drain breakdown voltage
and with a good temperature characteristic.
·
Semiconductor-insulator-semiconductor field-effect transistor (SISFET)
Conceived independently by Rosenberg [101]
and Solomon et al. [102], the SISFET is similar to a
HIGFET except that the gate material contacting the
wide-energy-gap material is another semiconductor that
is usually the same as the channel layer, and is heavily
doped (Figure 3.17).
The fact that the critical AlxGa1-xAs layer is
buried under the GaAs gate endows the structure with
Figure 3.17: SISFET
excellent thermal stability under high-temperature
·
47
Chapter 3: Field-effect transistors – theoretical aspects
processing.
Because the entire structure of a SISFET is a single crystal this device introduces a
new degree of freedom into the art of FET design, because the parameters of all layers may be
changed at will. One such concept is the saturable-charge FET (SATFET) [103], in which the
n-type gate is nonuniformly doped in a heavy-light-heavy configuration. When the 2DEG
concentration in the channel increases the heavily doped layer nearest the channel is depleted.
Beyond a critical 2DEG concentration (i.e. gate voltage), the depletion layer spreads into the
lightly doped layer. The charge in the 2DEG saturates, and with it the gate leakage current;
the gate capacitance decreases. Even if there is not possible to increase the maximum current,
it allows the gate voltage to swing over a wide voltage range without affecting the
low-voltage performance of the FET.
Pseudomorphic heterojunction field-effect transistor (pseudomorphic HFET)
The channel in pseudomorphic HFETs
(Figure 3.18) is a narrow-energy-gap material as
InGaAs. The channel yields even higher mobility, higher
saturation velocity and higher sheet-carrier densities
than GaAs. Another important advantage of using
InGaAs is that the noise performance of the devices is
much improved.
Also by realizing a d-doped pseudomorphic
Figure 3.18: Pseudomorphic HFET
HFET, higher breakdown voltages and large gate
voltage swings may be obtained [104].
·
48
– Chapter 4 –
In-plane gate transistors fabricated by focused ion
beam implantation in negative pattern definition
4.1
Depletion region of a 2D p-n junction
It is well known that the modulation-doped heterostructures allow the realization of
high-quality two dimensional systems and, using focused ion beam implantation technique,
one can fabricate two-dimensional p-n junctions in these heterostructures [105-107] when a
two-dimensional electron gas (2DEG) and a two-dimensional hole gas (2DHG) form an
in-plane junction (Figure 4.1). Interesting physical properties have been predicted for 2D p-n
junctions [5]:
(i) a linear dependence of the depletion region dimension on the applied voltage. This
result suggests that the IPG channels can be linearly tuned in width with the gate
voltage;
(ii) the electric field is almost independent on the applied voltage, so that the breakdown
voltages are not reached as easily as in sandwich diodes (where the electric field
depends on V );
(iii) the in-plane capacitance depends only on the length of the in-plane capacitor and has
very small values (according to Wiemann et al. [5] about 0.5 fF/µm for GaAs)
making the devices based on 2D p-n junction to be very promising for applications
like fast light-emitting diodes, etc.
The theory of 2D p-n junctions has been
developed in Ref. [5, 108, 109] and recently Reuter et
al. [110] have proved experimentally, that the width
of the total-depletion layer in a 2D p-n abrupt
junction is given by
e e (V - V )
L = 2l = 2 0 r bi2 D
,
(4.1)
eN
while for a linearly-graded 2D p-n junction the
Figure 4.1: Schematic representation of a 2D
dependence is similar to the 3D case [109]
p-n junction
49
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
4e 0e r (Vbi - V )
,
(4.2)
p eK
where K is the grading constant (given by linearly-graded junction defined by the equation
L = 2l = 2
N D2 D - N A2 D = Kx ).
Significant contributions to the calculation of intrinsic and extrinsic capacitances of
IPG transistors are attributed to de Vries et al. [2, 3] and Petrosyan et al. [108, 109]. A short
summary and a straightforward comparison between the depletion regions and capacitances of
3D and 2D p-n junctions is given in Table 4.1.
Table 4.1: Comparison between 3D and 2D p-n junctions
Junction type
Depletion width
Abrupt(*)
2e 0e r (Vbi ± V )
L=
eN 3 D
Linearly-graded
é12e e (V ± V ) ù
L = ê 0 r bi
ú
eK
ë
û
3D
(†)
ee 0e r N 3 D
-1/ 2
C=
(Vbi ± V )
2
1/ 3
1/ 3
Abrupt
(‡)
L = 2l = 2
2D
Linearly-graded
4.2
Capacitance
L = 2l = 2
e 0e r (Vbi ± V )
eN 2 D
4e 0e r (Vbi ± V )
p eK
é eK e 02e r2 ù
C=ê
ú
ë12 (Vbi ± V ) û
C p2-Dn
1
= A + a ln
e 0e r
Vbi ± V
w
p
where A is a constant and
for abrupt junct.
ì1
a =í
î1/ 2 for lin. - grad . junct.
Realization, basic device characteristics
As discussed in Chapter 3, conventional field-effect transistors have a sandwich
structure with the gate placed on top of the channel between source and drain. The main
distinct characteristic of in-plane gate transistors is that the gate-induced electric field is
parallel to 2DEG, the gate being separated from the narrow conducting channel by an
implantation barrier. One can say that gate, source and drain are in the same plane, fact that
justifies the “in-plane gate” denomination. Introduced by Wieck and Ploog [1, 111] the IPG
transistor is a promising device due to the fact that using FIB implantation, its fabrication is
inherently self-aligned, and consequently consists of an easy single maskless step process.
(*)
(†)
(‡)
The calculation for the abrupt 3D junction is performed considering an abrupt one-sided junction (Ref.
[10]).
The signs + and - are for the reverse and forward bias, respectively.
In contrast with 3D case, equation (4.1) was calculated considering N A2 D = N D2 D , so that the depletion
region symmetrically extends in both p- and n-type materials (Ref. [108]).
50
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
The IPG transistor fabrication is based on a standard MODFET structure, with a high mobility
2DEG, and the FIB implantation lines define the source, the drain, the gate and the channel.
Figure 4.2: Energy band diagrams for the significant sequence of layers in the heterostructures a) 1091
and b) 1068. For the complete sequence of layers please see Paragraph 2.1.
Practically speaking, there are a few different possible ways to deal with IPG
transistors fabrication. One can start from a certain heterostructure and adjust the implantation
parameters, so that the implanted ions reach the 2DEG and the insulation lines are obtained; a
second way would be to design the heterostructure knowing the implantation parameters, or
finally, the third and maybe the most realistic procedure consists in a mixture of these two
methods. One good starting point for the IPG fabrication is to set the main implantation
parameters like acceleration voltage and ion species, which should be implanted. In our case,
Ga+ ions are implanted having a kinetic energy of 100 keV.
Figure 4.3: SRIM simulation of ions penetration into the matter for the heterostructures a) 1091 and b) 1068.
The acceleration energy of the incident Ga+ ions is 100 keV, the total number of ions in the simulation is 10 6.
Then, using the SRIM simulation software, a three dimensional Monte–Carlo
simulation of the ions penetration into the matter [32] one can design the heterostructure.
Finally, fine settings of the implantation parameters like the dwell time or step size can
improve the insulating character of the implanted lines as needed. The band diagrams for the
51
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
heterostructures 1091 and 1068 are presented in Figure 4.2 and the ion ranges obtained by
SRIM software in Figure 4.3. A sketch of a typical IPG transistor is presented in Figure 4.4.
Figure 4.4: FIB implanted heterostructure (left) and a zoomed area (right) in which two IPG transistors defined
by insulating lines implanted with FIB are presented.
The sheet carrier concentration and mobility of 2DEG obtained by Hall measurements
at both room temperature (RT) and 4.2 K are presented in Table 4.2.
Table 4.2: Sheet carrier concentration and mobility of 2DEG at RT and 4.2 K
Wafer
1068
1091
n[1011 cm-2]
RT
9.16
3.50
mn[cm2/(Vs)]
4.2 K
8.86
2.35
RT
5517
7159
4.2 K
31985
401313
The fabricated IPG transistors showed good FET characteristics. The characteristics
have been measured with a HP 4156A precision semiconductor parameter analyzer at RT.
The I-V characteristics are similar to that of a JFET.
Figure 4.5 and Figure 4.6 present the I-V characteristics and the leakage currents for
an IPG transistor with a geometrical width of the channel Wgeo= 1.0 μm fabricated on the
heterostructure 1091 and 1068, respectively.
One can notice that:
· the channels can be controlled by the gate bias;
· for the transistor fabricated on the heterostructure 1091 the gate bias for which the
channel is completely closed is 3.0 V, while for the IPG fabricated on the wafer 1068 the
corresponding gate bias is 1.5 V;
52
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
·
the values for the saturation currents are larger for the IPG fabricated on the
pseudomorphic heterostructure (1068) with a factor of approximate two, being equal to
(
the ratio n1068 m 1068
·
) (n
1091
m 1091 ) ;
the leakage currents in the pseudomorphic heterostructure are about two orders of
magnitude lower than for a normal HEMT structure;
Figure 4.5: The I-V characteristics (left) and the leakage currents (right) for an IPG transistor with a geometrical
channel width Wgeo= 1.0 μm realized on the wafer 1091.
Figure 4.6: The I-V characteristics (left) and the leakage currents (right) for an IPG transistor with a geometrical
channel width Wgeo= 1.0 μm realized on the wafer 1068.
4.3
Theoretical aspects – simple models
In the following calculations it will be considered that the FIB technique used to
fabricate the IPG transistors produces 2D abrupt junctions between the 2DEG of the wafer
and the 2DHG realized by Ga+ implanted ions. The main goal is to know the current through
the channel, so that the main problem reduces to model the channel geometry, i.e. the
effective width Weff and the length L. The source is grounded, all voltages being then
considered with respect to the source electrode.
53
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
A model for depletion regions
For a p-n abrupt 2D-junction, the width of the depletion region is given by equation
(4.1), which in our case becomes
2e e (V + V ( x) - VG )
h( x) = 0 r bi
.
(4.3)
eN D
Here h is the width of the depletion region, Vbi is the built-in potential of the abrupt p-n
2D-junction, e is the electron charge, V(x) is the voltage in the channel at point x, VG is the
gate bias and ND the donor carrier concentration equal to the acceptor carrier concentration in
2D gases (in Ref. [108] the calculation were performed considering both 2D gases, which
define the junction, to have the same carrier concentration ND=NA). The channel is defined by
two depletion regions, one appearing along the line between source and drain, the other along
the line between gate and source/drain, both being linear functions of the applied voltage
across the respective insulating line.
A rigorous expression for the effective width of the channel Weff is [112]
Weff ( x ) = Wgeo - 2 ( rbeam + rstrag ) - hG - D ( x;VG , VD ) - hS - D ( x;VD ) ,
(4.4)
where Wgeo is the geometrical width of the channel, 2ּrbeam is the beam diameter, and rstrag is
the lateral straggling.
Figure 4.7: (a) Schematic draw of the extension of depletion regions for an IPG transistor. The black dotted
lines represent the mathematical (i.e. with no dimension) lines along which the beam moved during the
implantation; the pink regions are the implanted regions with the width given by the beam diameter, the small
blue regions represent the lateral straggling of the ion beam, the yellow areas represent the depletion regions. (b)
a model for the depletion regions: the width of the implanted lines is neglected in comparison with the depletion
region width (i.e. the FIB lines are considered to have no width in the model), the straggling is also neglected,
the depletion region along the line between source and drain is considered to be a rectangle with the length equal
to the length of the implanted line. The width of the rectangle is given then by equation (4.1).
A simple estimation of the depletion region for gallium arsenide (εr=13.1) with
ND=10 cm-2 gives a size of hundreds of nanometers to few micrometers (for Vbi ~ 1V).
11
54
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
Because the beam diameter is about 100 nm, one can neglect the second term on the right of
equation (4.4) and, since the depletion region is a linear function of the applied voltage, one
may consider in a simple model that the depletion region along the line between source and
drain is rectangular, with the length being equal to the geometrical length of the FIB
implanted line. It means, in fact, that because the beam size is very small, the depletion region
extends only in the drain region parallel to the other implanted line (Figure 4.7).
Along the line between the gate and source/drain electrodes, the corresponding
depletion widths at the source and the gate are:
2e e (V - V )
h(0) º h1 = 0 r bi G ,
(4.5)
eN D
h( L) º h2 =
2e 0e r (Vbi + VD - VG )
,
eN D
(4.6)
where the channel length depends on the drain voltage L = L(VD) and is equal to the width of
the rectangular depletion region given by
2e e (V + VD )
.
(4.7)
L (VD ) = 0 r bi
eN D
When the depletion region extends in the entire channel at the drain electrode,
Weff ( L) = 0 , the corresponding voltage is called pinch-off voltage. In other words, the
pinch-off voltage is the gate-drain voltage necessary to increase the depletion width at the
drain from zero to the geometrical width of the channel [40, 113]
eN W
VP = (V ( x) - VG + Vbi ) W ( L )=0, V =V = D geo .
(4.8)
G
bi
0
2e 0e r
The I-V characteristics
The 2D-current density in the x direction is: J x2 D = s 2 D ( x)E x
(i)
(ii)
(iii)
One can obtain the current-voltage characteristics making following assumptions:
FIB produces an abrupt junction,
using FIB machine, 2D uniformly doped n- and p-regions with approximately equal
carrier concentrations ND are obtained;
the depletion region varies gradually along the channel (gradual channel
approximation).
The constant mobility model
At relatively low values of the electric field it is reasonable to assume that the mobility
of the carriers is constant, i.e. independent of the applied drain-source voltage. Together with
the other three assumptions considered above, this leads to a drain-source current having the
following expression
55
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
æ dV ö
I D = J x2 DW ( x) = eN D m 2 D ç
÷ éëWgeo - h ( x ) ùû .
è dx ø
From equation (4.1) one can obtain the differentiation of the drain voltage
eN D
dV =
dh .
2e 0e r
(4.9)
By substituting this expression in (4.9) one obtains
I D dx = N D m 2 D (Wgeo - h ) dV =
e 2 N D2 m 2 D
(Wgeo - h ) dh
2e 0e r
and by integrating along the channel:
e 2 N D2 m 2 D
I D ò dx =
2e 0e r
0
L
h2
ò (W
geo
- h ) dh ,
(4.10)
h1
where h1 and h2 are the depletion widths at the source and the drain ends, respectively, and are
given by equations (4.5) and (4.6). This yields
e 2 N d2 m 2 D
ID =
2e 0e r L
1 2
é
2 ù
êëWgeo ( h2 - h1 ) - 2 ( h2 - h1 ) úû .
(4.11)
Considering the normalized depletion widths:
h( x) V ( x) + Vbi - VG
u ( x) =
=
,
Wgeo
VP
(4.12)
u1 =
V -V
h1
= bi G ,
Wgeo
VP
(4.13)
u2 =
V +V -V
h2
= D bi G ,
Wgeo
VP
(4.14)
the current can be written as
ID =
2
e 2 N D2 m 2 DWgeo
4e 0e r L
é 2 ( u2 - u1 ) - ( u22 - u12 ) ù .
ë
û
(4.15)
A simplified form would be
I D = I P ( u2 - u1 )( 2 - u2 - u1 ) ,
where I P =
2
e 2 N D2 m 2 DWgeo
4e 0e r L
=
2
e3 N D3 m 2 DWgeo
8e 02e r2 (Vbi + VD )
(4.16)
.
(4.17)
One of the characteristics of the IPG transistors is that the channel length L depends on
the drain voltage according to equation (4.7). In order to study the dependence I D = f (VD )
one can write equation (4.16) as
ID =
2
e 2 N D2 m 2 DWgeo
4e 0e r L
2
e 2 N D2 m 2 DWgeo
VD
( u2 - u1 )( 2 - u2 - u1 ) =
2e 0e r L
VP
æ Vbi - VG VD
ç1 VP
2VP
è
ö
÷ , (4.18)
ø
and considering (4.7) and (4.8), finally, one obtains:
ID =
e 2 N D2 m 2 DWgeo
2e 0e r
VD
Vbi + VD
æ Vbi - VG VD
ç1 V
2VP
P
è
56
ö
÷.
ø
(4.19)
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
For low drain-source applied voltages VD << VP and VD << Vbi, the drain current ID
simplifies to:
e 2 N D2 m 2 DWgeo æ Vbi - VG
ID =
ç1 2e 0e rVbi è
VP
ö
(4.20)
÷ VD
ø
The first result found experimentally is that: for low applied drain-source voltages the
current increases linearly with the applied voltage.
The saturation current is obtained for u2 = 1 in equation (4.16)
2
æ V -V ö
I = I P (1 - u1 ) = I P ç1 - bi G ÷ .
(4.21)
VP ø
è
This result can also be obtained if one considers the more general case of an arbitrary
charge distribution and, in the general formula(*) obtained for the saturation current, one
replaces the charge distribution with a delta function at depth y= a.
2
sat
D
Equation (4.21) can be written as a function of VDsat :
I
sat
D
I
= P2 VDsat
VP
(
)
2
(
sat
)
2
eN m 2 D VD
= D
2
Vbi + VDsat
where VDsat = VP + VG - Vbi =
eN DWgeo
2e 0e r
(4.22)
+ VG - Vbi ;
(4.23)
or as a function dependent on the gate bias:
2
2
e3 N D3 m 2 DWgeo
æ Vbi - VG ö
I = 2 2
ç1 ÷ .
VP ø
8e 0 e r (VP + VG ) è
For higher VD voltages the current in
this model is supposed to remain constant at
sat
D
(4.24)
the value I Dsat . Equation (4.22) could explain
the experimental results from Figure 4.5 and
Figure 4.6 where the ratio between the
saturation currents for the IPG transistors
obtained on 1068 and 1091 is approximately
equal
to
(N
1068
D
m 1068 )
(N
1091
D
m 1091 ) .
Of
course, due to the fact that the transistors
have different built-in and pinch-off
voltages, this relation can be considered only
as a rough estimation.
A graphical representation of
equation (4.19) is given in Figure 4.8. The
maximum of the current occurs for values
VDmax < VDsat ,
(*)
this
maximum
appearing
Figure 4.8: The I-V characteristics for an IPG transistor
calculated in the constant mobility approximation. The
dotted black curves represent the calculated
characteristics using equation (4.19). The blue curves
represent the model, for which the current remains
constant after reaching its maximum value.
S. M. Sze, “Physics of Semiconductor Devices”, John Wiley & Sons, Inc., New York, 1981, page 322, table
1 and equation (32).
57
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
because both the length and the width of the channel are varying in this model. Still the
measurements showed that these maxima never appear, demonstrating that the channel
defined by the depletion regions is probably changing in such a manner that for values of VD
higher than VDmax the hypothesis that the depletion region is a perfect rectangle is not any more
valid. Another reason could be the field dependent mobility. Finally, regions of electron
accumulation and depletion may form in the channel, as it will be discussed at the end of this
chapter, which could be the main cause of vanishing of these maxima.
The evolution of the depletion region as a function of the drain voltage and the gate
bias, and the corresponding I-V characteristics are presented in Figure 4.9.
The maximum value for the saturation current is obtained from equation (4.19)
æ
ö
V -V +V
¶I D
= 0 Þ VDmax = Vbi ç 1 + 2 P bi G - 1÷ ,
ç
÷
¶VD
Vbi
è
ø
and considering (4.23)
max
D
V
(4.25)
æ
ö
VDsat
VDsat ö
sat æ
= Vbi ç 1 + 2
- 1÷ ; VD ç1 ÷.
ç
÷
Vbi
è 2Vbi ø
è
ø
(4.26)
From this equation one can see that VDmax < VDsat as it was already mentioned.
The maximum source-drain current is
2
ö
VP - Vbi + VG
eN D m 2 D æ
I =
- 1÷÷ Vbi .
(4.27)
çç 1 + 2
Vbi
2
è
ø
A metamorphose of the presented model can be obtained if one considers that the
max
D
current after reaching the maximum value I Dmax for the source-drain voltage value of VDmax the
depletion regions shape change in such a manner so that the current should remain practically
constant. This corresponds to the blue curves in Figure 4.8. In this case, the saturation value
of the current is replaced by the maximum value.
Figure 4.9: Depletion region and source-drain current for (a) small values of the drain voltage (linear region);
sat
(b) at the pinch-off point; (c) for drain voltages higher than VD , (the current remains at the same value
obtained at the pinch-off of the channel, but the depletion regions extend more in the drain region); (d) for small
drain voltages when the gate bias is increased in absolute value; (e) when the channel is completely closed.
58
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
The transconductance g m is defined as
2
2 2D
¶I D e N D m Wgeo VD
and considering (4.8)
gm =
=
2e 0e rVP Vbi + VD
¶VG
g m = eN D m 2D
gm V
D = ct
gm ;
VD
,
Vbi + VD
(4.28)
= ct and for VD = Vbi (very close to zero drain voltage)
eN D m 2D
VD .
Vbi
(4.29)
The transconductance in the saturation regime can be calculated starting from (4.24):
g
sat
m
2
¶I Dsat eN D m 2 D é æ Vbi ö ù
ê1 - ç
=
=
÷ ú.
¶VG
2
êë è VP + VG ø úû
(4.30)
This equation can also be written as function of VDsat
2
ö ù
eN D m 2 D é æ Vbi
VDsat æ 1 VDsat ö
2D
ê1 - ç sat
ú
=
g =
eN
m
(4.31)
÷
ç1 ÷
D
2
Vbi + VDsat è 2 Vbi + VDsat ø
êë è VD + Vbi ø úû
The main result is if for very small drain voltages, when (4.29) is valid, the
transconductance values are dependent on the drain voltage, increasing the drain voltage the
transconductance, being now given by (4.30), becomes independent of the drain voltage.
From the expression of the saturation
current (4.24) another interesting result can be
sat
m
obtained: when I Dsat = 0 , which is equivalent with
VP - Vbi + VG = 0 , the saturation transconductance,
g msat becomes also zero.
In conclusion, when the channel is
completely closed the transconductance measured
for any drain voltage is zero.
The equation I Dsat = 0 implies that
Figure 4.10: Numerical simulation for trans-
VGcl .channel º VT = Vbi - VP .
(4.32) conductance at maximum of the current (blue
That means the threshold voltage, VT (the voltage curves) and at saturation given by the pinch-off
condition
(red
curves).
The
simulation
for which the channel is completely closed) is the
parameters correspond to heterostructure 1068.
bias which applied on the gate extends the The large values of transconductances are due to
depletion region at the source electrode over the the fact that the mobility field dependence was
entire channel (u1=1). One can say that when the not considered. The shift of the threshold voltage
depletion region between source and gate extends with the built-in potential is indicated by black
arrows.
so much in the channel, so that the channel is fully
“flooded”, then the saturation current and the transconductance are zero. Knowing the gate
bias for which the channel is closed one can determine the built-in potential.
59
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
It is interesting to note that the transconductance that corresponds to the current
maximum is higher than the transconductance that corresponds to the saturation given by the
pinch-off condition (4.23).
The transconductance corresponding to the current maximum is
é
ù
¶I Dmax
1
ú.
= eN D m 2 D ê1 (4.33)
¶VG
êë
1 + 2 (VP - Vbi + VG ) Vbi úû
A graphical comparison between the transconductance obtained at saturation (given by
pinch-off condition) and the maximum of the current (given by (4.33)) can be seen in
Figure 4.10. One can notice that the threshold voltage is shifting to higher gate biases with the
increase of the built-in potential. At the same time the difference between transconductance
which corresponds to the maximum of the current and that corresponding to saturation is
decreasing. Because the built-in potential depends on the temperature, one can expect for
measurements performed at 4.2 K and RT a shift of the transconductance.
g mmax =
Field dependent mobility
As one might expect, the previous model cannot explain all experimental results due
to the limitations of its hypotheses. Especially for GaAs the carrier velocity saturates at about
vsat » 107 cm/s and it is this saturation velocity, which governs the I-V characteristics. In the
following section, a simple dependence of the drift velocity on the electric field will be
considered and the implications of this assumption will be analyzed. In this more general
model it will be considered that at low electric fields the mobility is approximately constant,
but at the same time, at high electric fields the drift velocity of the carriers reaches a
saturation value. This would correspond to the picture presented below (Figure 4.11).
The corresponding dependence of the
drift velocity is [40]
v=
m 2 DE x
,
1 + m 2 DE x v s
(4.34)
where vs is the saturation velocity.
In this case, equation (4.9) for the
source-drain current becomes
æ dV ö
m 2D ç
÷
è dx ø W - h .
I D = eN D
(
)
Figure 4.11: Approximations for the velocity-field
m 2 D æ dV ö geo
1+
ç
÷
curves.
v s è dx ø
After separating the variables, integrating and considering the normalized depletion widths
from the previous model one obtains
ID =
I P L éë 2 ( u2 - u1 ) - ( u22 - u12 ) ùû
eN D m 2 D
L +
( h2 - h1 )
2e 0e r v s
=
I P éë 2 ( u2 - u1 ) - ( u22 - u12 ) ùû
m 2 DVD
1+
vs L
60
,
(4.35)
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
where IP is defined by (4.17).
m 2 DVD
,
According to this model the current, in fact, is reduced by a factor of 1 +
vs L
where L is given by (4.7), so that
ID =
I P éë 2 ( u2 - u1 ) - ( u22 - u12 ) ùû
eN m 2 D VD
1+ D
2e 0e rv s Vbi + VD
.
(4.36)
The final result is:
e 2 N D2 m 2 DWgeo
VD æ Vbi - VG VD
ç1 2e 0e r
Vbi + VD è
VP
2VP
2D
eN m
VD
1+ D
2e 0e rv s Vbi + VD
ID =
ö
÷
ø.
(4.37)
The saturation current, given by the pinch-off condition ( u2 = 1 ) will be
2
2
e3 N D3 m 2 DWgeo
æ Vbi - VG ö
= 2 2
ç1 ÷
8e 0 e r (VP + VG ) è
VP ø
eN m 2 D
1+ D
2e 0e rv s
1
.
(4.38)
æ
Vbi ö
ç1 ÷
è VP + VG ø
If one calculates the ratio between the saturation current in the constant mobility
approximation and the saturation current obtained for a field dependent mobility, one gets:
I
sat
D
(I )
(I )
sat
D
sat
D
m
m 2 D = ct .
2D
= f (VD )
Vbi ö
eN D m 2 D æ
= 1+
ç1 ÷,
2e 0e rv s è VP + VG ø
( )
which shows for VG ³ 0 that I Dsat
m 2 D = ct .
( )
? I Dsat
(4.39)
m 2 D = f (VD )
. The measurements proved that the
values for the saturation current are much smaller than those obtained from calculations
considering the constant mobility approximation. In conclusion, (4.39) together with the
experimental data showed that the saturation of the current is due to field dependent mobility.
For VP - Vbi + VG = 0 , when the ratio becomes equal to unity, the channel is completely
pinched-off. It is important to mention that equation (4.39) gives the ratio between the
saturation currents, calculated in both approximations, at the pinch-off condition. The
saturation resulted from the field-dependent mobility effect and the saturation due to the
pinch-off are two distinct phenomena that occur at the same time.
The current given by (4.37) has a maximum value I Dmax for a drain voltage VDmax given
by dI D dVD = 0 . Solving this equation one obtains
VDmax =
(*)
Vbi
b
æ
ö V
VP - Vbi + VG
b - 1÷÷ = bi
çç 1 + 2
Vbi
è
ø b
æ
ö
VDsat
1
+
2
b - 1÷ (*),
ç
ç
÷
Vbi
è
ø
(4.40)
The saturation drain voltage VDsat corresponds to the value obtained considering the constant mobility
approximation in order to make a comparison between these values, as it was done in (4.25).
61
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
where b = 1 +
eN D m 2 D
.
2e 0e rv s
(4.41)
This is an equation similar to (4.25) “adjusted” with the factor β. In the case of constant
mobility v s ® ¥ , so that b = 1 and (4.25) is obtained. A relation between VDmax and VDsat
given by the constant mobility model can be found by the following approximation:
2
é
ù
sat
VDsat )
(
V
1
1
1 VDsat ö
2
sat æ
D
ê
ú
V
1+ 2
b - 4b
- 1 = VD ç1 b ÷ .(4.42)
ê 2 Vbi
ú
Vbi2
8
2 Vbi ø
è
ë
û
This equation shows that the maximum drain current is obtained for a drain voltage smaller
max
D
V
= bi
b
æ
ö V
VDsat
b - 1÷ ; bi
ç 1+ 2
ç
÷ b
Vbi
è
ø
than the value for which the pinch-off occurs(*), VDmax < VDsat .
Analogue to (4.27), the maximum current in this case becomes:
eN m 2 DVbi (a - 1)
= D
,
2
b2
2
I
max
D
where a = 1 + 2b
(4.43)
VP - Vbi + VG
. In the case of constant mobility v s ® ¥ , b = 1 and (4.27)
Vbi
is naturally obtained.
A simplified form of the current given by (4.37) is
ID =
Q (VD )
æ V -V
V ö
v s eN DWgeo ç1 - bi G - D ÷ ,
1 + Q (VD )
VP
2VP ø
è
eN D m 2 D VD
where Q (VD ) =
.
2e 0e rv s Vbi + VD
(4.45)
Q (VD ) éë1 + Q (VD ) ùû
dependent on the drain voltage is rapidly
saturating (Figure 4.12) and considering the
wafer 1068 (Table 4.2) for VD= 1.0 V and
Vbi=1.0 V its value is 0.9446. For
VD= 10 V the corresponding value becomes
0.9688, which means a relative increase of
only 2.5 %. If the pinch-off is not occurring
for drain voltages less than 1 V, namely
when the saturation drain voltage values
are higher than 1 V, one can write
The
(4.44)
factor
æ V - V V sat
I Dsat ; 0.95v s eN DWgeo ç1 - bi G - D
VP
2VP
è
Figure 4.12: The function θ/(1+θ) is fast saturating.
ö
÷,
ø
where the saturation drain voltage VDsat is given by the pinch-off condition VDsat = VP + VG - Vbi .
Under these assumptions one obtains
(*)
The pinch-off occurs for u2=1 which is equivalent to (4.23).
62
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
Wgeo æ Vbi - VG ö
(4.46)
ç1 ÷.
2 è
VP ø
This approximation is especially good for the IPG transistors, which function in enhancementmode and, eventually, have large geometrical widths of the channel. When the saturation
drain voltages are smaller than 1 V, equation (4.37) must be used.
The transconductance in the linear region can be calculated from (4.44)
v s eN DWgeo Q (VD )
Q (VD )
gm =
= 2e 0e rv s
,
(4.47)
VP
1 + Q (VD )
1 + Q (VD )
I Dsat ; 0.95v s eN D
VD
Vbi + VD
which gives g m =
, and for VD = Vbi :
2D
eN D m
VD
1+
2e 0e rv s Vbi + VD
eN D m 2 D
g m ; eN D m 2D
VD
,
Vbi
(4.48)
this being the same as (4.29) for the constant mobility model. This means that for small drain
voltages, when the approximation VD = Vbi is valid, the transconductance is independent of
the model, which one should maybe expect, since the carrier drift velocity does not saturate.
In order to calculate the transconductance in the saturation regime, one should
consider the expression for the saturation drain current, (4.38):
g msat =
ù
öé
Vbi
ú,
÷ ê1 +
ø ëê g (VP + VG ) ûú
eN D m 2 D
2g
æ
Vbi
ç1 è VP + VG
eN D m 2 D
2e 0e rv s
æ
Vbi ö
ç1 ÷
è VP + VG ø
where g = 1 +
(4.49)
(4.50)
For the case when v s ® ¥ the result (4.30) from the constant mobility model is
obtained. Although (4.49) is valid for the saturation, it is interesting to note that, theoretically
speaking, for very small drain voltages, when VD ® 0 equation (4.29) is obtained. But one
should consider that (4.49) is only valid for the saturation regime and should not expect to
find the same values experimentally.
Another thing that should be pointed out is that the transconductance in the saturation
regime cannot be obtained directly from equation (4.47) simply considering the factor
(
Q VDsat
(
)
1+ Q V
sat
D
)
= 1 . This would be valid only for transistors, for which VDsat values are higher
than 1 V, e.g., IPG transistors, which function in the enhancement-mode. For normal
transistors the VDsat values are usually as high as 1 V or smaller. The saturation current is
supposed to remain constant at VDsat , meaning in fact that the current saturates before the
(
factor Q VDsat
)
(
)
é1 + Q VDsat ù . It also means that in the saturation drain voltage range, the
ë
û
(
instantaneous rate of change of the factor Q VDsat
63
)
(
)
é1 + Q VDsat ù (which depends on VG as
ë
û
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
VDsat does) cannot be neglected. Otherwise, one obtains a linear function of the gate bias, and
hence, a constant value for the transconductance, fact that is not experimentally verified.
The transconductance corresponding to the maximum current can be calculated from
(4.43):
g mmax =
eN D m 2 D
b
æ 1ö
ç1 - ÷ .
è aø
(4.51)
Saturated velocity model
In the case of short channels, due to the high-field velocity saturation, one of the
simplest models expected to be valid is the saturated velocity model. In fact, the saturated
velocity model can be considered as a particular case of the previous one, and it will be
briefly discussed in the following paragraphs. This model, in spite of its simplicity, gives very
good results, because high electric fields are easily obtained even for small drain voltages, due
to the small length of the channel that forms between depletion regions. Consequently, the
saturation drift velocity of the carrier is immediately reached, and it is not surprising that it is
this model, which was very often considered for the IPG transistors [114, 115]. For uniformly
doped materials, when the carriers move with a saturated drift velocity, the source-drain
current is given by
I D = eN Dv s (Wgeo - h ) = eN Dv sWeff .
(4.52)
This model was usually used to evaluate the effective width Weff of the channel for the
saturation current. In the limit of constant sheet carrier density, which is a good
approximation for devices, where the in-plane gate influences mainly the width, and almost
not at all the carrier density of the channel, as the magneto-transport measurements [116]
showed, one can write
Weff [ m m ] =
I Dsat [ m A]
160 ´ N D éë1012 cm -2 ùû
.
(4.53)
This model assumes that the velocity and the number of carriers are both constant and
field-independent throughout the channel and considering that the channel is rapidly
narrowing (very short) then
æ
2e e (V - V ) ö
æ V -V ö
I D = eN Dv s ç Wgeo - 0 r bi G ÷ = eN Dv sWgeo ç1 - bi G ÷ .
eN D
VP ø
è
è
ø
¶I
It results that the transconductance is g m = D = 2e 0e rv s ; 23 μS for GaAs.
¶VG
This value is in good agreement with the transconductance value (17 μS) obtained by
Nieder et al. [117]. However, the model allows one to obtain higher transconductance values
for devices with more than one channel in parallel, or if the saturation velocity is increased.
Very high transconductance values were obtained by Wieck [114] using a device with two
channels; in the same reference the “velocity overshoot” was experimentally proved.
64
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
Negative drain voltages
So far, all the models considered the positive range for the drain voltage, this situation
being very well illustrated in Figure 4.9. The measurements showed that these I-V
characteristics are not symmetric for negative drain voltages. In the following this negative
range of the drain voltage will be considered and analyzed.
When the drain voltage becomes negative, the channel that is defined by the depletion
region along the implanted line between source and drain, will move in the source region and
its length will be given (as previous) by the width of this depletion region. At the same time,
the other depletion region, that is along the FIB implanted line between gate and drain, will
decrease in width. Considering that the depletion region extending in the source region is a
perfect rectangle, there are three distinct situations, which should be separately discussed
(Figure 4.13):
(i)
For small gate biases, Vbi - VP < VG < 0 , the pinch-off of the channel does not occur for
any drain voltage. The drain voltage increases the length of the channel but its
effective width is fixed at the source electrode since Vbi - VG is fixed.
(ii)
For a gate bias VG = Vbi - VP the pinch-off occurs at the source.
(iii)
For larger gate biases and zero drain voltage the channel is closed. Decreasing the
drain voltage, the depletion region from the drain is decreasing until its width is the
same as the geometrical channel width, then the channel starts to open. Decreasing
further the drain voltage the channel continues to open up until the depletion region
from the drain is completely expulsed into the gate region.
For small gate biases equation (4.10) becomes
e 2 N D2 m 2 D
I D ò dx =
2e 0e r
-L
0
h2-
ò (W
geo
h1-
- h - ) dh - ,
(4.54)
are the depletion regions in the channel for negative drain voltage at the source and
where h1,2
drain electrodes. The length of the channel being considered positive, in this case one should
note that
L (VD ) =
2e 0e r (Vbi + VD
eN D
) = 2e e (V
0 r
bi
- VD )
eN D
,
because the channel length is given now by the depletion region from the source side of the
implanted line between source and drain, and not from the drain side, as for positive drain
voltages.
Integrating (4.54) one obtains
ID =
e 2 N D2 m 2 DWgeo
2e 0e r
VD
Vbi - VD
æ Vbi - VG VD
ç1 VP
2VP
è
65
ö
÷.
ø
(4.55)
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
Figure 4.13: Depletion region extensions in the source for the negative range of drain voltages: (a) zero drain
voltage; (b) small drain voltages never lead to the pinch-off of the channel. Decreasing the drain voltage the
depletion region between source and drain is supposed to extend only on Ox-direction (negative direction)
creating a longer channel, but the effective width of the channel at the source, depending only on the difference
Vbi - VG remains constant; (c) the pinch-off occurs only applying a sufficient large negative gate bias; (d)
increasing the drain voltage the channel opens at the drain but remains pinched-off at the source; (e) gate bias
higher than the pinch-off one is applied and the channel is completely closed for small (negative) drain voltages;
(f) for higher absolute values of drain voltage the channel opens (VD < VP + VG - Vbi ) .
It is important to note that this equation is not symmetric neither relative to the origin
(because of the quadratic term in VD) nor to the Oy-axis. However, for very small drain
voltages the last term from the parenthesis can be neglected in (4.19) or (4.55). Consequently,
for small negative drain voltages one should obtain approximately a linear dependence with
the same slope as for the positive small drain voltages. In other words, around VD = 0 V and
66
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
for small gate biases, one should obtain a line, which agrees with the experiments, shown in
Figure 4.5 and Figure 4.6 (between -1 V and +1 V the source-drain current has a linear
behavior).
Increasing the drain voltage in absolute value, the quadratic term becomes important
and differences between positive and negative side of the drain range become visible. Because
the effective channel width at the source is fixed by the gate bias, no pinch-off occurs for low
gate biases no matter what drain voltage is. According to the constant mobility model, the
current does not saturate. The saturation occurs only due to the field dependent mobility effect
and the saturation region was experimentally proved in both Figure 4.5 and Figure 4.6.
Considering the field dependent mobility, one should divide the current by
1 - m 2 DVD (v s L ) , and then, for negative drain voltages equation (4.44) becomes
ID = -
Q - (VD )
æ V -V
V ö
v s eN DWgeo ç1 - bi G - D ÷ ,
1 - Q (VD )
2VP ø
VP
è
-
eN D m 2 D VD
where Q (VD ) = .
2e 0e rv s Vbi - VD
-
(4.56)
(4.57)
Because no pinch-off occurs, the factor Q- (VD ) éë1 - Q- (VD ) ùû ; 1 for large negative
drain voltages, so that the current becomes
æ V -V
æ V
V ö
V ö
(4.58)
I D = -v s eN DWgeo ç1 - bi G - D ÷ ; -v s eN DWgeo ç1 - bi - D ÷
2VP ø
VP
è
è VP 2VP ø
The main result is that there is no constant value for the saturation current, but the
v eN W
slope for large negative drain currents drastically changes to p large neg. VD = s D geo = e 0e rv s .
2VP
The ratio between the slope at large negative drain voltage, for which the field-dependent
effect is important, and the slope for very small drain voltages, for which the constant
mobility approximation is valid, is
2e 02e r2v sVbi
p large neg. VD
;
= 2.27 ×10-3 (*). The result shows
p small neg. VD e 2 N D2 m 2 DWgeo
that for large negative drain voltages (practically for VD < -2 V) the current curves become
almost flat, i.e. a slow dependence on drain voltage. Practically one could say that a saturation
region is obtained, because the current is very slowly increasing in absolute value. In the
following, the references to the saturation will point to this region.
In situation (ii), completely different from the case of positive drain voltages, the
pinch-off and the saturation currents can no longer be obtained from the condition u2- = 1 , but
from u1- = 1 =
Vbi - VG
, where u1- is the normalized depletion width for negative drain voltage,
VP
corresponding to h1- . Starting from (4.54) and considering u1- = 1 one can write the saturation
current for negative drain voltage as
(*)
This value is for an IPG transistor fabricated on heterostructure 1068, whose channel width Wgeo=1µm and
Vbi=1 V.
67
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
ID = -
2
e 2 N D2 m 2 DWgeo
4e 0e r L
(1 - u ) .
- 2
2
(4.59)
By substituting u1- = 1 in (4.55) one obtains I D = -
eN D m 2 D VD2
. For u2- = 0 , namely
2
Vbi - VD
when VD = -VP , the drain voltage is sufficient to expulse completely the depletion region
from the drain, and the current becomes
ID = -
2
e 2 N D2 m 2 DWgeo
=-
4e 0e r L
2
e3 N D3 m 2 DWgeo
4e 02e r2 (Vbi + VP )
.
(4.60)
For larger negative drain voltages, there is practically no depletion in the drain region and
because of the FIB-implanted line, the channel cannot be theoretically enhanced, so that
h2- = 0 . Consequently, (4.54) becomes
0
ID
ò dx =
-L
e 2 N D2 m 2 D
2e 0e r
0
ò (W
geo
h1-
- h - ) dh - .
(4.61)
The right term is independent of the drain voltage, while the left term depends on the drain
voltage, because the length L of the channel is drain-voltage dependent. The physics of
equation (4.61) is that the width of the depletion region h1- , which is influenced only by the
gate bias, is fixed for a given gate bias, while the channel length is increasing with the drain
voltage. By integrating equation (4.61) one obtains
ID = -
2
e 2 N D2 m 2 DWgeo
4e 0e r L
(
)
u1- 2 - u1- = -
2
e 2 N D2 m 2 DWgeo
4e 0e r L
,
(4.62)
which is similar to (4.60). Equation (4.62) shows a weak dependence of the source-drain
current on the drain voltage that is given by its denominator, due to the depletion region
width L.
The third case corresponds to
large negative gate biases, when the
channel is completely pinched-off for
zero drain voltage. In this case u1,2 > 1 .
Decreasing the drain voltage, at a
certain
value
given
by
VD = VP + VG - Vbi the channel is open at
the drain electrode, but remains
pinched-off at some point in the source
region (Figure 4.14). Decreasing further
the drain voltage the current flows
through the channel and then the
situation is similar to that previously
presented.
Figure 4.14: A zoomed-in plot of the I-V characteristics of the
IPG transistor from Figure 4.6 for small negative drain
voltages. One can notice that the channel remains closed for
large gate biases until a certain value of the drain voltage
given by (4.63).
68
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
One could consider that for large negative biases there is a kind of threshold drain
voltage
(*)
VDT = VP + VG - Vbi ,
(4.63)
for which the channel is open. For higher values of the drain voltage the channel remains
closed.
4.4
Depletion and enhancement modes of the IPG
transistor
Considering the band diagrams
across the 1D-channel of an IPG transistor
Wieck [115] explained the main differences
between depletion and enhancement-mode.
Figure 4.15 presents the energy band
diagrams for three different cases:
(a) VG = 0 V; (b) VG < 0 (depletion mode)
and (c) VG > 0 ; the FIB lines are implanted
at a distance Wgeo locally producing p-type
lines in an n-type sample. The transport
direction of the 1D-channel is perpendicular
to the drawing plane. One can see that in the
p-type lines the Fermi level is pinned close
to the top of the valence band so that high
barriers are created, separating the in-plane
gates and the channel. Due to these barriers
the IPG transistors work also at room
temperature. By applying a negative bias on
the left in-plane gate, the channel is depleted
and almost the entire voltage drop will occur
very close to the channel. When the gate bias
is positive the voltage drop occurs in a
region which is further away from the
channel. Because the confining electric field
is not homogeneous (as for a surface-gate
field-effect transistor) it matters where the
voltage drop occurs.
For IPG transistors fabricated on p type wafers by writing n-type FIB lines n and p-regions are exchanged as well as the
(*)
Figure 4.15: Conduction band (Ec) and valence band
(EV) diagrams of a cross-section of an IPG transistor cut
perpendicularly to the current flow of the channel, after
Wieck [115]. The electric field lines are represented by
ellipses.
The threshold voltage is usually defined as a gate bias. Applying a gate bias less than this threshold voltage
the channel remains closed for practically any drain voltage. In our situation the channel remains closed for
any drain voltage less than the value given by (4.63).
69
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
polarity of gate bias is changed. Consequently in any IPG transistor the depletion mode is
more effective than the enhancement one.
According to the model, in the enhancement mode, the depletion region between
source and gate will move more in the gate region until it is completely expulsed from the
source. This corresponds to u1 = 0 , so that the saturation current (for positive drain voltages)
for VG ³ Vbi becomes
-1
æ m 2 DVD ö
(4.64)
I = I P ç1 +
÷ ,
vs L ø
è
which is independent of the gate bias.
It is interesting to remark that the ratio between the saturation current in the
enhancement mode and the saturation current at VG= 0V is
sat
D
-1
é enh. mVDsat ù
êL + v ú
s
ë
ûVG ³Vbi
éë I Dsat ùû
VG ³Vbi
=
-1
2
sat
éë I D ùû
æ Vbi ö é depl . mVDsat ù
VG = 0V
ç1 - ÷ ê L +
v s úûV =0V
è VP ø ë
G
and considering Figure 4.6 it results that for a typical Vbi= 1.0 V the length of the channel in
the enhancement mode is shorter than that corresponding to the depletion mode.
4.5
The IPG transistor at both RT and low temperatures –
comparison
The IPG channel characteristics change significantly with temperature. Decreasing the
temperature, two main processes occur: the mobility of the charge carriers increases typically
two orders of magnitude between RT and liquid helium temperature due to a strong decrease
of the phonon scattering and the carrier density decreases about 10 % as some carriers freeze
out.
·
The I-V and transconductance characteristics at RT
In order to study the behavior of the IPG transistors at both RT and 4.2 K one device
fabricated on the pseudomorphic heterostructure 1068 will be analyzed. The geometrical
width of the channel is Wgeo= 1.5 μm. The I-V characteristics at RT are presented in
Figure 4.16 being very similar to those from Figure 4.6, therefore the previous discussions are
also valid for the actual case. It is important to point out that the drain voltages for which the
currents saturate are smaller than 1 V for VG < 0 V (depletion mode) and between 1 - 2 V for
(
)
(
)
é1 + Q VDsat ù
ë
û
is not saturating and one should consider the transconductances given by equations (4.48) and
(4.49) for small drain voltages and the saturation regime, respectively.
VG > 0 (enhancement mode). Then, in the depletion mode the factor Q VDsat
70
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
Figure 4.16: The I-V characteristics (left) and the corresponding leakage currents (right) at RT for an IPG
transistor with a geometrical channel width Wgeo= 1.5 μm realized on wafer 1068.
Figure 4.17: The transconductance characteristics for the saturation regime (left) and for small drain voltages
(right) at RT for an IPG transistor with a geometrical channel width of Wgeo= 1.5 μm realized on wafer 1068.
Figure 4.17 presents the transconductance for both saturation regime and for small
drain voltages. The transconductance measured in the saturation regime has a linear
dependence in the range VT – -0.25 V, and all curves corresponding to drain voltages higher
than approximately 2.00 V superpose on each other. The independent-like character of the
transconductance in the saturation regime of the drain voltage was predicted by equations
(4.30) and (4.49). The linear behavior of the transconductance at saturation between -2 V and
-0.5 V suggests that the effective length of the channel Leff = L +
m 2 DVD
becomes constant for
vs
the saturation regime, i.e. in the saturation regime the effective length of the channel does not
depend on the drain voltage, the channel being in fact “screened” by both depletion regions.
For very small drain-source voltages the transconductance curves are much flatter and
in good agreement with equations (4.28) and (4.48), which both predict a constant behavior.
Again, a zoomed-in plot (Figure 4.17b) shows these curves have also a slow and linear
dependence on the gate bias that cannot be explained by any of the models presented in this
work. The measured maxima depend linearly on the drain voltage as shown in Figure 4.18.
The threshold voltage at RT is VT = -2.4 V and is given by the condition that the
transconductance at saturation is zero, as it was previously discussed.
71
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
The leakage currents are about three orders of magnitude lower than the corresponding
drain currents and indicate a good insulation between gate and source/drain.
Figure 4.18: The linear dependence between the transconductance
and the drain voltage measured for small drain voltages (VG= -0.5 V).
·
The I-V and transconductance characteristics at 4.2 K
At liquid helium temperature the I-V characteristics change drastically, as shown in
Figure 4.19. First of all, at 4.2 K the leakage currents become about two orders of magnitude
lower than those at RT. In order to have comparable currents one should increase the gate
bias. Overall in the measurements at 4.2 K the maximum allowed voltage difference over any
insulating line was 10 V in order not to destroy the device(*). Because the gate bias was
increased up to 8.0 V, the minimum drain voltage was set to -2.0 V.
Figure 4.19: The I-V characteristics (left) and the corresponding leakage currents (right) at 4.2 K for an IPG
transistor with a geometrical channel width Wgeo= 1.5 μm realized on wafer 1068.
The leakage currents are between -5 and +5 pA except the one corresponding to
VG= 0 V. Comparing with the leakage currents obtained at RT that means a decrease of more
(*)
One can notice in Figure 4.19(right) that for VG= 8.0 V there is a strong increase of the leakage current for
negative drain voltages.
72
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
than three orders of magnitude and indicates that the thermionic emission is the main
contribution to the leakage.
Figure 4.20: The transconductance characteristics for the saturation regime (left) and small drain-source
voltages (right) at 4.2 K for an IPG transistor with a geometrical channel width Wgeo= 1.5 μm realized on wafer
1068.
Figure 4.20 shows another interesting phenomenon: the threshold voltage moved to
about VT = 0 V, almost changing the transistor behavior from normally-on to normally-off. A
shift of the threshold voltage was predicted in Figure 4.10, but there a constant carrier
concentration was considered. Because one should expect a decrease of the built-in voltage
with temperature, the threshold voltage should be expected to move in opposite direction.
However, with the temperature decrease, the carrier density also decreases and, consequently,
in (4.32) the pinch-off voltage decreases and the threshold voltage increases. It results that the
shift of the threshold voltage is due to the temperature-dependence of the difference between
the built-in and the pinch-off voltage. For our situation because the threshold voltage is close
to zero it means in fact that the built-in and the threshold voltage are approximate equal.
Another remark is that the threshold voltage for low temperatures has a very weak
dependence on drain voltage Figure 4.20(left). The black curve corresponding VD= 0.3 V is
shifted to higher gate biases in comparison with the red curve, corresponding to VD= 3.6 V.
For very small drain voltages the threshold voltage is even more shifted to VG= 2.0 V, this
fact being noticed in Figure 4.20(right) for VD= 0.025 V. This suggests that for low
temperature the carrier density in the channel depends weakly on the drain voltage.
The transconductance curves in saturation regime present two distinct regions (0-2 V
and 2-8 V) with a linear behavior in both of them, but with different slopes. Probably this
occurs because the gate bias is increased too much in the positive range (enhancement mode)
and the channel cannot be enhanced accordingly. The linear behavior only in the vicinity of
zero gate bias sustains this affirmation.
Another reason for a very different behavior at RT and 4.2 K is the strong
temperature-dependent scattering mechanism. At RT the dominant scattering mechanism is
due to the optical phonons and does not depend on the impurity concentration. Therefore, the
RT mobilities in the IPG channel and in the 2DEG of the MBE heterostructures are similar.
At low temperatures, the scattering mechanism is due to the ionized impurities and therefore,
73
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
the mobilities in the channel region (very close to the FIB implanted lines) could be much
lower than in the 2DEG that is far away from the implanted lines/regions.
The implantation has also a strong influence on the carrier concentration in the
channel and this effect can be seen even at RT. The channel of the IPG transistor presented in
Figure 4.6 is closed for approximately VG= -1.5 V and considering Wgeo= 1 µm,
ND=9.16 ×1011 cm-2, it corresponds to a pinch-off voltage VP= 6.32 V and hence Vbi= 4.82 V.
This is an extremely high value for a typical built-in potential and is in strong contrast with
the fact that in the enhancement mode the channel can be enhanced only up to VG= 2.0 V.
According to the previous discussion it should be enhanced up to VG= Vbi. It results that it
eN W
might be possible that the pinch-off voltage given by VP = D geo = 6.32 V is
2e 0e r
overestimated. The numerical simulations from Figure 4.21 for an IPG transistor with the
geometrical width of the channel of 1.2 μm (it was considered also the beam size of the FIB),
ND= 5×1011 cm-2 and μ2D= 3500 cm2/(Vs) gives almost similar saturation currents with those
measured for the IPG transistor presented in Figure 4.16.
Figure 4.21: Numerical simulation for an IPG transistor with Wgeo= 1.2 μm, ND= 5×1011 cm-2,
μ2D= 3500 cm2/(Vs), Vbi= 1.7 V, using equation (4.37). The red line represents the locus of I Dmax given by
equation (4.43). The color code corresponds to that from Figure 4.16.
A strong approximation of the field dependent model is the drift velocity dependence
on the electric field given by equation (4.34). A corrected model should consider that the drift
74
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
velocity in GaAs increases almost linearly until a peak value of vp= 2.2×107 cm/s which
corresponds to an electric field of Ep= 3.2 kV/cm, then the drift velocity decreases with the
increase of the electric field, and for electric fields higher than approximate Es= 7×104 V/cm
the drift velocity remains almost constant to about a value of vs= 8×106 cm/s. Detailed
theoretical and experimental studies for drift velocity-field characteristics in different
materials can be found in Ref. 118 - 121.
In the next paragraphs a more appropriate
model for IPG transistors based on the constant
current condition along the channel and
considering the field-dependent mobility for GaAs
will be proposed and analyzed.
The drain current given by
I D = en ( x ) v ( x ) Weff ( x )
(4.65)
is constant along the channel.
The simplest situation corresponds to very
small drain voltages, when the pinch-off does not
occur and the electric field in the channel could be
in a first approximation considered constant E0. In Figure 4.22: Drift velocity versus electric field
this situation, the carrier drift velocity is also for Si, GaAs and InP (After Ref. 118 - 121).
constant in the channel and, the potential is a linear
function of coordinate x, V ( x ) µ E 0 x .
The effective width of the channel is
2e e (V + V ( x) - VG )
Weff = Wgeo - 0 r bi
= A - Bx .
eN D
1
, which means that a region of carrier accumulation forms at the
A - Bx
end of the channel (probably extended in the drain) and a depleted region at the entrance
(probably extended in the source).
A more complicate situation occurs for higher drain voltages. In this case, the electric
field increases almost along the entire length of the channel, only in a close vicinity of the
drain decreases very fast to the value E D corresponding to the drain electrode. Considering
Consequently, n ( x ) µ
E ( x ) ; kx n with n ³ 1 the corresponding potential in the channel is V ( x ) = k1 x n +1 . The carrier
velocity, according to Figure 4.22, before reaching the peak value increases almost linear,
v ( x ) µ E ( x ) so that, v ( x ) = k2 x n . In this case:
n ( x) =
I0
,
(4.66)
n +1
é
ù
2
e
e
V
+
k
x
V
0 r
bi
1
G
ú
ek2 x n êWgeo eN D
êë
úû
where I0 is the constant current through the channel considered, for example, at source
electrode.
(
)
75
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
From (4.66) by derivation with coordinate x one obtains that dn dx £ 0 for
1
1
é
ù n +1
n
x<ê
ú (VP - Vbi - VG ) n +1 ,
êë ( 2n + 1) k1 úû
so that there is a again a depleted region at the entrance of the channel and an accumulation
one inside the channel. The electric field of this dipole is opposite to the drain field, so that
the drain current can be significantly reduced. The leakage currents from Figure 4.16, which
are negative for positive gate biases could be explained by this opposite electric field.
Additionally, the maxima predicted by the theoretical models for constant and field-dependent
mobility might vanish also due to this dipole formation.
In Figure 4.23 the point x1
corresponds to the maximum drift velocity
of the carriers and the effective width of the
channel is Weff 1. Since effective width of the
channel continues to decrease, while the
carriers move slower and slower, strong
electron accumulation should form in this
region in order to preserve a constant
current. At the point x2 the effective width of
the channel is again Weff 1 and the electrons
move faster, causing a strong depletion
layer. The main issue is the apparition of
another stationary dipole layer and most of
the drain voltage distributes along these two
dipoles. The existence of the stationary
dipole from the end of the channel of a JFET
was for the first time demonstrated by
Kennedy and O’Brien [122] who showed
that the field-dependent carrier mobility, in
conjunction with the condition to preserve
the current continuity produces regions of
carrier accumulation and depletion within
the source-drain channel. They showed that
these regions of accumulation and depletion
are located throughout that portion of the
channel normally assumed to be pinched-off. Figure 4.23: The electric dipoles formation in the IPG
Liechti [40, 123] showed how the electric transistor channel and the corresponding electric field,
field, drift velocity and space-charge are drift velocity and space-charge distribution. The dotted
distributed in a GaAs MESFET channel blue curve from the drain marks the region, in which the
charge is “pushed” outside the channel due to
operated in saturation regime.
electrostatic forces.
Because the electric field in the
76
Chapter 4: IPG transistors fabricated by FIB implantation in negative pattern definition
channel decrease very fast at the end of the channel, the charge from this region is much
higher than that from the entrance and the electrostatic repulsion can “push” a part of it
outside of the channel, in the drain.
For negative drain voltages the dipoles location changes accordingly. In the case of
very short channels the velocity “overshoot”, i. e. a higher drift velocity than the equilibrium
value may be expected. A discussion about the velocity “overshoot” can be found in Ref. 40
and it was shown that the electrons travel a distance of about 1 μm before to relax to the
equilibrium velocity. Wieck [114] confirmed that this hypothesis is true for IPG transistors.
This velocity “overshoot” together with the change of the dipole position in the channel may
be the main reasons why the IPG transistors do not function in high frequency regime.
Another strong approximation considered was that FIB implantation produces 2D p-n
junctions and the carrier densities in p- and n-regions are approximately equal. In order to
produce insulating lines the required dose of implantation is high and one should expect a
strong difference between the carrier density in 2DEG and the carrier density from the lines.
Some corrections to the equation (4.1) are in this situation required.
Finally, the hypothesis that the FIB creates abrupt 2D p-n junctions might be less
correct and, consequently, some differences between the experimental data and the theoretical
models might be due to this hypothesis. According to Petrosyan et al. [109] for a 2D
linearly-graded p-n junction, the depletion region width depends as a square root on the
applied voltage. (Table 4.1). In this case, the drain current is completely different and all the
aforementioned models to calculate the I-V characteristics should be adjusted in order to
correspond to 2D linearly-graded p-n junctions hypothesis.
77
– Chapter 5 –
In-plane gate transistors fabricated by focused ion
beam implantation in positive pattern definition
5.1
Fabrication of IPG transistors in positive pattern
definition
Since the invention of the IPG transistor, different geometries, materials and
techniques were proposed for devices based on the same in-plane gate principle [124 - 129].
The main idea of the IPG transistor fabrication is that starting from a heterostructure with a
2DEG, a narrow quasi-1D channel can be defined using FIB technique to implant insulating
lines. The gate bias can control the effective width of the channel and consequently, the drain
current. This method is also known as negative pattern definition. Even if there is no report
about IPG transistors fabricated in negative pattern definition on heterostructures with 2DHG,
it is theoretically also possible to use p-type wafers as starting material. However, depending
on the heterostructure doping, only one type of carriers governs the electrical transport
properties of these devices and the fabrication of both n- and p-type IPG transistors on the
same wafer is intrinsically impossible. Another difficulty to fabricate IPG transistors in
negative pattern definition on heterostructures with a 2DHG consists in the impossibility to
obtain high resistive Ga-implanted regions after heat treatment [12].
A different approach is to start from a semi-insulating substrate, which can be used as
highly resistive region, and to implant both the channel and gate regions. Consequently,
contrary to the negative pattern definition, in which one implants insulating lines in order to
define the quasi-1D channel, in positive pattern definition one implants conductive regions.
Due to the implantation process, which induces defects, the electrical characteristics of the
implanted regions are not too good. It is therefore necessary to perform a rapid thermal
annealing process, immediately after the implantation, in order to heal these defects and repair
the lattice. Also, the optimization of the FIB implantation doses is a very important step for
improving further the mobility, and therefore the channel conductivity. Hirayama [6] was the
first to fabricate n- and p-type IPG transistors by implanting Si2+ and Be2+, respectively, on the
same semi-insulating GaAs substrate (Figure 5.1). The devices showed good channel
conductance controllability at RT by application of in-plane gate voltages. The main
disadvantage of this method consists in the use of the semi-insulating substrate as high
resistive region between gate and channel and therefore, one cannot employ the high carrier
mobilities obtained in selectively doped heterostructures. However, the fabrication of a 2DEG
78
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
by implantation doping of an initially undoped heterostructure is a very difficult task. Sasa et
al. [7] fabricated 2DEGs in undoped GaAs/AlxGa1-xAs quantum well heterostructures by
implanting Si2+ ions. Their measurements proved that the transport properties are dominated
at T= 4.2 K by the successful formation of a good quality 2DEG in the quantum well, but at
the same time proved also the existence of a second 2DEG at an interface of the
heterostructure forming a parallel conducting channel. Meier et al. [107] studied the 2DEG
fabrication by FIB doping in Al0.33Ga0.67As/GaAs pseudomorphic heterostructures with a
strained In0.1Ga0.9As channel and quantum wells. They reported the successful fabrication of
2DEGs in all systems without parallel conduction.
Based on these results, a
metamorphosis of the positive pattern
definition technique proposed by Reuter et
al. [8] is to use as substrate an undoped
pseudomorphic HEMT heterostructure, for
example, GaAs/In0.1Ga0.9As/Al0.35Ga0.65As,
and dope it locally by FIB implantation
(Figure 5.2a). In this way they have
fabricated two-dimensional IPG transistors
by
creating
2DEGs
in
undoped
heterostructures. Even if until present there
is no report on Be doping, the FIB
implantation
doping
of
undoped Figure 5.1: Schematic diagram of an in-plane gate
semiconductor heterostructures offers the transistor written in positive pattern definition on a
possibility to create both 2DEGs and semi-insulating substrate after Hirayama [6]: (a) top
view; (b) enlarged top view of the center region; (c)
2DHGs by implanting n- or p-type dopants. cross section along the line a-b from (b). The green
However,
there
are
some represents implanted regions, while the yellow indicates
technological difficulties to implant both ohmic contacts.
types of dopants in the same wafer, due to the different implantation depths, e. g. Be has a
three times larger implantation depth than Si (Figure 1.5d), or due to the alignment step,
which should be performed for both implantation patterns, and finally not to forget about
refocusing, which is necessary when changing the ion species. In order to overcome these
difficulties Reuter et al. [105] proposed another method to obtain a 2DEG with no parallel
conducting channel at both 4.2 K and RT in a p-doped GaAs/InyGa1-yAs/AlxGa1-xAs
heterostructure. This method relies on the local compensation doping of the p-doped
heterostructure. One of the advantages consists in the fact that it is easier to grow a
heterostructure and set the depth of the 2DHG at the corresponding depth of the maximum ion
distribution to ensure the alignment between 2DHG and 2DEG. In other words, because only
one type of ion is implanted, the heterostructure is designed to the necessary depth of the ion
distribution given by the implantation parameters. The implantation patterns, which should be
aligned during the implantation process with two ion species, together with the necessary
supplementary refocusing step, are eliminated.
Proving to be a successful method to obtain a 2DEG, in 2004 Reuter et al. [9]
proposed another change from the original positive pattern definition technique to obtain
79
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
n- and p-channel transistor devices that require the implantation of only one type of dopant.
According to this technique, one uses as substrate p-type GaAs/InyGa1-yAs/AlxGa1-xAs
heterostructures and implants only Si2+, the 2DEG formation being based on local
overcompensation doping (Figure 5.2 b1 and b2). This method opened the possibility of
fabrication of two-dimensional n- and p-type IPG transistors from the same heterostructure
[8, 9]. In comparison with all the other techniques having between gate(s) and channel a
damaged region [1, 114] (insulating lines for negative pattern definition), a semi-insulating
substrate [6] or an undoped gap [8] in this case one has a 2D p-n junction. This fact made
Reuter et al. [9] to call this transistor IPG junction field-effect transistor (IPGJFET).
Figure 5.2: (a) Schematic implantation pattern, defining the IPG transistor after Reuter [8] using as substrate an
undoped pseudomorphic heterostructure (brown). The 2DEG (green) is obtained by Si2+ FIB implantation. (The
ohmic contacts are not represented here); (b1) and (b2) The important part of the implantation pattern for an
n- and p-type channel IPGJFET respectively, both obtained by the local overcompensation doping [9] on the
same p-type GaAs/InyGa1-yAs/AlxGa1-xAs.
All experiments and devices studied in this chapter are based on this new method, so
that any reference to the positive pattern definition technique should be understood as
pointing to this one.
5.2
Theoretical aspects – basic device characteristics
The main goal of this Section is to calculate the current-voltage dependence through
the channel. It will be considered that the FIB implantation produces 2D abrupt junctions
between the 2DHG (or 2DEG) of the wafer and the 2DEG (or 2DHG, respectively) realized
by FIB implantation in positive pattern definition. As in Chapter 4.3, the source is grounded,
so that all voltages will be considered, as previously, with respect to the source electrode. For
a p-n abrupt 2D-junction, the width of the depletion region is given by the equation (4.1).
80
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
A simple model for IPGJFETs
The simplest model considers that the channel is defined by two depletion regions,
each one appears along the geometrical implanted line, which is the border between the
channel and the gate (Figure 5.3). Of course, both depletion regions are linear functions of the
applied voltage across the respective 2D p-n junction.
The following hypotheses will be considered:
(i)
FIB produces an abrupt junction;
(ii) using FIB, 2D uniform doped n- and p-regions with the same carrier concentrations
are obtained;
(iii) gradual channel approximation – the depletion region varies gradually along the
channel;
(iv)
long-channel IPG transistors, i.e. L0 ? Wgeo , h ( L0 ) ;
(v)
the constant mobility approximation, which implies that the mobility does not depend
on electric field (valid only for low electric fields).
The corresponding depletion widths
at source and drain are:
2e e (V - V )
h1 = h(0) = 0 r bi G ,
(5.1)
eN D
h2 = h( L0 ) =
2e 0e r (Vbi + VD - VG )
.
eN D
(5.2)
In contrast with the model
developed for the IPG transistors fabricated
in the negative pattern definition, this
Figure 5.3: Depletion regions in the channel
simple model considers the length of the
channel to be constant.
When the depletion region extends in the entire channel at the drain electrode, then
Weff ( L0 ) = Wgeo - 2h ( L0 ) = 0 and the corresponding voltage is called the pinch-off voltage. In
other words, the pinch-off voltage is the drain voltage necessary to increase the depletion
width at the drain from zero to the half of the geometrical width of the channel:
eN W
eN a
VP = (V ( x) - VG + Vbi ) W ( L )=0, V =V = D geo = D .
(5.3)
0
G
bi
4e 0e r
2e 0e r
Considering the assumptions (i) – (v) the drain-source current would be
æ dV ö
I D = J x2 DW ( x) = eN D m 2 D ç
÷ 2 éë a - h ( x ) ùû .
è dx ø
(5.4)
Following the same method described in Chapter 4.3, integrating from zero to the length of
the channel one obtains
ID =
e 2 N D2 m 2 D
e 0e r L0
1 2
é
2 ù
êë a ( h2 - h1 ) - 2 ( h2 - h1 ) úû .
Considering the normalized depletion widths:
81
(5.5)
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
h( x) V ( x) + Vbi - VG
=
,
a
VP
u ( x) =
(5.6)
u1 =
h1 Vbi - VG
=
,
a
VP
(5.7)
u2 =
h2 VD + Vbi - VG
=
,
a
VP
(5.8)
the current can be written as
ID =
e 2 N D2 m 2 D a 2
é 2 ( u2 - u1 ) - ( u22 - u12 ) ù = I P é 2 ( u2 - u1 ) - ( u22 - u12 ) ù ,
û
ë
û
2e 0e r L0 ë
(5.9)
or as
I D = I P ( u2 - u1 )( 2 - u2 - u1 ) = 2 I P
VD
VP
æ Vbi - VG VD
ç1 VP
2VP
è
ö
÷,
ø
(5.10)
where
IP =
e 2 N D2 m 2 D a 2
.
2e 0e r L0
(5.11)
For low drain-source voltage the last term in the parenthesis from equation (5.10) can
be neglected, so that I D µ VD . For low drain-source voltage the current increases linearly
with the applied voltage.
The saturation current is obtained for u2 = 1 in (5.9):
2
I Dsat = I P éë 2 (1 - u1 ) - (1 - u12 ) ùû = I P (1 - u1 ) or
(5.12)
2
I
sat
D
æ V -V ö
= I P ç1 - bi G ÷ .
VP ø
è
(5.13)
The transconductance g m is defined as
gm =
é2
ù 2I V
¶I D
= I P ê ( u2 - u1 ) ú = P 2 D ,
¶VG
VP
ëVP
û
gm V
D = ct
(5.14)
= ct .
The transconductance in the saturation region is
g msat =
¶I Dsat 2 I P æ Vbi - VG
=
ç1 ¶VG
VP è
VP
ö
÷,
ø
g msat =
2 I (V - V )
2I P
VG + P P2 bi , which is a linear function of VG .
2
VP
VP
(5.15)
The transconductance measured in the linear region of I-V characteristic for a
given drain voltage is a constant, and in the saturation regime is a linear function of the
gate bias.
The measured transconductance characteristics for both linear and saturation regime
are illustrated in Figure 5.4.
82
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
Figure 5.4: The transconductance characteristics for an IPGJFET measured for both the linear region of I-V
characteristic and the saturation regime.
The slope of g msat = f (VG ) is given by: p =
2 I P 4 m 2 D e 0e r
=
.
VP2
L0
Introducing the value of the slope in equation (5.14) one obtains:
g m = pVD .
(5.16)
(5.17)
The transconductance values obtained for different drain voltages in the linear
region of I-V characteristic are correlated with the slope of the saturation
transconductance by the drain voltage.
This means that knowing the transconductance in the saturation regime one could
determine the transconductance in the linear regime for any given VD. This fact is very well
illustrated in Figure 5.5.
83
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
Figure 5.5: The transconductance measured for an IPGJFET for very small drain voltages (zoomed-in plot of the
previous figure). The curves are flat in comparison to those from the saturation regime, but in a zoomed scale,
one can see that practically immediately after the gate voltage is higher than the threshold voltage, all curves
increase almost linearly, having slopes closer and closer to that corresponding to the saturation. The maxima are
situated at multiples of 2.5 µS, in good agreement with the value obtained from the product p∙VD. In the vicinity
of the region, where the 2D p-n junction between source and gate is forward biased, all curves decrease.
Considering the value of
the slope of the saturation
transconductance (5 × 10-5 S/V)
(Figure 5.6) and the fact that the
drain voltage was increased in
steps of 0.05 V the expected
transconductance values in the
linear
region
of
I-V
characteristics correspond to the
measured ones.
Finally, another result
can be obtained from the
expression of the saturation
current: one can see that when
I Dsat = 0 ,
the
saturation
transconductance g msat is also
Figure 5.6: The saturation transconductance measured for VD= 5.0 V.
In the region, in which the transistor is normally working, the
saturation transconductance is linear.
zero.
The transconductance in the saturation regime becomes zero at the same time as the
saturation drain current I Dsat becomes zero. In other words, when the channel is completely
closed the transconductance in the saturation regime is zero.
84
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
The equation I Dsat = 0 implies that VT = Vbi - VP or VT = - VP - Vbi . This means that
the threshold voltage, VT (the bias for which the channel is completely closed) is the gate bias
which applied to the gate extends the depletion region at the source electrode to half of the
channel ( h1 = a ). Practically, when both depletion regions extend in the channel so much that
the channel is fully “flooded” by the depletion regions, then the saturation current and the
transconductance are zero.
The field-dependent mobility
Due to its very restrictive hypotheses the above model cannot perfectly describe the
experimental results. In order to overcome the discrepancies between theory and experimental
data, a reconsideration of these hypotheses is necessary. First of all, the constant mobility
approximation cannot make good predictions at high electric fields, especially for GaAs
material.
This approximation is only valid for low electric fields in the region where the
velocity increases linearly with the field, and the slope corresponds to a constant mobility. But
by further increasing the electric field, the velocity reaches a peak value and then decreases
toward a value of about 6 - 8 × 106 cm/s.
An analytic expression proposed for the drift velocity is given by (4.34) and
introducing it in the drain-source current expression, as in previous chapter, one obtains that
the current given by (5.9) is reduced by a factor of 1 +
ID =
I P éë 2 ( u2 - u1 ) - ( u22 - u12 ) ùû
m 2 DVD
1+
v s L0
.
m 2 DVD
:
v s L0
(5.18)
This formula valid for IPGJFET transistors is the analogous formula obtained for the
first time by Lehovec and Zuleeg [130], who made all calculations for 3D JFET transistors.
The main difference consists in the fact that the depletion region has a dependence on the
square root of the applied voltage and, of course, the expressions for the normalized depletion
widths used in their calculations are different. Writing the source-drain current in a similar
form, and using adequate normalized depletion widths corresponding to the 2D case, when the
dependence of the depletion region is a linear function on the applied voltage, the following
form for equation (5.18) is obtained:
2
2
I D 2 ( u2 - u1 ) - ( u2 - u1 )
=
,
IP
1 + z ( u2 - u1 )
(5.19)
where the parameter z is the ratio between the small-field velocity extrapolated linearly to the
field VP/L0 and the saturation velocity [130]:
85
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
VP
L0 mVP
z=
=
.
vs
v s L0
m
(5.20)
For the constant mobility v s ® ¥ , so that z = 0 .
Equation (5.19) has a maximum u2 = um , which is the solution of
1ö
2
æ
um2 - 2 ç u1 - ÷ um + u12 - = 0 .
(5.21)
zø
z
è
By substituting in (5.19) one obtains
2 I (1 - um )
I Dsat = P
.
(5.22)
z
Equation (5.19) can be written in a very general case considering the variable
V -V
V
x = u2 - u1 = D that gives the dependence on drain voltage and the parameter u1 = bi G
VP
VP
which gives the dependence on gate bias:
I D 2 x - x 2 - 2 xu1
=
.
IP
1 + zx
(5.23)
This equation is valid for any IPGJFET, the dependence on material being given by
the saturation drift velocity. Graphical representations of equation (5.23) are given in
Figure 5.7, Figure 5.8 and Figure 5.9.
Figure 5.7: Numerical simulation for the normalized drain current of an IPGJFET as function of the normalized
drain voltage and the field dependent mobility parameter for different gate biases in GaAs (v s ≈ 107 cm/s).
86
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
Figure 5.8: Numerical simulation for the normalized drain current vs. normalized drain voltage with the gate
bias as parameter for the constant mobility approximation (z=0) for IPGJFETs in GaAs (v s ≈ 107 cm/s).
Figure 5.9: Numerical simulation for the normalized drain current vs. normalized drain voltage with the gate
bias as parameter for the field dependent mobility with z= 30, for IPGJFETs in GaAs (v s ≈ 107 cm/s).
87
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
Two-region model
Hypothesis (iv) is probably not suitable for the real case. It assumes that the channel is
much longer than both the depletion region at the drain, which can be in micrometer range
and become comparable with L0, and the geometrical width of the channel. In this case, the
real length of the channel is
2e e (V + VD - VG )
L = h1 + L0 + h2 @ L0 + h2 = L0 + 0 r bi
,
(5.24)
eN D
where the depletion width at the source h1 was neglected.
The hypothesis (iii), the gradual channel approximation, is also valid only until the
pinch-off condition is fulfilled, so that it should be replaced with another more general
approximation.
An appropriate model is obtained if
one considers the channel divided in two
main regions: in the first region, near the
source, the constant mobility and gradual
channel approximations are valid, in the
second region a conductive channel of finite
width is postulated and the velocitysaturation phenomena governs the transport
mechanisms.
The position corresponding to the
velocity saturation (x = L1) in Figure 5.10 is
not fixed at the drain end of the channel as
the field dependent mobility approximation
supposes. The position of the point where
the drift velocity saturates is allowed to be
at any distance in the channel, according
only to the field distribution. This position
can be determined from the condition that
the longitudinal channel field reaches the
critical value, for which the carriers drift
velocity is vs.
Defining the normalized depletion Figure 5.10: (a) The depletion regions for an
width at the point x = L1
implantation pattern like those presented in Figure 5.2
in two-region model; (b) Region I has constant mobility
yc
uc = ,
and region II has saturated velocity.
a
and integrating from x = 0 to x = L1 (instead
of x = L0) one obtains an expression similar to (5.9) except that u2 is replaced by uc and IP by
I1:
88
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
ID =
where I1 =
e 2 N D2 m 2 D a 2
é 2 ( uc - u1 ) - ( uc2 - u12 ) ù = I1 é 2 ( uc - u1 ) - ( uc2 - u12 ) ù ,
û
ë
û
2e 0e r L1 ë
e 2 N D2 m 2 D a 2
.
2e 0e r L1
(5.25)
(5.26)
In region II the carriers have a constant drift velocity v s = m Ec :
I D = eN Dv s 2 ( a - yc ) = I S (1 - uc ) ,
(5.27)
where I S = 2eN Dv s a = eN Dv sWgeo is the open-channel saturation current, which would flow
between source and drain if the depletion regions are zero and the carriers move with the
saturation velocity. From (5.25) and (5.27) one can obtain the length L1
(
)
(
2
2
2
2
eN D m 2 D a 2 ( uc - u1 ) - uc - u1
VP m 2 D 2 ( uc - u1 ) - uc - u1
L1 =
=
vs
2e 0e rv s
1 - uc
1 - uc
)
(5.28)
Considering the parameter z defined by (5.20), the length L1 can be written as
L1 = zL
(
2 ( uc - u1 ) - uc2 - u12
)
(5.29)
1 - uc
where L is defined by (5.24).
The potential between the point x = L1 and source can be calculated by integrating the
longitudinal electric field from x = 0 to x = L1:
L1
yc
0
h1
V ( region I ) = ò Edx =
eN D
ò 2e e
dh = VP ( uc - u1 )
(5.30)
0 r
In region II the potential can be calculated using Laplace’s equation and keeping the
lowest space harmonic [40]
V ( region II ) @
é p ( L - L1 ) ù
2a
py
Ec cos
sinh ê
ú
p
2a
2a
ë
û
(5.31)
Finally, the source-drain potential will be
ìï
é p ( L - L1 ) ù üï
2 a
VD = VP í( uc - u1 ) +
sinh ê
(5.32)
úý
p zL
2a
ë
û þï
îï
From (5.29) and (5.32) one can eliminate L1 and determine uc for a certain (VG, VD).
That is equivalent with determining the source-drain current ID since equation (5.27) gives the
relation between uc and ID.
Finally, it should be pointed out that a more complicated model must also consider the
existence of the regions of carrier accumulation and depletion within the source-drain
channel, which can de deduced from the current continuity condition together with the
field-dependent carrier mobility.
A similar situation with that discussed in the end of the Chapter 4 (Figure 4.23) also
occurs for the IPG transistors implanted in positive pattern definition. The static electric
dipoles, which form in the channel, have a strong influence on all electric characteristics,
including I-V, i.e. the disappearance of the maxima from low drain voltages predicted by the
theoretical models, the leakage currents or transconductances.
89
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
5.3
In-plane gate transistors
heterostructures
fabricated
on
p-doped
The starting heterostructures for these IPG transistors were described in details in
Chapter 2. The band diagram of the significant layer sequence of the heterostructure is
illustrated in Figure 5.11. The quantum well (QW) is situated at 85 nm under the sample
surface.
Figure 5.11: (a) Energy band diagrams for the significant sequence of layers in heterostructure 12290; (b) SRIM
simulation of the Si2+ ions penetration into the same heterostructure. The acceleration voltage of the incident ions
is 30 kV, which corresponds to an energy of 60 keV. The total number of ions in the simulation is 10 6.
The QW position was optimized for RT measurements, i.e. its position was considered
so that a large number of ions should reach it. The electron density and mobility at both RT
and liquid helium temperature for a relatively large interval of implantation doses are
presented in Figure 5.12. The data have been determined by Hall measurements in van der
Pauw geometry [131, 132] after the RTA was performed.
Figure 5.12: (a) The electron density and (b) mobility as functions of the dose of implantation for
heterostructures like the one presented in Figure 5.11 implanted by FIB in positive pattern definition.
90
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
As one would expect the carrier concentration increases with the implantation dose for
both RT and liquid helium temperature, but the increase for the latter is smaller. At the same
time with the implantation dose increase, the formation of defects also increases. The
annealing step, although very efficient, cannot remove all these defects, so that the mobility
decreases due the defects that could not be removed by RTA and act as scattering centers. The
mobility value of 5000 cm2/(Vs) obtained at RT for the lowest implantation doses is
comparable to the typical values obtained for bulk doped AlxGa1-xAs heterostructures obtained
by MBE. This shows that for low implantation doses most of the defects generated by FIB
implantation are removed during the RTA. At low temperatures, the mobility values are more
than one order of magnitude smaller than the typical values obtained from MBE-doped
material. This fact can be explained by a strong temperature dependent scattering mechanism.
At RT the dominant scattering mechanism is due to the optical phonons [133], and does not
depend on the impurity concentration. The RT mobilities of implantation doped and
MBE-doped heterostructures are therefore similar. At low temperatures, the scattering
mechanism is due to the ionized impurities and hence, the mobilities of the FIB-implanted
heterostructure are much lower than those obtained in MBE-doped ones.
These results are in good agreement with the results obtained by Reuter et al. [105]
who studied the 2DEG formation in p-doped GaAs/InyGa1-yAs/AlxGa1-xAs heterostructures by
FIB implantation of Si2+ ions. They also used different measurement techniques to
demonstrate both the 2DEG formation and the absence of any unwanted parallel conducting
channel for implantation doses up to 1×1013 cm-2 (Figure 5.13). For low temperature, the
magneto-transport measurements (at high magnetic field) showed pronounced oscillations in
the longitudinal resistance (Shubnikov-de Haas oscillations) and, together with a Fourier
analysis, demonstrated the existence of only one frequency as one would expect from a single
2DEG. Hall measurements (at low magnetic fields) found practically the same value for the
electron density. While the magneto-transport measurements at high magnetic fields detect
only the electrons in 2DEG, the Hall measurements probes all free electrons from the sample.
Figure 5.13: (a) The longitudinal resistance for an electron system fabricated by compensation doping of a
p-doped GaAs/InyGa1-yAs/AlxGa1-xAs after Reuter [105]; (b) Apparent carrier concentration as a function of the
depth, determined by C-V spectroscopy for a 2DEG fabricated by 60 keV Si-implantation doping of a p-type
heterostructure [105]. The depth profile shows there is no parallel conductive channel [134].
The perfect agreement between these two techniques demonstrates that all electrons
are located in 2DEG and no parallel channel is formed.
91
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
Because at RT the Landau quantization is smaller than 4k BT , the magneto-resistance
measurements cannot be used to check the existence of any parallel conducting channel.
Consequently, capacitance-voltage spectroscopy [134] was used. No free carriers were
detected up to the depth of the In0.11Ga0.89As channel where the 2DEG was formed.
n- and p-channel IPGJFETs fabricated on p-doped heterostructures
Different p-doped heterostructures grown by MBE, similar to that presented in
Figure 5.11(a) were implanted with Si2+ ions with an energy of 60 keV. The ion doses were
around 1013 cm-2. After implantation, the samples were annealed in a RTA furnace. All details
about the sample preparation can be found in Chapter 2. The typical geometry of the
implantation is shown in Figure 5.14 and this is also the geometry which provides the best
results(*) for I-V characteristics: highest drain-source currents, lowest leakage currents, etc.
The n-channel IPGJFET supposes that the channel region is implanted, while for the
p-channel one, the gate regions are implanted. Of course, the corresponding recipes for the
ohmic contacts were used, as shown in the figure. Under the contacts evaporated on implanted
regions, squares of about 100 µm2 were implanted with higher doses (around 1014 cm-2) in
order to provide a better ohmic contact.
Figure 5.14: (a) Perspective view of an implanted IPGJFET realized on a p-doped heterostructure; A zoomed-in
area of the channel region is also presented for (b) an n-channel IPGJFET (implanted channel) and (c) a
p-channel IPGJFET (implanted gates). Green represents the implanted region (n-type) while red the p-doped
heterostructure.
(*)
A detailed study of IPGJFETs implanted with different geometries will be presented in Section 5.5
92
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
5.3.1 n-channel in-plane gate transistors
Figure 5.15 presents the I-V characteristics and the corresponding leakage currents of
an n-type channel IPGJFET measured with a parameter analyzer HP4156A at RT. All
measurements were performed with both gates connected together and the source connected
to the ground. The channel can be fully controlled by the gate bias, being completely
pinched-off for a gate bias of VG = -2.40 V. For small drain voltages, the field independent
mobility approximation is valid and, consequently, the source-drain current increases
approximately linear with VD. Increasing further the drain voltage, the current saturates, but a
linear increase can still be observed. According to A. Seekamp [17] the saturation region can
be well described if one multiplies the initial saturation value of the current with
é1 + l (VD - VDsat ) ù , where λ is a fitting parameter. In this case equation (5.13) becomes
ë
û
2
æ V -V ö
(5.33)
I D (VD > V ) = I P ç1 - bi G ÷ éë1 + l (VD - VDsat ) ùû .
VP ø
è
For VG= 0 V the corresponding λ equals 0.0161 V-1. Between 0 - 15 V, the leakage
currents are more than three orders of magnitude lower than the saturation source-drain
current measured at VG= 0 V and this interval is quite large compared to the typical drain
voltage domain, 0-5 V. This shows that the breakdown occurs at relatively large drain
voltages.
sat
D
Figure 5.15: (a) I-V characteristics and (b) the corresponding leakage currents obtained for an n-type channel
IPGJFET implanted in the geometry presented in Figure 5.14b. All measurements were performed at RT.
The transconductance measurements, presented in Figure 5.16 show the following
characteristics:
· for gate biases lower than the threshold voltage the transconductance is zero,
independent of the drain voltage.
93
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
·
for drain voltages higher than the saturation value, when the 2D p-n junctions between
gates-source and gates-drain are reverse biased, the saturation transconductance is
linear when the channel is open.
·
for the transconductance measured at very small source-drain voltages (when the
IPGJFET works in the linear region of I-V characteristics) almost “flat” curves are
obtained and the mean value of these curves is dependent on the applied drain
voltage. A zoomed-in plot (Figure 5.16b) shows that these “flat” curves are
monotonically increasing until a maximum close to zero gate bias, and the position of
the maximum is practically fixed.
Figure 5.16: (a) The transconductance measured for both linear region of I-V characteristic and saturation for an
n-type channel IPGJFET implanted in the geometry presented in Figure 5.14b. (b) A zoom of the
transconductance measured in the linear region of I-V characteristics. One can see that the flat maxima of the
curves perfectly match the product between the slope and the drain voltage, as the theoretical model predicts
(equation (5.17)). All measurements were performed at RT.
A short analysis of these results will be performed in the following paragraphs. The
first result is obvious: because no current flows through the channel when the gate bias is
lower than the threshold voltage, the transconductance is zero.
According to equation (5.15), the transconductance is linear for drain voltages higher
than the saturation value. The slope of the saturation transconductance is independent of the
gate bias, fact very well illustrated in Figure 5.16a. For higher drain voltages all the curves
have the tendency to superpose over the curve obtained for about VD = 4.5 V, and any further
increase of the drain voltage will not change this slope.
Equation (5.17) gives a correlation between the slope of the saturation
transconductance and the theoretically predicted constant values of the transconductances
obtained for very low drain voltages. A linear fit of the saturation transconductance gives a
value of the slope of p= 58 µS/V. Increasing the drain voltage in small steps of 0.05 V, from
zero to 0.45 V, the values of the maxima obtained in Figure 5.16b are exactly at multiples of
2.9 µS, as the product pVD requires.
For positive gate biases, the 2D p-n junction between source and gate becomes
forward biased and, consequently, the leakage currents drastically increase. The
94
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
transconductance decreases for positive gate biases, demonstrating that the channel
controllability with the gate bias decreases. It is the increased leakage current that might be
responsible for this behavior. In fact, the leakage component of the total current, which flows
through the channel, becomes almost comparable with the source-drain current. Since the
leakage component cannot be controlled by the gate bias, the transconductance decrease is
reasonable.
5.3.2 p-channel in-plane gate transistors
The experimental results obtained for a p-type channel IPGJFET are presented in
Figure 5.17. As for n-type channel IPGJFETs when the drain voltage is small, the sourcedrain current increases linearly in absolute value with the drain voltage. Increasing further the
absolute value of the drain voltage, a saturation region is observed (-20 V < VD < -5 V). One
difference from the n-type IPGJFETs is the range of the drain current, which is much reduced
in this case of p-type channel IPGJFETs. This can be explained by the much lower mobility of
the holes. Also, the shape of the curves are different i.e. the relative increase of the current in
the saturation regime for the p-channel IPGJFETs is higher than for the n-channel IPGJFETs.
This is in fact given by the increase of the fitting parameter λ, which is about four times
higher for p-channel IPGJFETs λ= 0.0442 V-1 for zero gate bias.
The not well-pronounced saturation behavior can be explained by the hole drift
velocity which is not saturated with the electric field along the channel.
Another difference between the aforementioned n-channel IPGJFETs and the p-type
ones consists in the leakage currents. For p-type channel IPGJFETs the leakage currents are
about only two orders of magnitude smaller than the corresponding source-drain currents in
the saturation regime. The channel can hardly be closed, and it is necessary to apply a gate
bias of about 20 V, in order to completely close the channel.
Figure 5.17: (a) I-V characteristics and (b) the corresponding leakage currents obtained for a p-type channel
IPGJFET implanted in the geometry presented in Figure 5.14c.
95
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
5.4
In-plane gate transistors fabricated on n-doped
heterostructures
Up to now, only p-doped heterostructures were used for the fabrication of n- and
p-channel IPGJFETs. No results were reported for n-doped heterostructures. In this Section
the experimental results obtained on n-doped heterostructures will be presented and analyzed.
Figure 5.18: (a) Energy band diagrams for a significant sequence of layers in the heterostructure 12341; (b)
SRIM simulation of the Be+ ions penetration into the same heterostructure with an acceleration energy of
30 keV. The total number of ions in the simulation is 106.
The sequence of layers and other details for the heterostructures were already
presented in Chapter 2, so that only the main aspects will be pointed out here. First, of course,
the δ-doping of the MBE-grown
heterostructure was changed from
C-δ-doping to Si-δ-doping. Second,
to overcompensate the initial doping
of the wafer one should implant now,
the complementary ion, for example
Be+. Because the Be+ has an
extremely different ion range(*) a
SRIM
simulation
is
required
(Figure 5.18). Then, the depth of the
quantum
well
was
adjusted
accordingly to roughly 145 nm under Figure 5.19: The hole density and mobility as functions of the
the sample surface. This ensures a dose of implantation for heterostructures like the one presented
in Figure 5.18 implanted by FIB in positive pattern definition.
(The blue and red lines are not a fit, but a guide for the eye).
(*)
An example for Si+ and Be+ ions implanted with the same energy in AlGaAs heterostructures and the
difference between ion ranges was given in Figure 1.5.
96
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
good comparison with the previous results.
The RT density and mobility of the 2DHG obtained by FIB implantation within the
heterostructure as a function of the implantation dose are presented in Figure 5.19. One can
notice the increase in the carrier density and the strong decrease of the mobility in comparison
with those obtained for the 2DEG obtained in p-doped heterostructures using the same
technique.
FIB implantation of n- and p-channel IPGJFETs on n-doped heterostructures
Si-δ-doping MBE-grown heterostructures were implanted with Be+ ions, which were
extracted from an Au-Be-Si LMIS source, with an energy of 30 keV. The ion doses were
between 2 × 1012 and 4 × 1013 cm-2. In order to allow a better comparison with the transistors
obtained on p-doped wafers, the implanted geometry was the same, the only difference being
the complementary type of the channel. The corresponding recipes for the ohmic contacts
were used, as shown in the Figure 5.20. Under the contacts, which were evaporated on the
implanted regions, squares of about 100 µm2 were implanted with higher doses (around
1014 cm-2) in order to provide a better ohmic contact.
Figure 5.20: (a) Perspective view of an implanted IPGJFET realized on an n-doped heterostructure; A
zoomed-in area of the channel region is also presented for (b) a p-channel IPGJFET (implanted channel) and (c)
an n-channel IPGJFET (implanted gates). Red represents the implanted region (p-type) while green the n-doped
heterostructure.
97
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
5.4.1 n-channel in-plane gate transistors
The I-V characteristics and leakage currents measured at RT for n-channel IPGJFETs
fabricated on n-doped QW heterostructures are presented in Figure 5.21. There are both
similarities and differences between these results and those obtained for n-channel IPGJFETs
fabricated on p-doped QW heterostructures. First of all, the linear region for small drain
voltages is observed. Increasing the drain voltage the current saturates at a certain value.
Afterwards, a further increase of the drain voltage has practically no influence on the current
until the breakdown occurs. This is the most significant difference between these IPGJFETs
and the previously discussed ones. Generally speaking, the increase of the saturation current is
related to some effects not considered in our theoretical models. The constant-like character
of the saturation of n-channel IPGJFETs fabricated on n-doped heterostructures might be
explained by the better quality(*) of the channel. Because the channel is not implanted, the
channel region is a FIB defect-free region for n-doped QW heterostructures, while for the
p-doped ones it is the channel, which is implanted. As it was discussed, the RTA cannot
completely remove all these defects and, therefore a small increase of the saturation currents
can be noticed for n-channel IPGJFETs fabricated on p-doped heterostructures.
Figure 5.21: (a) I-V characteristics and (b) the corresponding leakage currents obtained for an n-type channel
IPGJFET implanted in the geometry presented in Figure 5.20c.
For VG = 0 V the saturation current is approximately 180 µA, which is higher than the
corresponding value measured on n-channel IPGJFETs fabricated on p-doped heterostructures. This can be explained by the higher mobility (μn= 7000 cm2/(Vs) ), and the lower
carrier density (n= 6.0 × 1011 cm-2) of the 2DEG fabricated by MBE in comparison with the
2DEG fabricated by FIB implantation (about μn= 4000 cm2/(Vs) and n= 8.0 × 1011 cm-2). Still
the currents ratio is not given only by the ratio between the products nµn (one should consider
also the geometrical dimensions of the channel) as equations (5.10) and (5.11) suggest,
because the transistors most probably have also different built-in voltages. The channel can be
enhanced (black curve corresponding to VG = 0.5 V), but the leakage current doubles (in
(*)
A less number of defects in the channel
98
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
comparison with that measured for VG = 0 V) because the 2D p-n junctions between drain and
gates are forward biased.
The other leakage currents (for VG < 0 V) are about three orders of magnitude smaller
than the drain currents for almost all investigated drain voltages. However, around 10 V,
which is a relative high value, the breakdown occurs and the leakage currents suddenly
increase. This can be very well noticed for the curves corresponding to VG < -4 V. This
increase of the leakage current is immediately sensed in I-V characteristics(*).
Figure 5.22: The transconductance characteristics (a) and the corresponding drain currents (b) measured in the
saturation regime for an n-type channel IPGJFET implanted in the geometry presented in Figure 5.20c. The
transconductance (c) and the corresponding drain currents (d) measured for very small drain voltages, for the
same IPGJFET in the linear region of I-V characteristics presented in Figure 5.21.
The transconductance measured in both saturation regime and for very small drain
voltages are presented in Figure 5.22. For the saturation regime (VD > 3.0 V) the
transconductances overlap again showing the independent-character of the drain voltage
similar to those presented in Figure 5.16a. A difference appears for small drain voltages, for
which the transconductance has also a linear behavior. This cannot be explained by any
theoretical model presented in this work.
5.4.2 p-channel in-plane gate transistors
The p-type channel IPGJFETs implanted with different geometrical lengths and
widths measured at RT showed bad I-V characteristics, similar to those in Figure 5.23. One
can see that the channel cannot be fully controlled by the gate bias, e.g. it cannot be closed
even with 20 V gate bias. This might be due to the fact that the gate is depleted with the
increase of the VD, i.e. very large depletion regions appear also in both gate regions, not only
in the channel. These depletion regions can make the gates almost completely inefficient
(*)
Note the small increase of the current corresponding to VG= -4 V at roughly VD= 10 V. Here, in fact, the
transistor was somehow “forced” to work just to present the starting point of the breakdown region. A small
increase of the drain voltage can damage irremediably the device, so that any further increased was avoided.
99
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
because in fact the channel is masked by them. Such a situation is illustrated in Figure 5.24. In
spite of the symmetry of the implantation, due to the fact that the source and the drain are at
different potentials, a strong asymmetry of the depletion regions from the gates can be seen.
Figure 5.23: (a) I-V characteristics and (b) the corresponding leakage currents obtained for an n-type channel
IPGJFET implanted in the geometry presented in Figure 5.20b.
Even when the gates 1 and 2 are connected together,
drain and gates is always higher than that between source
(which is grounded) and gates. Consequently, the depletion
region from gate 1 is “pushed” toward the source masking
the channel. One thing, which attests the validity of this
affirmation, is the fact that increasing the gate bias from
15 V to 20 V practically no influence on the drain current
can be noticed and therefore one can say that the channel
does not “feel” any gate bias higher than this value.
A second fact that might account for a channel
screening is the saturation region, which is not well
pronounced, due also probably to overextended depletion
regions in the gates. In order to check if this is the reason
for the impossibility to control the channel via the gate bias,
IPGJFETs with channels having different lengths were
implanted in the range 1-15 μm. No change in the I-V
characteristic shape was found.
5.5
the potential difference between
Figure 5.24: A simple model which
might explain why the channel cannot
be closed for p-channel IPGJFETs.
Yellow represents the overextended
depletion regions.
Different geometries of the channel – comparison
One of the first problems one is confronted with, before starting the device fabrication,
is to find out the optimum geometry for the channel and/or gates in order to obtain the best
performance devices (the highest source-drain currents, the lowest leakage currents, etc.).
This Section treats this problem and three different geometries will be presented and
analyzed.
100
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
Figure 5.25 presents different geometries for the channel showing only the middle
region of the IPG transistor, where the channel is implanted. An “U”-geometry is presented in
Figure 5.25(a), complementary “H”- geometries in Figure 5.25(b) and (d), and
complementary “Z”-geometries in Figure 5.25(c) and (e). The term of complementary refers
to the following aspect: if in the Figure 5.25(b) and (c) the implanted regions, which are
always represented by green-colored areas, are the source, the drain and the channel, in
Figure 5.25(d) and (e), the gates are implanted, so that the channel is defined by two gate
regions very close to each other.
Figure 5.26 presents the results obtained for an n-type channel IPG transistor
implanted in an “U”-geometry on a p-doped heterostructure. The geometrical channel length
channel
and width are Lchannel
= 2 μm, Wgeo
= 2 μm, and the aspect ratio (the ratio between gate and
geo
gate
channel
channel widths) is Wgeo
: Wgeo
= 12 : 1 .
Figure 5.25: Different geometries of the channel: (a) - (c) the implanted regions are the source, the drain and the
channel; (d), (e) the implanted regions corresponds to the gate electrodes. For the implantation (green) with Si 2+
the heterostructure (red) is p-doped and blue represents 2DHG. For Be+ the heterostructure is n-doped and blue
represents 2DEG.
This geometry was designed considering the corresponding one of a conventional IPG
transistor fabricated in negative pattern definition (NPD), for which the channel is defined by
two implanted insulating lines. In positive pattern definition (PPD), the channel is implanted
and the lines are replaced by two regions (not implanted) which play the role of gates. The
implantation dose is 1.39×1013 cm-2. Because the channel of a conventional IPG transistor
fabricated in NPD can be closed using only one gate, one would think that this may also be
valid for a transistor fabricated in PPD. In Figure 5.26(a) the source-drain current as a
function of the source-drain voltage is shown for different gate biases when only the bottom
gate, namely the gate which controls the channel for a conventional IPG transistor fabricated
101
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
in NPD, is connected. One can see not only that the channel cannot be closed down to a gate
bias of -3.60 V, but it is very far from closing, either. When both gates are connected together,
the channel is closed at about -3.0 V gate bias. Of course, when one gate is connected,
because mainly, only one depletion region is controlled by the gate, one would think that the
effective width of the channel is larger than when both gates are connected. Comparing the
curves from Figure 5.26(a) and (b) the saturation current for VG= 0 V is higher in the first
Figure 5.26: I-V characteristics for an n-type, “U”-geometry implanted channel IPGJFET realized on a p-doped
heterostructure when (a) only gate 1 is connected and (b) both gates are connected together.
case, proving that this assumption is perfectly true. However, the difference is too small to
lead to the conclusion that the channel cannot be closed because the gate bias is not
sufficiently high. In fact, the channel could not be closed even with a gate bias of -8.0 V. The
main reason for the impossibility to close the channel is the potential redistribution in the
region of the unconnected gate close to the channel. Another reason is the fact that the current
path moved very close to the junction between the channel and the top gate which is not
connected (Figure 5.27).
The leakage current, which is the inverse current
that flows through the p-n junction between channel and
gate, is about 500 nA with only one gate connected and
becomes double when both gates are connected together.
The “U”-geometry of the channel is the most
favorable geometry to be closed with only one gate. Since
this is not possible, an important conclusion from
Figure 5.26 is that all electrical measurements for the IPG
transistors with different channel geometries must be
performed with both gates connected together.
Figure 5.27: The region close to the
Figure 5.28(a) and (b) present the typical drain- junction between channel and
source current as function of drain-source voltage for unconnected gate due to the
overextension of the depletion
different gate biases for IPGJFETs fabricated on p-doped
region(s) in the gates is not influenced
heterostructures with an n-type implanted channel in “H”- by the gate biases.
and “Z”-geometry, respectively. For a better comparison,
the geometrical dimensions of the channels and the implantation dose for both transistors are
102
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
channel
identical: the length Lchannel
= 4 μm, width Wgeo
= 2 μm and the dose 1.39×1013 cm-2. The
geo
current is almost double for “Z”-geometry, while the gate bias is about only 1.5 times higher,
proving that the gates efficiency is better for “Z”-geometry. This is not surprising, because for
“H”-geometry, the gate regions in the vicinity of the channel have very small dimensions
(given by the channel length and the ratio between source/drain and channel width), which
results in the distribution of the gate bias perpendicular to the channel. Consequently, the real
gate bias, which reaches the channel, is less than the applied one.
Figure 5.28: Comparison between I-V characteristics measured for n-type channel IPGJFETs implanted with
different geometries: (a), (b) IPGJFETs realized by implantation of Si2+ on p-doped heterostructures with “H”and “Z”-geometry, respectively; (c), (d) IPGJFETs realized by implantation of Be + on n-doped heterostructures
with “H”- and “Z”-geometry, respectively.
The leakage currents are remarkably small, for “H”-geometry about 70 nA, and for
“Z”-geometry, even if the current is doubled, the leakage current was only about 50 nA.
In Figure 5.17 was already presented the I-V characteristics for a p-type channel
IPGJFET fabricated on a p-doped heterostructure with a “Z”-geometry defined by two n-type
implanted and conductive regions very close to each other, which play the role of gates. The
geometrical width and length of the channel are 2 µm and 6 µm respectively, and the
implantation dose is 9.83×1013 cm-2. One should note that the drain current is much smaller in
comparison with the measured one for n-type channel IPGJFETs. This difference is most
probably due to the much lower mobility of the holes. Also important is that the channel can
103
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
be closed only applying very high gate biases of about -20 V, similar results being also
reported by Hirayama [6] and, for a similar “H”-geometry by Reuter et al. [9].
A solution to increase the current would be to create a wider geometrical width of the
channel, but a larger width of the channel, in turn, leads to a larger area in which the
depletion region should extend in order to close the channel, and hence to higher gate biases.
At higher gate biases, however, the depletion region also extends in the gate regions, and the
gate dimensions should be considered carefully, so that the depletion region does not “flood”
completely the gates. The latter situation makes it practically impossible to close the channel.
In Figure 5.28(c) and (d) are presented the I-V characteristics for n-type channel
IPGJFETs implanted with “H” and “Z”-geometry respectively. The channels can be
enhanced (the curve corresponding to a positive gate bias) or completely depleted. The
saturation currents are very well defined and the corresponding maximum leakage currents
are of about few hundreds of nanoamperes, i.e. about three orders of magnitude lower.
5.6
The source–drain current dependence
geometrical dimensions of the channel
on
the
The source-drain current dependence on the geometrical width and length of the
channel was investigated by fabrication of different n-type channel IPGJFETs on p-doped
heterostructures. The geometrical width and length of these transistors varied between 1-8 μm
and 1-15 μm, respectively. The results are presented in Figure 5.29(a)-(b).
Figure 5.29: The drain current dependence on: (a) the geometrical width of the channel, (b) the geometrical
length of the channel.
In order to explain the dependence of the saturation current on the geometrical width
and length of the channel we will start from the equation of the saturation current in the
field-dependent mobility model, (5.22):
I
sat
D
=
2 I P (1 - u2m )
z
m
2
where u is the solution of (5.21).
104
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
Substituting u2m in (5.22) the saturation current can be written as:
(
)
1
é
ù
(5.34)
êë1 - u1 - z 2 z - 2u1 z + 1 - 1 úû
where u1 , I P and z are given by (5.7), (5.11) and (5.20), respectively. Replacing all these in
I Dsat =
2I P
z
(5.34) the saturation current can be written as:
é
öù
4e 0e rv s Lgeo æ eN D m 2 DWgeo 2m 2 D
4e 0e r
ê
ç
÷ú
I = eN DWgeov s 1 V
V
+
1
1
(Vbi - VG ) (
)
bi
G
÷ú
eN D m 2 DWgeo ç 2e 0e rv s Lgeo v s Lgeo
ê eN DWgeo
è
øû
ë
(5.35)
However, the behavior of the
saturation current with the geometrical
length of the channel cannot be explained by
the field-dependent mobility model, and
using as fitting parameters the carrier
density, the mobility and the built-in voltage,
no value with a physical meaning can be
found. But, considering the corrections at the
channel length due to the extension of the
depletion region in both source and drain
regions given by (5.24), the experimental
Figure 5.30: Fit (blue curve) of the measured saturation
data can be fitted (Figure 5.30) and a value
current (red dots) as a function of geometrical length of
of about 4.8 μm for the fitting parameter the channel at V = 0V.
G
h1+h2 results using equation (5.35).
A numerical simulation using
equation (5.35) for IPGJFETs with the
geometrical length of 6.0 μm at VG= 0 V is
illustrated in Figure 5.31. It should be
pointed out that these numerical values
found by fitting are only approximate due to
the fact that the saturation current was
measured for different devices and the
carrier density and the mobility as well as
the built-in voltage can be slightly different
from device to device. The extension of the
depletion region in the drain h2 depends on
the drain voltage, so that a more detailed Figure 5.31: Comparison between experimental data
theoretical model should consider also this (red dots) and calculated curve of the saturation current
(blue curve) as function of the geometrical width of the
dependency.
channel at VG= 0V.
Finally, it should be mentioned that
the two-region model is more suitable for GaAs than the field-dependent one, and the
field-dependent carrier mobility, in conjunction with the condition to preserve the current
continuity produces regions of carrier accumulation and depletion within the source-drain
sat
D
105
Chapter 5 - IPG transistors fabricated by FIB implantation in positive pattern definition
channel of the IPGJFET. A similar situation, with that presented for IPG transistors fabricated
by FIB implantation in negative pattern definition (Figure 4.23) occurs and the static dipole,
which forms in the channel, has a strong influence on all electrical characteristics of the
IPGJFET.
106
– Chapter 6 –
Applications of the in-plane gate transistors
6.1
An electron pump realized with two IPG transistors
Introduction
In the last decade there has been a considerable interest especially in the metrological
community to design and develop a device capable to deliver a standard current (in
picoampere range) with an extremely high accuracy. A device that transports electrical charge
from a reservoir at low electrochemical potential to one at the same or higher electrochemical
potential by cyclic modulation of some internal parameters is a charge pump. A device that
transports extremely small quantities of charge, practically a small number of electrons per
cycle, is named electron pump. The Coulomb blockade of electron tunneling in small
junctions, first experimentally demonstrated by Fulton and Dolan [135] made possible
devices, which manipulate individual electrons [136, 137].
Figure 6.1: (a) Circuit diagram of an electron pump with three tunnel junctions having the capacitances C, C’
and C’’, after Pothier [138]. The gates capacitances C1 and C2 are much smaller than the junctions capacitances.
The bias voltage is V, the pumping process is controlled by gate voltages U 1 and U2. (b) A seven-junction
electron pump after Keller [141, 142] with a metrological accuracy: the error per pumped electron is 15×10 -9.
Electron pumps consisting of three [138, 139] and five [140] tunnel junctions based on
the same principle were immediately proposed. A seven-junction electron pump was
fabricated by Keller et al. [141, 142] and consists of a chain of metal islands separated by
107
Chapter 6 – Applications of the in-plane gate transistors
tunnel junctions with a gate electrode capacitively coupled to each island. They used this
device as an electron counter with an error per pumped electron of 15 ppb and a hold time of
600 s. Generally speaking, an electron pump based on Coulomb blockade and single electron
tunneling effects predicted by Averin and Likharev [143] consists in N tunnel junctions,
N ³ 3 and N-1 gates. The dominant factor limiting the pumping accuracy is the process of
electron co-tunneling [144, 145]. This is an uncontrolled process in which the charge is
transferred by simultaneous tunneling in several junctions in one quantum event. The theory
of co-tunneling in N-junctions arrays with resistors has been developed by Odintsov et al.
[146] for N = 2 and generalized by Golubev and Zaikin [147] for N ³ 2 . The rate of
co-tunneling drops exponentially with the number of junctions. This was one of the main
reasons for designing a seven-junction pump. The drawback consists in a very sophisticated
routine for tuning and operating the pump. It is not surprising that the interest did not focus on
such complicated devices. One year after Keller et al. proposed the seven-junction electron
pump, Tsukagoshi and Nakazato [148, 149] continued to study the three-junction electron
pump, the electron packet being transferred by two trapezoidal pulses with phase delay
(Figure 6.2). The dependence on the shape of the pulses and various phase delays were
investigated. A maximum current was observed for a particular phase delay when the
backward tail of the first pulse just overlaps the forward tail of the second pulse. The rate of
co-tunneling was not reported, but later Zorin, Lotkhov and co-workers [150, 151] showed
that even in the case of three junctions the co-tunneling rate can be drastically reduced by
using on-chip high-ohmic resistors.
Another approach to the electron pump
design and fabrication was to consider the
interactions between a 2DEG and a surface
acoustic wave, which were well described in Ref.
[152]. Based on these interactions, Talyanskii et
al. [153-156] fabricated a device, for which the
charge transport through a one-dimensional
channel
formed
in
a
GaAs-AlxGa1-xAs
heterostructure is done using surface acoustic
waves of high frequency (few GHz). The main
advantage is a strong increase of the current,
which extends to the nanoampere range, i.e. three
orders of magnitude higher than the one obtained Figure 6.2: Sketch of a pumping device, which
with the previously discussed devices.
functions by applying two trapezoidal pulses
A fundamentally different theoretical with a phase delay, after Tsukagoshi and
approach was reported by Astumian and Derényi Nakazato [148]. The frequency is 0.5 MHz.
[157] who showed that stochastic modulation
between two configurations of gate and quantum well energies can drive efficient pumping
through a molecular wire (Figure 6.3). They assert that this mechanism can also shed light on
the function of biological electron transport in proteins and a chemically driven electron pump
could play a role in the design of molecular computers [158, 159]. Even more, because the
108
Chapter 6 – Applications of the in-plane gate transistors
nonequilibrium chemical reaction that provides the power can be entropically driven and in
principle can be endothermic, the system could be self-cooling.
Figure 6.3: A comparison between (a) a quantum dotlike device for pumping charged particles
from a left reservoir to a right reservoir by modulating the gate biases V L and VR and the dot
voltage VD; (b) a wire molecule with a quantum well structure similar to the quantum dot, but at a
scale of few angstroms rather than a micron; (c) the corresponding quantum well for the molecular
wire, after Astumian and Derényi [157]. The quantum well is formed due to the interposition of
the σ bonds in the π bonded backbone of the wire. The functional R and R′ can influence the left
gate height and the quantum well level depending on how strongly electron withdrawing or
donating they are.
In this chapter we propose an electron pump with two IPG transistors [160], which
operates at low frequencies (tens of kHz) and is capable to produce a current more than one
order of magnitude higher than other electron pumps based on Coulomb blockade and single
electron tunneling effects.
Pump design and fabrication
The design of the electron pump is
shown in Figure 6.4. Two IPG transistors are
fabricated using FIB technique by
implanting insulating lines with Ga+ ions
with an energy of 100 keV on the same
GaAs-AlxGa1-xAs modulation-doped heterostructure with a 2DEG located at 105 nm
below the sample surface. The drain from
the first transistor is bound to the source of
the second one. The IPG transistors will
work as “valves” of the active region, which
is the small rectangular area from the middle
of the mesa defined by the FIB implanted
lines. The long sides of the rectangle are Figure 6.4: Secondary electron image induced by the
connected to the active gate electrodes. An ion beam of an electron pump fabricated by FIB
+
important requirement is that the FIB implantation of Ga with an energy of 100 keV.
109
Chapter 6 – Applications of the in-plane gate transistors
implanted lines should have extremely good insulating properties. In Figure 4.16 were
presented the typical leakage currents obtained for an IPG transistor at RT. The leakage
currents are in the order of 10 nA, which are too high for our purpose. However, according to
Figure 4.19, the same IPG transistor has at 4.2 K leakage currents smaller than 5 pA for gate
biases smaller than 7.0 V. Consequently, all measurements were performed at 4.2 K. The
active region dimensions are 7 μm × 30 μm and the FIB implanted lines have a width of about
100 nm. The geometrical width of the channel of the IPG transistors varied between 0.8 μm
and 1.2 μm. The Hall measurements at 4.2 K, without illumination revealed a carrier sheet
density in the 2DEG of n = 2.3 × 1011 cm-2. The threshold voltage VT, i.e. the necessary gate
bias to close an IPG transistor, at 4.2 K is relatively small (around -0.5 V for our device). In
order to ensure a firmly closed channel, a value between -1.2 V and -0.8 V was used. The
active gate bias was set between -2 V and -1.3 V, because the depletion regions that extend in
the active region should extend much more than the one necessary to close the first or second
IPG transistor. Since there are two active depletion regions, for an active bias VGA equal with
VG1, their total width is two times larger than the active region corresponding to VG1.
Pump operation
The operation principle of the electron pump presented in Figure 6.5 is based on the
piston-pump operation. If at least one of the IPG transistors is opened, the depletion regions,
which will appear inside the active region, by applying a negative voltage VGA to the
corresponding active electrodes, will “push” a number of electrons from the 2DEG out of the
active region. Practically, the depletion regions will act as active pistons, while the 2DEG is
the “fluid”. If the sequence, in which the IPG transistors – the valves open and close, is
correlated properly with the extensions and contractions of the active depletion regions – the
pistons, a charge is transported from the source S to the drain D, although no external
potential between them is applied. In initial state, both IPG transistors are closed. Then, the
IPG 2 transistor between the active region and drain is opened by removing the negative gate
bias VG2. In the third step, a bias is applied on the active region gates, and the electrons are
“pushed” out of the active region through the channel of the IPG 2 transistor between active
region and drain, which is still opened at this moment. In the next step, the second IPG
transistor is closed. Immediately the first transistor is opened, the active gate bias is removed,
and the electrons are “flowing” into the active region. When the active region is “refilled”, the
IPG 1 transistor closes and the entire cycle repeats itself. Figure 6.5 illustrates the entire cycle
together with the corresponding time dependency of the gate biases, but for simplicity, in the
same figure, every step of the cycle was considered to be 10 μs.
The time sequence of all gate biases is maintained using a controller, the electronic
circuit of this device being presented in Appendix E. This controller was designed to allow
the study of the frequency dependence of the pumped current, the current dependence on any
gate bias and the dependence of the pumped current on different sequences of the gate biases.
110
Chapter 6 – Applications of the in-plane gate transistors
Figure 6.5: Electron pump operation principle: (a) both IPG transistors are closed by applying a voltage equal
with the threshold voltage VT; (b) IPG 2 (“the valve” between the active region and the drain) is opened; (c) the
active gate biases (“the pushing pistons”) VGA are applied and a number of electrons are forced to move in the
drain; (d) IPG 2 is closed; (e) IPG 1 is opened; (f) the active gate biases are removed, while IPG 1 is open, and
the electrons “flow” in the active region; the entire cycle (a)-(f) repeats itself; (1) the equivalent diagram of the
gate biases in time. For simplicity, every step was considered in the graphic to be 10 μs and the respective
voltages are shown in the figure.
111
Chapter 6 – Applications of the in-plane gate transistors
Results and discussion
In this section, an electron pump with a design similar with that presented in
Figure 6.4 will be analyzed. After implantation, the leakage currents, i.e. the currents over the
insulating lines, were measured and it was found that they are below 3 pA for voltages
between -3 V and 3 V for all implanted insulating lines.
The operation sequence for the gate biases described in the previous section is not the
only one, which provides a current. Three different sequences, which deliver a current with
different magnitude, are illustrated in Figure 6.6. The gate bias sequence corresponding to the
Figure 6.6: Three different sequences for the gate biases having as result a charge transport between the source
and the drain. For simplicity, every step was considered in the graphic to be 10 μs, VG1 = VG2 = -1 V and
VGA = -2 V.
cycle illustrated in Figure 6.5, was labeled abcdef. In Sequence 2, labeled abcdaf, the IPG 1
remains closed after step (d), while the active gate bias is removed. Consequently, in the last
step, the electrons “flow” into the active region due to the concentration gradient between the
source and the active region. There is no active “piston” to “absorb” these electrons, therefore
the corresponding current I2, presented in Figure 6.7 is expected to be lower than I1 measured
for abcdef. In Sequence 3, labeled abcdef , the cycle starts with both IPG transistors opened.
The state a refers to the IPG
transistors state, i.e. in the state a both
transistors are closed, while in a both
are opened. The measured current is
higher because the transistors being
opened in state a , the area of the
depletion regions inside the active
region is minimized and a larger
number of electrons is pumped every
cycle. The main disadvantage of this
cycle is that due to the same state a , it
cannot operate as a charge pump
without an external circuit, which
Figure 6.7: The current-frequency dependence corresponding
permits the electrons to return to the
to the gate sequences from Figure 6.6 at VGA= -1.5 V.
source electrode. Figure 6.7 illustrates
the current-frequency dependence at VGA= -1.5 V for all sequences studied. An experimental
112
Chapter 6 – Applications of the in-plane gate transistors
test, was to keep one of the transistors closed during measurements and measure the current.
Indeed, the current was zero for all sequences, when any IPG transistor remains closed. Also,
the current is zero when the active gate bias is zero.
Another interesting aspect is the
current dependence on the active gate
bias. Because the depletion region of a
2D p-n junction depends linearly on
the applied voltage [5, 108-110] for
small active gate biases, one would
expect a linear dependence of the
current. This was experimentally
proved and the results are presented in
Figure 6.8. For very small active gate
biases, all currents are practically zero
having a kind of “threshold” at about
-0.25 V. Then, between -0.25 V and
-1.1 V the currents depend linearly on
Figure 6.8: The current – gate bias dependence corresponding
the gate bias. By further increasing the to the gate sequences from Figure 6.6 at 10 kHz.
gate bias, a saturation occurs probably
due to the fact that the active region is practically flooded by the depletion regions. However,
in this saturation regime the number of electrons “expulsed” from active region increases with
the gate bias and the current increases, too. This increase seems to be also linear, but with a
different slope.
Outlook
To obtain a higher current one
idea is to make a larger active region, the
current being proportional to the number
of electrons “expulsed” in every cycle
from the active region. A proposal for
such a device is illustrated in Figure 6.9.
The drawback is of course the much
more complicated layout, which could
be a possible factor for higher leakage
currents. In addition, long rectangles
force the gate bias to redistribute along
them, so that the real active gate bias is
lower than the applied one, making the
results on this device to be harder to
control and interpret.
Figure 6.9: A proposal for an electron pump with an active
area of roughly 20 times larger than that from Figure 6.4.
113
Chapter 6 – Applications of the in-plane gate transistors
6.2
Logic circuits with in-plane gate transistors
One of the most important applications of the transistors is in the field of logic
circuits. The logic circuits, whose functionality is based on Boolean algebra, fascinated the
mankind over the years, due to the possibility to construct electronic high speed computers.
The idea is that any decimal number can be uniquely written using only two symbols “0” and
“1”. Consequently, a Boolean logical input or output always takes one of two logic levels.
These logic levels can be implemented considering different systems including: on/off,
high/low, one/zero, true/false, positive/negative, positive/ground, open circuit/close circuit,
potential difference/no difference. Using simple logic circuits as NOT, NAND or OR one can
implement practically any complex function. This chapter will present and propose such
simple circuits using IPG transistors.
6.2.1 Inverter fabricated with in-plane gate transistors in negative pattern definition
The most simple, but very important, logic circuit is the inverter. An inverter with IPG
transistors was fabricated and
studied for the first time by
Wiemann et al. [5]. A similar
circuit
is
presented
in
Figure 6.10, except that IPG 2 is
a normally-off transistor. The
only difference consists in using
positive voltages as it will be
discussed in the following. The
first IPG transistor, which is
always open, forms an active
load that controls the current
behavior, keeping it almost
constant. Considering that the
state “0” corresponds to zero
voltage and “1” to a positive one
necessary to open the IPG
transistors, when no gate bias is
applied on the IPG 2 transistor,
the channel of IPG 2 is closed
and,
therefore,
Vout = Vdd .
Consequently, the corresponding Figure 6.10: An inverter with IPG transistors; (a) electric circuit; (b)
logic state is “1”. Applying a perspective view of the implanted inverter; (c) zoomed-in area of the
positive gate bias on transistor 2, implanted region. (Vdd is the power supply voltage).
the channel will open and the output will be practically connected to the ground, i.e. the logic
114
Chapter 6 – Applications of the in-plane gate transistors
state at the output is “0”. If the second transistor were also a normally-on transistor, then a
negative gate bias should be applied in order to close the channel. Because usually the lowest
potential is associated with “0” state, it means the notation is complementary, i.e. “0”
corresponds to an applied gate bias, and “1” to zero voltage. The output voltage as a function
of the input one is illustrated in Figure 6.11.
Figure 6.11: Drain voltage vs. gate voltage of the
inverter, after Wiemann et al. [5].
6.2.2 Logic circuit NOR / AND with IPG transistors implanted with FIB in positive
pattern definition
Another important and interesting logic circuit is NOR one, which is a combination of
OR and NOT. The electrical circuit of such a device with IPG transistors fabricated by FIB
implantation in positive pattern definition is presented in Figure 6.12 and consists of two IPG
transistors connected in parallel. When no bias is applied on any transistor, the output is in the
logic state “1”. Applying a positive bias on either gate of transistor 1 or transistor 2, the output
is connected to the ground, so that the logic state of the output becomes “0”.
Table 6.1 – The truth table of the circuit
from Figure 6.12
Figure 6.12: Electric circuit of a logic circuit NOR with
IPG transistors.
115
Vin1
Vin2
0
0
1
1
0
1
0
1
Vout =Vin1 +Vin2
1
0
0
0
Chapter 6 – Applications of the in-plane gate transistors
A proposal for the FIB implanted device is illustrated in Figure 6.13.
Figure 6.13: A logic circuit NOR with IPG transistors fabricated by FIB implantation in positive pattern
definition; (a) perspective view of the implanted device; (b) zoomed-in area of the implanted region.
It is worth to mention that using the same geometry an AND circuit can also be
realized if the transistors are normally-on and it is considered that the state “0” corresponds to
zero voltage and “1” to the necessary gate bias to close the transistors(*). In this case the
transistors are open when no bias is applied on their gates and Vout is connected to the ground,
i.e. the state “0”. Only by applying a bias on the gates of both transistors 1 and 2, the output
becomes Vout = Vdd , i.e. the logic state ”1”.
Table 6.2 – The truth table of the circuit
from Figure 6.14
Vin1
Vin2
0
0
1
1
0
1
0
1
Vout =Vin1 × Vin2
0
0
0
1
Figure 6.14: Electric circuit of a logic circuit AND with
IPG transistors.
Since the only difference between the normally-on and normally-off IPG transistors is
the geometrical width of the channel, it is possible to fabricate either NOR or AND logic
circuits by controlling only one parameter.
(*)
The gate bias required to close the transistor is negative; the correspondence between the state “1” and the
lower potential is not usual. But in our case the state “1” is associated with the existence of a given gate bias
(which is negative).
116
Chapter 6 – Applications of the in-plane gate transistors
6.2.3 Logic circuit NAND / OR with IPG transistors implanted with FIB in positive
pattern definition
A logic circuit NAND is a combination of NOT and AND logic circuits. The electric
circuit for the device fabricated with IPG transistors is given in Figure 6.15, while the
proposal for the implanted device is shown in Figure 6.16.
Table 6.3 – The truth table of the circuit
from Figure 6.15
Vin1
Vin2
0
0
1
1
0
1
0
1
Vout =Vin1 × Vin2
1
1
1
0
Figure 6.15: Electric circuit of a logic circuit NAND
with IPG transistors.
The output for this circuit Vout = Vdd except the case when a positive bias is applied on
the gates of both transistors. This means that only when both inputs are in the logic state “1”,
the corresponding logic state at the output is “0”.
Figure 6.16: A logic circuit NAND with IPG transistors fabricated by FIB implantation in positive pattern
definition; (a) perspective view of the implanted device; (b) zoomed-in area of the implanted region.
117
Chapter 6 – Applications of the in-plane gate transistors
Considering the aforementioned convention, which associates the logic state “1” to the
existence of a gate bias, and using normally-on IPG transistors, one obtains a logic circuit OR
using the same electric circuit and implantation geometry.
Table 6.4 – The truth table of the circuit
from Figure 6.17
Vin1
Vin2
0
0
1
1
0
1
0
1
Vout =Vin1 × Vin2
0
1
1
1
Figure 6.17: Electric circuit of a logic circuit OR with
IPG transistors.
In conclusion, in spite of the fact that a profound optimization of the implantation
technique for all the devices presented in this chapter should be carefully performed, the IPG
transistors proved their potential for successfully fabricated new devices like the electron
pump or in the very attractive field of logic circuits.
118
Conclusions
The two-dimensional systems embedded in modulation-doped heterostructures are a
very interesting and actual research field. The FIB implantation technique can be successfully
used to fabricate using these heterostructures two-dimensional p-n junctions, i.e. in-plane
junctions between a 2DEG and a 2DHG. Interesting physical properties have been predicted
for 2D p-n junctions like a linear dependence of the depletion region width on the applied
voltage, a high breakdown voltage and an extremely small capacitance value.
Introduced by Wieck and Ploog [1] the IPG transistor fabrication is based on a
standard MODFET structure with a high-mobility 2DEG and using the FIB implantation
technique, one defines the source, the drain, the gate and, therefore the channel, by implanting
insulating lines. The main distinct characteristic of in-plane gate transistors is that the
gate-induced electric field is parallel to 2DEG, the gate being separated from the narrow
conducting channel by an implantation barrier. The gate bias can control the effective width
of the channel and consequently, the drain current. The IPG transistor fabrication, in
comparison with other conventional FETs, is inherently self-aligned, and consequently,
consists of an easy single maskless step process. Considering the aforementioned interesting
properties of the 2D p-n junctions, the IPG transistor is a very promising device for a new
semiconductor technology, since the device functions not only at cryogenic temperature, but
also at RT. The fact that the 2D p-n junction capacitance is extremely small could also be a
starting point to design and fabricate an IPG-based device that would function in ultra- or
even extremely-high frequency regime.
The fabrication method based on FIB-implanted insulating lines is also known as
negative pattern definition. Even if there is no report about IPG transistors fabricated in
negative pattern definition on heterostructures with 2DHG, it is theoretically also possible to
use p-type wafers as starting material. However, depending on the heterostructure doping,
only one type of carriers governs the electrical transport properties of these devices and the
fabrication of both n- and p-type IPG transistors on the same wafer is intrinsically impossible.
Another difficulty to fabricate IPG transistors in negative pattern definition on
heterostructures with a 2DHG consists in the impossibility to obtain high resistive
Ga-implanted regions after heat treatment [12].
A different approach is to start from a semi-insulating substrate, which can be used as
highly resistive region, and to implant both the channel and gate regions. Consequently,
contrary to the negative pattern definition, in which one implants insulating lines in order to
define the quasi-1D channel, in positive pattern definition one implants conductive regions.
Due to the implantation process, which induces defects, the electrical characteristics of the
implanted regions are not too good. It is therefore necessary to perform a rapid thermal
annealing process, immediately after the implantation, in order to heal these defects and repair
the lattice. Also, the optimization of the FIB implantation doses is a very important step for
119
Conclusions
improving further the mobility, and therefore the channel conductivity. The positive pattern
definition proposed by Hirayama [6] was much improved in 2004 by Reuter et al. [9] after
successfully fabrication of 2DEGs by overcompensation doping. According to this technique,
one uses as substrate, for example, p-type GaAs/InyGa1-yAs/AlxGa1-xAs heterostructures and
implants only Si2+. This method opened the possibility of fabrication of two-dimensional
n- and p-type IPG transistors from the same heterostructure [8, 9].
Since the goal of this work is to fabricate IPG transistors in negative and positive
pattern definition, these techniques supposing to implant either insulating lines or areas with a
certain and constant dose, the starting point was to investigate in which conditions the sum of
the discretely implanted Gaussian-shape distributions, permitted experimentally by a FIB
machine, could lead to a constant-like character. Then the IPG transistors were fabricated in
negative pattern definition on two different heterostructures, a normal modulation-doped
heterostructure and a pseudomorphic one. The I-V characteristics were measured and it was
shown that the pseudomorphic heterostructure yields higher saturation currents (approximate
two times higher for the investigated heterostructures) and much lower leakage currents,
about two orders of magnitude lower. In order to explain the electrical characteristics of the
IPG transistor different theoretical models were proposed and analyzed. Considering as
hypotheses that the FIB produces abrupt 2D p-n junctions, and considering in a first
approximation that the depletion region along the insulating line between source and drain is a
perfect rectangle, a constant mobility model is proposed and analyzed starting from the linear
dependence of the depletion region width on the applied bias [5, 108-110]. The high values of
the current obtained using this model by numerical calculations proved that the
field-dependent mobility cannot be neglected. Consequently, a standard dependence of the
drift velocity on the electric field [40] was considered and the implications investigated. The
saturation velocity model, the usually model used for IPG transistors [114, 115] was also
reviewed.
For the first time the negative drain voltage range of the I-V characteristics obtained
for IPG transistors is largely discussed. It was shown that depending on the gate bias, there
are three different situations: for small gate biases the pinch-off of the channel never
produces, but still a kind of saturation is obtained because the current increases slowly in
absolute value for large negative biases mainly due to the field-dependent mobility effect. The
second situation corresponds to a gate bias, for which the pinch-off occurs at the source. In
the third situation for larger gate biases and zero drain voltage, the channel is completely
pinched-off. Decreasing the drain voltage, the depletion region from the drain is decreasing
until its width is the same as the geometrical channel width, then the channel starts to open.
Decreasing further the drain voltage the channel continues to open up until the depletion
region from the drain is completely expulsed into the gate region. The main consequence is
that a threshold voltage is obtained for this situation, which was also experimentally observed.
Then, the depletion and enhancement modes are reviewed in the frame of these models. The
discussion continues with a comparison between the RT and 4.2 K electrical characteristics
(I-V and transconductance characteristics) of an IPG transistor fabricated on pseudomorphic
heterostructure. At RT, it was found that for very small drain voltages, the transconductance
curves are flat curves in comparison with those measured in saturation regime, in good
120
Conclusions
agreement with the predictions of the field-dependent theoretical model. However, in a
zoomed-in plot, these curves have a very slow dependence on the gate bias that cannot be
explained by any of the presented models. The measured maxima depend linearly on the drain
voltage suggesting that, in spite of the gate bias dependence, the correction, which should be
made to the theoretical model, is small. At 4.2 K the I-V characteristics change drastically.
The threshold voltage is shifted to VT = 0 V almost changing the transistor behavior from
normally-on to normally-off. The transconductance curves in saturation regime present two
distinct regions with a linear behavior in both of them, but with different slopes. Probably this
occurs because the gate bias is increased too much in the positive range (enhancement mode)
and the channel cannot be enhanced accordingly. Another reason for a very different behavior
at RT and 4.2 K is the strong temperature-dependent scattering mechanism. At RT the
dominant scattering mechanism is due to the optical phonons and does not depend on the
impurity concentration. Therefore, the RT mobilities in the IPG channel and in the 2DEG of
the MBE heterostructures are similar. At low temperatures, the scattering mechanism is due to
the ionized impurities and therefore, the mobilities in the channel region (very close to the
FIB implanted lines) could be much lower than in the 2DEG that is far away from the
implanted lines/regions. This affirmation is sustained by a numerical simulation, which
proved that the pinch-off voltage that depends linearly on the carrier density is overestimated.
At the end of the Chapter 4, the two-region model is also proposed and discussed.
IPG transistors fabricated in positive pattern definition were also investigated. Starting
again with the simplest model of constant mobility adapted for the geometry of the IPG
implanted in positive pattern definition and continuing with the field-dependent mobility
model, the results obtained experimentally are discussed. For the first time, a formula
analogue to Lehovec-Zuleeg one, which was deduced for junction field-effect transistors, is
calculated for IPGJFETs. Detailed graphical representation of the equation is provided in
Chapter 5. By implanting either the channel or the gate regions the positive pattern definition
technique allows the fabrication of both n- and p-type channel transistors for p- and similar
for n-type heterostructures. Consequently, the fabrication of IPG transistors was divided in
four different cases. For n-channel IPGJFETs obtained on p-doped heterostructures, the I-V
characteristics present well-defined saturation currents, the drain current can be controlled by
the gate bias and the breakdown occurs at very large drain voltages. The leakage currents are
more than three orders of magnitude smaller than the corresponding drain currents. The
transconductance measurements showed the following characteristics: for gate biases lower
than the threshold voltage the transconductance is zero, independent of the drain voltage; for
drain voltages higher than the saturation value, when the 2D p-n junctions between
gates-source and gates-drain are reverse biased, the saturation transconductance is linear when
the channel is open; for the transconductance measured at very small source-drain voltages,
when the IPGJFET works in the linear region of I-V characteristics, flat curves are obtained
and the mean value of these curves is dependent on the applied drain voltage. Again, as for
the IPG implanted in negative pattern definition, a zoomed-in plot shows that these flat curves
are monotonically increasing until a maximum close to zero gate bias, and the position of the
maximum is practically fixed. For p-type channel IPGJFETs the measured drain currents are
two orders or magnitude smaller than for n-type channel transistors and the saturation region
121
Conclusions
is not well defined. Also, the leakage currents are higher, being only about two orders of
magnitude smaller than the corresponding drain currents. The last important remark is that the
channel could be closed only by applying a very high gate bias.
For the first time, IPGJFETs fabricated on n-doped heterostructures are reported. For
n-channel IPGJFETs obtained on n-doped heterostructures, the I-V characteristics are similar
to that obtained on p-doped heterostructures, but the saturation currents have a much better
constant-like character. Practically there is no increase of the saturation current, as was
previously observed for the other aforementioned transistors. This may be associated with the
fact that the channel of these transistors is not implanted, but the gates are. The channel region
is consequently a FIB defect-free region. The leakage currents are about three orders of
magnitude smaller than the corresponding drain currents. Another difference appears for the
transconductances measured at very small drain voltages, which do not present a maximum in
the negative range of the gate bias, i.e. normal working regime (for positive gate biases the
source-gate junctions are forward biased and consequently, in this range the transistor does
not function). For small drain voltages the transconductances seems to linearly increase with
the gate bias, fact that cannot be explained by any discussed theoretical model. The fabricated
p-type channel IPGJFETs showed very bad I-V characteristics. The saturation region can
hardly be seen and the channel could not be closed by applying gate biases up to 20 V.
An ample analysis of different implanted geometries of the IPGJFETs is for the first
time reported. IPGJFETs with the channel implanted in three different geometries were
compared. An “U”-geometry provides the easiest possibility to close the channel with only
one gate, because the channel is situated at one edge of the gates. It is, in fact, the
complementary geometry of the standard IPG implanted with insulating lines, and one would
naturally think that the channel could be controlled with one gate. The measurements proved
that the channel cannot be closed with one gate, due probably to the potential redistribution in
the region of unconnected gate close to the channel, together with the fact that the current path
is shifted toward the unconnected region. Consequently, all electrical measurements were
performed with both gates connected together for all implanted geometries. It was shown that
the “Z”-geometry provided the highest saturation drain currents for n-type channel IPGFETs
implanted on p-doped heterostructures. However, the constant-like character of the saturation
currents of n-channel IPGJFETs implanted on n-doped heterostructures could determine one
to use these transistors, if the selection criterion was the behavior of the current in the
saturation regime.
The drain current dependence on the geometrical dimensions of the channel was also
investigated, this being a test of the models. The fitting shows that as in the case of IPG
transistors fabricated in negative pattern definition, the length of the channel is dependent on
the drain voltage and this thing cannot be neglected. A two-region model could be a good
solution, but the subject remains open, waiting for eventually a more detailed model to be
proposed.
The last chapter is dedicated to IPG transistor applications. For the first time an
electron pump with two in-plane gate transistors is proposed and fabricated. The electron
pump was measured in three different working regimes. Thus three different gate biases
sequences were considered. The measured currents have a linear dependence on the frequency
122
Conclusions
of the applied gate sequence. A linear dependence on the active gate bias is also measured for
low active gate biases. Increasing further the active gate bias in absolute value a kind of
saturation occurs probably due to the fact that the active region is practically flooded by the
depletion regions. However, the currents still increase linearly, but with a different slope.
Different logic circuits with IPG transistors either in negative or in positive pattern
definition are proposed. The theme remains also open in this field since the fabrication and
optimization of logic circuits was always an attractive subject for electronics.
123
Appendix A - Fundamental physical constants
Name
Atomic Mass Unit
Avogadro's Number
Bohr Magneton
Bohr Radius
Boltzmann's Constant
Compton Wavelength
Deuteron Mass
Electric Constant
Electron Mass
Electron-Volt
Elementary Charge
Faraday Constant
Fine Structure Constant
Hartree Energy
Hydrogen Ground State
Josephson Constant
Magnetic Constant
Molar Gas Constant
Natural Unit of Action
Newtonian Constant of Gravitation
Neutron Mass
Nuclear Magneton
Planck Constant
Planck Length
Planck Mass
Planck Time
Proton Mass
Rydberg Constant
Stefan Boltzmann Constant
Speed of Light in Vacuum
Thompson Cross Section
Wien Displacement Law Constant
Symbol
mu
NA
μB
ao
k
λc
md
εo
me
eV
e
F
α
Eh
Kj
μo
R
h
G
mn
μn
h
lp
mp
tp
mP
RH
σ
c
σe
b
Value(*)
1.66053873(13) × 10-27 kg
6.02214199(47) × 1023 mol-1
9.27400899(37) × 10-24 J T-1
0.5291772083(19) × 10-10 m
1.3806503(24) × 10-23 J K-1
2.426310215(18) × 10-12 m
3.34358309(26) × 10-27 kg
8.854187817 × 10-12 F m-1
9.10938188(72) × 10-31 kg
1.602176462(63) × 10-19 J
1.602176462(63) × 10-19 C
9.64853415(39) × 104 C mol-1
7.297352533(27) × 10-3
4.35974381(34) × 10-18 J
13.6057 eV
4.83597898(19) × 1014 Hz V-1
4π × 10-7
8.314472(15) J K-1 mol-1
1.054571596(82) × 10-34 J s
6.673(10) × 10-11 m3 kg-1 s-2
1.67492716(13) × 10-27 kg
5.05078317(20) × 10-27 J T-1
6.62606876(52) × 10-34 J s
1.6160(12) × 10-35 m
2.1767(16) × 10-8 kg
5.3906(40) × 10-44 s
1.67262158(13) × 10-27 kg
10 9.73731568549(83) × 105 m-1
5.670400(40) × 10-8 W m-2 K-4
2.99792458 × 108 m s-1
0.665245854(15) × 10-28 m2
2.8977686(51) × 10-3 m K
Source:
CODATA Recommended Values of the Fundamental Physical Constants: 2005 by Peter J.
Mohr and Barry N. Taylor, National Institute of standards and Technology, Gaithersburg,
Maryland 20899-8401 USA [161].
(*)
Values given in brackets are not exact. The uncertainty and other details can be found in [161].
124
Appendix B – The mask layouts
Photolithography mask used for IPG transistors fabricated in negative pattern definition
Photolithography mask for mesa structures with 8 contacts.
125
Appendix B
Photolithography masks used for IPG transistors implanted in positive pattern definition
126
Appendix B
Photolithography masks used for AND / NOR logic circuits fabricated with IPG transistors
implanted in positive pattern definition
127
Appendix B
Photolithography masks used for OR / NAND logic circuits fabricated with IPG transistors
implanted in positive pattern definition
128
Appendix C – The samples processing
The processing steps for IPG transistors fabricated in positive
pattern definition
MBE
n-type contacts
alloying (400 °C)
Photolithography
for p-type contacts
p-type contacts
evaporation
FIB implantation
n-type contacts
evaporation
Bonding
p-type contacts
alloying (385 °C)
RTA
(750 °C, 30s)
Photolithography
for n-type contacts
Photolithography
for mesa
Mesa etching
MBE
Photolithography
for n-type contacts
n-type contacts
evaporation
Bonding
Photolithography
for mesa
Mesa etching
n-type contacts
alloying (400 °C)
FIB implantation
The processing steps for IPG transistors fabricated in negative
pattern definition
129
Appendix D – Different types of FETs
Type
Electrical
symbol
Cross section
n-channel
enhancement
(normally-off)
n-channel
depletion
(normally-on)
p-channel
enhancement
(normally-off)
p-channel
depletion
(normally-on)
130
Output
characteristics
Transfer
characteristics
Appendix E – The electron pump gate controller
131
Appendix F – Physical parameters of AlxGa1-xAs
Basic Parameters at 300 K
Crystal structure
Group of symmetry
Number of atoms in 1 cm3
Debye temperature [K]
Density [g·cm-3]
Dielectric constant (static)
Dielectric constant (high frequency)
Effective electron mass me
Density-of-states electron mass mcd
Conductivity effective mass mcc
Effective hole masses mh
Effective hole masses mlp
Electron affinity
Zinc Blende
Td2-F43m
(4.42-0.17x)·1022
370+54x+22x2
5.32-1.56x
12.90-2.84x
10.89-2.73x
0.063+0.083x mo (x<0.45)
0.85-0.14x mo (x>0.45)
0.26 mo (x>0.45)
0.51+0.25x mo
0.082+0.068x mo
4.07-1.1x eV (x<0.45)
3.64-0.14x eV (x>0.45)
5.6533+0.0078x
36.25+1.83x+17.12x2-5.11x3
n=3.3-0.53x+0.09x2
Lattice constant [Å]
Optical phonon energy [meV]
Optical refractive index
Band structure and carrier concentration
Energy gap [eV]
x<0.45
1.424+1.247x
x>0.45
1.9+0.125x+0.143x2
Energy separation (EΓL) between Γ and L
0.29
valleys [eV]
Energy separation (EΓ) between Γ and top
1.424+1.155x+0.37x2
of valence band [eV]
Energy separation (EX) between X-valley
1.9+0.124x+0.144x2
and top of valence band [eV]
Energy separation (EL) between L-valley
1.71+0.69x
and top of valence band [eV]
Energy spin-orbital splitting [eV]
0.34-0.04x
-3
Intrinsic carrier concentration [cm ]
x=0.1
2.1·105
x=0.3
2.1·103
x=0.5
2.5·102
x=0.8
4.3·101
Intrinsic resistivity [Ω·cm]
x=0.1
4·109
x=0.3
1·1012
x=0.5
1·1014
x=0.8
5·1014
Effective conduction band density of
x<0.41 2.5·1019·(0.063+0.083x)3/2
states [cm-3]
x>0.45 2.5·1019·(0.85-0.14x)3/2
Effective valence band density of states
2.5·1019·(0.51+0.25x)3/2
[cm-3]
132
Appendix F
Temperature dependences
x<0.41
Nc=4.82·1015·(mΓ/mo)3/2·T3/2=4.82·1015·T3/2·(0.063+0.083x)3/2
Effective density of states
in the conduction band Nc
x>0.41
[cm-3]
Nc=4.82·1015·(mcd/mo)3/2·T3/2= 4.82·1015·T3/2·(0.85-0.14x)3/2
where mcd is effective mass of the density of states;
Effective density of states in
Nv = 4.82·1015·T3/2·(0.51+0.25x)3/2
the valence band Nv [cm-3]
Band Discontinuities at AlxGa1-xAs/GaAs Heterointerface
Valence band discontinuity [eV]
ΔEv = - 0.46x
Conduction band discontinuity [eV]
x<0.41
ΔEc = 0.79x
x>0.41
ΔEc = 0.475-0.335x+0.143x2
Electrical properties - Basic Parameters
Breakdown field [V/cm]
≈(4÷6) ·105
Diffusion coefficient electrons [cm2/s]
0<x<0.45
200-550x+250x2 cm2/s
0.45<x<1
-6.4+29x-18x2 cm2/s
2
2
Diffusion coefficient holes [cm /s]
9.2-24x+18.5x
Electron thermal velocity [m/s]
0<x<0.4
(4.4-2.1x)·105
0.45<x<1
2.3·105
Hole thermal velocity [m/s]
(1.8-0.5x)·105
Mobility and Hall Effect
For weakly doped AlxGa1-xAs at 300 K
0<x<0.45
µH=-8000 - 22000x + 10000x2
2 -1 -1
electron Hall mobility [cm ·V ·s ]
0.45<x<1
µH=-255 + 1160x - 720x2
For weakly doped AlxGa1-xAs at 300 K hole
µH= -370 - 970x + 740x2
Hall mobility [cm2·V-1·s-1]
Impact Ionization
Parametrizations of the electron and hole ionization coefficients. T=300 K
(
)
(
)
m
m
For electrons a i = a 0 exp é - Fn0 F ù
For holes
bi = b 0 exp é - Fp0 F ù
êë
úû
êë
úû
-1
-1
-1
-1
αo (cm )
Fno (V cm )
m
βo (cm )
Fpo (V cm )
M
x
x
5
5
5
5
0.1
1.81·10
6.31·10
2.0
0.1
3.05·10
7.22·10
1.9
0.2
1.09·106
1.37·106
1.3
0.2
6.45·105
1.11·106
1.5
0.3
2.21·105
7.64·105
2.0
0.3
2.791·105
8.47·105
1.9
0.4
1.74·107
3.39·106
1.0
0.4
3.06·106
2.07·106
1.2
Breakdown voltage and breakdown field of n-GaAs/p-Al0.3Ga0.7As at T=300 K
Na=1014 cm-3
Vi=2.8 kV
Ei=2.8·105 V cm-1
Na=1016 cm-3
Vi=70 V
Ei=4.5·105 V cm-1
Recombination Parameter
Radiative recombination coefficient at 300K ~ 1.8·10-10 cm3/s
Auger coefficient at T=300 K
Cn [cm6/s] (for n-doped samples)
Cp [cm6/s] ( for p-doped samples)
x
0.0
1.9·10-31
12·10-31
0.1
1.2·10-31
8.5·10-31
0.2
0.7·10-31
6.1·10-31
133
Appendix F
Surface and interface recombination velocities in GaAs and AlxGa1-xAs
S (cm/s)
x
0
4·105
free surface
0
45
interface between GaAs/Al0.3Ga0.7As
0
450±100
interface between GaAs/Al0.5Ga0.5As p-type
0.08
4·105
free surface
4
0.08÷0.18
~3·10
interface between AlxGa1-xAs/Al0.88Ga0.22As undoped
0.28
4200
interface between AlxGa1-xAs/Al0.5Ga0.5As undoped
Thermal properties
Bulk modulus [dyn cm-2]
(7.55+0.26x)·1011
Melting point [°C]
1240-58x+558x2 (solidus curve)
1240+1082x+582x2 (liquidus curve)
Specific heat [J g-1°C -1]
0.33+0.12x
-1
-1
Thermal conductivity [W cm °C ]
0.55-2.12x+2.48x2
Thermal diffusivity [cm2s-1]
0.31-1.23x+1.462
-1
Thermal expansion, linear [°C ]
(5.73-0.53x)·10-6
Approximate formula for the lattice thermal
Rth=2.27+28.83x-30x2
resistivity [cm·W-1]
Mechanical properties, elastic constants, lattice vibrations
Hardness on the Mohs scale
~5
Cleavage plane
{110}
Piezoelectric constant
e14= -0.16-0.065x C m-2
C11=(11.88+0.14x)·1011
2
Elastic constants at 300 K [dyn/cm ]
C12=(5.38+0.32x)·1011
C44=(5.94-0.05x)·1011
Anisotropy factor
A=0.55-0.01x
Shear modulus [dyn/cm2]
C'=(3.25-0.09x)·1011
2
[100] Young's modulus [dyn/cm ]
Yo=(8.53-0.18x)·1011
[100] Poisson ratio
σo=(0.31+0.1x)
Acoustic Wave Speeds
Wave propagation
Wave
Wave speed formula
Wave speed [105 cm/s]
Direction
character
VL
(C11/ρ )1/2
4.73+0.68x+0.24x2
[100]
VT
(C44/ρ )1/2
3.34+0.46x+0.16x2
1/2
Vl
[(C11+C12+2C44)/2ρ ]
5.24+0.78x+0.24x2
Vt||
Vt||=VT=(C44/ρ)1/2
3.34+0.46x+0.16x2
[110]
1/2
[(C11-C12)/2ρ]
2.47+0.33x+0.10x2
Vt ^
Vl'
[(C11+2C12+4C44)/3ρ]1/2
5.40+0.79x+0.26x2
[111]
1/2
Vt'
[(C11-C12+C44)/3ρ]
2.79+0.38x+0.12x2
Source: M. Levinstein, S. Rumyantsev, M. Shur [162].
134
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Acknowledgements
Now, at the end of this work, looking back in time and remembering the moments
since I started until the present, I feel deeply indebted to thank to all those persons, who
helped me in one way or another to accomplish my goal.
First of all, I would like to thank to Prof. Dr. Andreas D. Wieck who gave me the
opportunity to work in a very interesting field of semiconductor physics. His door was always
open for discussions and his scientific advises significantly contributed to the progress of my
work during the last three years. Having access to a modern equipment, and it is probably
sufficient to mention only the MBE and not less than six different focused ion beam
machines, I am proud I could work in one of the best groups. It is Prof. Wieck’s merit for this
infrastructure and I thank him for the kind reception in his group.
Special thanks to Dr. Dorina Diaconescu for the introduction into the FIB technique,
for many fruitful high-level scientific discussions and for her guidance during the entire
period we work together. Now, I could say that Dorina was the guide I needed most, at that
moment, and I am glad she was “there”. I also thank to Dorina for her friendship and support
as well as for the wonderful moments spent in her companion in Bochum.
I am grateful to Prof. Dr. Michael-Karl Sostarich for kindly agree to be co-referee of
my thesis, for discussions and deep corrections, which helped me to bring out the best of this
project.
I thank to Dr. Dirk Reuter for many useful hints during the work and for the
high-quality and professionally-grown MBE heterostructures, which this entire work is based
on. Once, I remember that asking him to grow a heterostructure, he grew not less than four,
optimizing the growth parameters until the electrical measurements were the best. It was a
reassuring thought for me that the heterostructures were provided by him.
I am also thankful to Dr. Alexander Melnikov for his permanent help at focusing
technique during the FIB implantation. I have also learnt many practical things from Dr.
Melnikov that helped me a lot during all experiments.
I thank to Rolf Wernhardt for many enlighten discussions about different
measurement-techniques. These discussions were always a high-quality source of learning.
I thank to Georg Kortenbruck for all his help and technical support whenever I need it.
Special thanks to Daniel Salloch for his introduction to electronics and providing me
the first gate controller for the electron pump. His suggestions in electronics helped me to
build the final gate controller presented in this work. I also thank to Michael Kalthoff for
many different useful ideas to build or to improve the gate controller and for the time spent to
debug the electronic circuit of this device.
For deep corrections and many useful suggestions, which improved the quality of this
work special thanks to: Dr. Domocos Kovacs, Fang-Yuh Lo and Dr. Aurel Sălăbaş. I also
146
Acknowledgements
thank for corrections to Răzvan Roescu and Minisha Mehta. I am thankful to Mirja Richter
for the german translation of the conclusions section.
During this three years period, working together and discussing different aspects of the
FIB implantation technique with Dr. Christof Riedesel, Dr. Peter Kailuweit and Dr. Sinan
Ünlübayir it was a great opportunity to learn or improve my knowledge. I thank them not only
for this, but also for their friendship during this period.
I have also appreciated all the time the friendship of Safak Gök and Arne Ludwig.
I thank to Nadine Viteritti for the introduction to the sample preparation and to
Christian Werner for the scientific hints given at different moments.
I thank to Carmen Rockensüß, Regina Lehnart and all members of AFP group for the
memorable moments we spent together in Bochum.
I am grateful to the Deutsche Forschungsgemeinschaft for the financial support within
the framework of Graduiertenkolleg 384.
I bear with pleasure in my memory, a lot of scientific discussions with Res. Prof. Dr.
Magdalena Lidia Ciurea and Dr. Vladimir Iancu, which sometimes transformed into deep
scientific disputes. Many times, I was wrong, but I have learnt every time new things. I thank
them also for the very useful suggestions and corrections of this work and for their valuable
friendship. I thank to Prof. Dr. George Filoti for his support and encouragement to come to
Bochum and many helpful suggestions provided along these years.
I would like to express my sincere thanks to Dr. Victorina Poenariu and Dr. Sorin
Poenariu who helped me from the very moment when I came in Bochum, and were probably
the closest friends I had in this period. The impossible to forget moments spent in the short
trip in Denmark, as well as in other wonderful places, made our friendship to be unbreakable
and I am thankful for having such a nice companion all this time.
I also thank to all my friends in Romania, who have always been enthusiastically
interested in my scientific work in spite of the fact that they did not exactly understand what I
am doing. However, their moral support was remarkable and I greatly appreciate it.
My warmest thanks go to my wife who filled my soil with light and courage to step
forward when I couldn't see the path from the front of my eyes. I also thank to Clari for being
always beside me, for her active support and understanding for many “stolen” hours, which I
had to spend in the lab. I also thank to my wife’s parents for the constant love and
encouragement during these years.
Finally, the last but not the least, I would like to express my appreciation and gratitude
to my parents, grandparents and my brother for the continuous support before and during this
work. I am also aware that their blessings have carried me so far.
147
Curriculum Vitae
Name:
Born:
Place:
Mihai Drăghici
March, 3rd , 1975
Bucharest, Romania
09.1981 – 06.1989
09.1989 – 06.1993
10.1993 – 06.1998
Primary-school
High-school
University of Bucharest, Faculty of Physics,
Diploma thesis title: “Electrical transport
phenomena in fresh, nanocrystalline porous
silicon films”.
Master of Science at University of Bucharest,
Faculty of Physics, Chair for Solid State Physics
Master thesis title: “Trapping levels in fresh and
aged nanocrystalline porous silicon films”.
Scientific Researcher at National Institute of
Materials Physics (NIMP-Bucharest, Romania)
Laboratory: Low Dimensional Systems
Headed by Res. Prof. Dr. M. L. Ciurea
Ph.D. student at Ruhr-University Bochum,
Faculty of Physics, Chair for Solid State Physics
(Lehrstuhl für Angewandte Festkörperphysik)
Headed by Prof. Dr. Andreas D. Wieck
10.1998 – 06.1999
09.1998 – 08.2003
Since 01.09.2003
148