Download Introducción a los Circuitos Digitales - fc

Dra. Ruth M. Aguilar Ponce
Otoño 2008
Fall 2008
1
Moore’s Law
l
In 1965, Gordon Moore noted that the
number of transistors on a chip doubled
every 18 to 24 months.
l
He made a prediction that
semiconductor technology will double
its effectiveness every 18 months
Fall 2008
2
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG2 OF THE NUMBER OF
COMPONENTS PER INTEGRATED FUNCTION
Moore’s Law
Fall 2008
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics, April 19, 1965.
3
Evolution in Complexity
Fall 2008
4
Transistor Counts
1 Billion
Transistors
K
1,000,000
100,000
10,000
1,000
i486
i386
80286
100
10
Pentium® III
Pentium® II
Pentium® Pro
Pentium®
8086
Source: Intel
1
1975
1980
1985 1990
1995 2000
2005 2010
Projected
Fall 2008
Courtesy, Intel
5
Moore’s law in Microprocessors
Transistors (MT)
1000
100
2X growth in 1.96 years!
10
486
1
P6
Pentium® proc
386
286
0.1
8086
8085on Lead
Transistors
Microprocessors double every 2 years
0.01
0.001
1970
Fall 2008
8080
8008
4004
1980
1990
Year
Courtesy, Intel
2000
2010
6
Die Size Growth
Die size (mm)
100
10
8080
8008
4004
1
1970
8086
8085
1980
286
386
P6
Pentium
® proc
486
~7% growth per year
~2X growth in 10 years
1990
Year
2000
2010
Die size grows by 14% to satisfy Moore’s Law
Fall 2008
Courtesy, Intel
7
Frequency
Frequency (Mhz)
10000
Doubles every
2 years
1000
100
486
10
8085
1
0.1
1970
8086 286
P6
Pentium ® proc
386
8080
8008
4004
1980
1990
Year
2000
2010
Lead Microprocessors frequency doubles every 2 years
Fall 2008
Courtesy, Intel
8
Power Dissipation
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Lead Microprocessors power continues to increase
Fall 2008
Courtesy, Intel
9
Power will be a major problem
100000
18KW
5KW
1.5KW
500W
Power (Watts)
10000
1000
Pentium® proc
100
286
486
8086
10
386
8085
8080
8008
1 4004
0.1
1971
1974
1978
1985 1992
Year
2000 2004 2008
Power delivery and dissipation will be prohibitive
Fall 2008
Courtesy, Intel
10
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
Hot Plate
10 4004
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
Year
2010
Power density too high to keep junctions at low temp
Fall 2008
Courtesy, Intel
11
Not Only Microprocessors
Cell
Phone
Small
Signal RF
Digital Cellular Market
(Phones Shipped)
Year
Units
1996
48M
1997
86M
1998
162M
Power
Managemen
t
1999
260M
2000
435M
(data from Texas Instruments)
Fall 2008
Power
RF
Analog
Baseband
Digital Baseband
(DSP + MCU)
12
Challenges in Digital Design
 DSM
 1/DSM
“Macroscopic Issues”
“Microscopic Problems”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
?
Fall 2008
…and There’s a Lot of Them!
13
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10,00010
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
x
1
1,000
21%/Yr. compound
Productivity growth rate
x
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Source: Sematech
Complexity outpaces design productivity
Fall 2008
Courtesy, ITRS Roadmap
14
Why Scaling?
 Technology shrinks by 0.7/generation
 With every generation can integrate 2x more
functions per chip; chip cost does not increase
significantly
 Cost of a function decreases by 2x
 But …
 How to design chips with more and more functions?
 Design engineering population does not double every
two years…
 Hence, a need for more efficient design methods
 Exploit different levels of abstraction
Fall 2008
15
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
Fall 2008
D
n+
16
Design Metrics
 How to evaluate performance of a digital circuit
(gate, block, …)?
 Cost
 Reliability
 Scalability
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function
Fall 2008
17
Introduction to VLSI-CMOS
 Integrated circuits: many transistors on one chip.
 Very Large Scale Integration (VLSI): very many
 Complementary Metal Oxide Semiconductor
 Fast, cheap, low power transistors
 Today: How to build your own simple CMOS chip
 CMOS transistors
 Building logic gates from transistors
 Transistor layout and fabrication
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18
Silicon Lattice
 Transistors are built
on a silicon
substrate
 Silicon is a Group IV
material
 Forms crystal lattice
with bonds to four
neighbors
Fall 2008
Si
Si
Si
Si
Si
Si
Si
Si
Si
19
Dopants
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)
Fall 2008
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
+
-
Si
Si
Si
20
p-n Junctions
 A junction
between p-type
and n-type
semiconductor
forms a diode.
 Current flows
only in one
direction
Fall 2008
p-type
n-type
anode
cathode
21
nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
 Gate and body are conductors
 SiO2 (oxide) is a very good insulator
 Called metal – oxide – semiconductor (MOS) capacitor
Source
Gate
Drain
 Even though gate is
Polysilicon
no longer made of metal
SiO2
n+
n+
p
Fall 2008
bulk Si
22
nMOS Operation
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body diodes are OFF
 No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
Fall 2008
D
bulk Si
23
nMOS Operation Cont.
 When the gate is at a high voltage:
 Positive charge on gate of MOS capacitor
 Negative charge attracted to body
 Inverts a channel under gate to n-type
 Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
Fall 2008
D
bulk Si
24
pMOS Transistor
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
Fall 2008
bulk Si
25
Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Fall 2008
26
Transistors as Switches
 We can view MOS transistors as electrically controlled
switches
 Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
Fall 2008
g=0
s
s
27
CMOS Inverter
A
VDD
Y
0
1
A
A
Y
Y
GND
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28
CMOS Inverter
A
VDD
Y
0
1
OFF
0
A=1
Y=0
ON
A
Y
GND
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29
CMOS Inverter
A
Y
0
1
1
0
VDD
ON
A=0
Y=1
OFF
A
Y
GND
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30
CMOS NAND Gate
A
B
0
0
0
1
1
0
1
1
Y
Y
A
B
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31
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
0
1
1
Fall 2008
ON
ON
Y=1
A=0
B=0
OFF
OFF
32
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
Fall 2008
OFF
ON
Y=1
A=0
B=1
OFF
ON
33
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
Fall 2008
ON
A=1
B=0
OFF
Y=1
ON
OFF
34
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
Fall 2008
OFF
A=1
B=1
OFF
Y=0
ON
ON
35
CMOS NOR Gate
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
Fall 2008
A
B
Y
36
3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0
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37
3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0
Y
A
B
C
Fall 2008
38
CMOS Gate Design
 Activity:
 Sketch a 4-input CMOS NAND gate
Fall 2008
39
CMOS Gate Design
 Activity:
 Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
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40
Complementary CMOS
 Complementary CMOS logic gates
 nMOS pull-down network
 pMOS pull-up network
 a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF Z (float)
1
Pull-down ON
X (crowbar)
Fall 2008
0
pMOS
pull-up
network
inputs
output
nMOS
pull-down
network
41
Series and Parallel
a
a
0
g1
 nMOS: 1 = ON
 pMOS: 0 = ON
g2
(a)
 Parallel: either can be ON
(b)
a
g1
g2
(c)
a
g1
g2
b
(d)
Fall 2008
0
1
b
b
OFF
OFF
OFF
ON
a
a
a
a
0
1
1
1
0
1
b
b
b
b
ON
OFF
OFF
OFF
a
a
a
a
0
0
b
1
b
0
b
1
1
0
g2
a
b
a
g1
a
0
0
b
 Series: both must be ON
a
0
1
1
0
1
1
b
b
b
b
OFF
ON
ON
ON
a
a
a
a
0
0
0
1
1
0
1
1
b
b
b
b
ON
ON
ON
OFF
42
Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
 Series nMOS: Y=0 when both inputs are 1
 Thus Y=1 when either input is 0
 Requires parallel pMOS
A
Y
B
 Rule of Conduction Complements
 Pull-up network is complement of pull-down
 Parallel -> series, series -> parallel
Fall 2008
43
Compound Gates
 Compound gates can do any inverting function
 Ex: Y  A  B  C  D
A
C
A
C
B
D
B
D
(a)
A
(b)
B C
D
(c)
C
D
A
B
(d)
C
D
A
B
A
B
C
D
Y
A
C
B
D
Y
(f)
(e)
Fall 2008
44
Example: O3AI

Y   A  B  C  D
Fall 2008
45
Example: O3AI

Y   A  B  C  D
A
B
C
D
Y
D
A
Fall 2008
B
C
46
Signal Strength
 Strength of signal
 How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
 But degraded or weak 1
 pMOS pass strong 1
 But degraded or weak 0
 Thus nMOS are best for pull-down network
Fall 2008
47
Pass Transistors
 Transistors can be used as switches
g
s
d
g
s
Fall 2008
d
48
Pass Transistors
 Transistors can be used as switches
g=0
g
s
d
s
d
Input g = 1 Output
0
strong 0
g=1
s
d
g=0
g
s
s
g=1
Input
d
d
g=1
s
Fall 2008
1
d
degraded 1
g=0
0
Output
degraded 0
g=0
strong 1
49
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Fall 2008
50
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
a
b
gb
Fall 2008
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
g
a
g
b
gb
Output
a
b
gb
51
Tristates
 Tristate buffer produces Z when not enabled
EN
A
0
0
0
1
1
0
1
1
EN
Y
Y
A
EN
Y
A
EN
Fall 2008
52
Tristates
 Tristate buffer produces Z when not enabled
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
EN
Y
A
EN
Y
A
EN
Fall 2008
53
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
 Only two transistors
 But nonrestoring

Noise on A is passed on to Y
EN
A
Y
EN
Fall 2008
54
Tristate Inverter
 Tristate inverter produces restored output
 Violates conduction complement rule
 Because we want a Z output
A
EN
Y
EN
Fall 2008
55
Tristate Inverter
 Tristate inverter produces restored output
 Violates conduction complement rule
 Because we want a Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
Fall 2008
56
Multiplexers
 2:1 multiplexer chooses between two inputs
S
S
D1
D0
0
X
0
0
X
1
1
0
X
1
1
X
Fall 2008
Y
D0
0
Y
D1
1
57
Multiplexers
 2:1 multiplexer chooses between two inputs
S
S
D1
D0
Y
0
X
0
0
0
X
1
1
1
0
X
0
1
1
X
1
Fall 2008
D0
0
Y
D1
1
58
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed?
Fall 2008
59
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed? 20
D1
S
D0
D1
S
D0
Fall 2008
Y
4
2
4
2
4
2
Y
2
60
Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
Fall 2008
61
Transmission Gate Mux
 Nonrestoring mux uses two transmission gates
S
 Only 4 transistors
D0
Y
S
D1
S
Fall 2008
62
Inverting Mux
 Inverting multiplexer
 Use compound AOI22
 Or pair of tristate inverters
 Essentially the same thing
 Noninverting multiplexer adds an inverter
D0
S
S
D1
D0
D1
S
S
Y
S
S
S
Y
S
D0
Y
S
D1
Fall 2008
0
1
63
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
Fall 2008
64
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two selects
 Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
 Or four tristates
D0
S0
D0
0
D1
1
S1
D1
0
Y
Y
D2
0
D3
1
1
D2
D3
Fall 2008
65
D Latch
 When CLK = 1, latch is transparent
 D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
 Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive latch
D
Fall 2008
Latch
CLK
CLK
D
Q
Q
66
D Latch Design
 Multiplexer chooses D or old Q
CLK
D
1
CLK
Q
Q
Q
D
Q
0
CLK
CLK
CLK
Fall 2008
67
D Latch Operation
Q
Q
D
CLK = 1
Q
D
Q
CLK = 0
CLK
D
Q
Fall 2008
68
D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop
CLK
CLK
D
Flop
D
Q
Q
Fall 2008
69
D Flip-flop Design
 Built from master and slave D latches
CLK
CLK
CLK
QM
D
CLK
QM
Latch
D
Latch
CLK
CLK
CLK
CLK
Q
CLK
Fall 2008
Q
CLK
70
D Flip-flop Operation
D
QM
Q
CLK = 0
D
QM
Q
CLK = 1
CLK
D
Q
Fall 2008
71
Race Condition
 Back-to-back flops can malfunction from clock skew
 Second flip-flop fires late
 Sees first flip-flop change and captures its result
 Called hold-time failure or race condition
CLK1
CLK2
Q1
Flop
D
Flop
CLK1
CLK2
Q2
Q1
Q2
Fall 2008
72
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
 As long as nonoverlap exceeds clock skew
 We will use them in this class for safe design
 Industry manages skew more carefully instead
2
1
QM
D
2
2
2
Q
1
1
1
1
2
Fall 2008
73
Gate Layout
 Layout can be very time consuming
 Design gates to fit together nicely
 Build a library of standard cells
 Standard cell design methodology
 VDD and GND should abut (standard height)
 Adjacent gates should satisfy design rules
 nMOS at bottom and pMOS at top
 All gates include well and substrate contacts
Fall 2008
74
Example: Inverter
Fall 2008
75
Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32 l by 40 l
Fall 2008
76
Fall 2008
77
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Fall 2008
78
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
2
dd
L
Energy/transition = C * V
L
Power = Energy/transition * f = C * V
2
dd
*f
Not a function of Ltransistor
sizes!
dd
Need to reduce C , V , and f to reduce power.
Fall 2008
79
Modification for Circuits with Reduced Swing
Vdd
Vdd
Vdd -Vt
CL
E0
1
= CL  Vdd   Vdd – Vt 
Can exploit reduced sw ing to low er power
(e.g., reduced bit-line swing in memory)
Fall 2008
80
Adiabatic Charging
2
2
Fall 2008
2
81
Adiabatic Charging
Fall 2008
82
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL  V dd2  n N 
EN : the energy consumed for N clock cycles
n(N ): the number of 0->1 transition in N clock cycles
EN
2
n N 
P avg = lim --------  fclk =  lim ----------- C  Vdd  f clk
N   N 
N N
L
0  1 =
n N 
lim -----------N N
P avg = 0 1  C  Vdd 2  f clk

L
Fall 2008
83
Transistor Sizing for Minimum
Energy
In
Out
Cg1
1
f
Cext
 Goal: Minimize Energy of whole circuit
 Design parameters: f and VDD
 tp  tpref of circuit with f=1 and VDD =Vref

f 
F 
t p  t p 0  1    1   
f  
   
VDD
t p0 
VDD  VTE
Fall 2008
84
Transistor Sizing (2)
 Performance Constraint (=1)
tp
t pref

t p0
t p 0 ref

F
 2  f  
f  VDD Vref  VTE


3  F 
Vref VDD  VTE

F
 2  f  
f 

1
3  F 
 Energy for single Transition
2
E  VDD
C g1 1   1  f   F 
2
 VDD   2  2 f  F 
E
 




Eref  Vref   4  F 
Fall 2008
85
Transistor Sizing (3)
VDD=f(f)
E/Eref=f(f)
4
1.5
3.5
F=1
normalized energy
3
2
vdd (V)
2.5
5
2
1.5
1
10
0.5
20
0
1
2
3
4
f
Fall 2008
5
6
7
1
0.5
0
1
2
3
4
5
6
7
f
86
Short Circuit Currents
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
Fall 2008
1.0
2.0
3.0
Vin (V)
4.0
5.0
87
How to Keep Short-Circuit Currents Low?
Short circuit current goes to zero if tfall >> trise,
but can’t do this for cascade logic, so ...
Fall 2008
88
Minimizing Short Circuit Power
8
7
6
Vdd =3.3
Pnorm
5
4
Vdd =2.5
3
2
1
Vdd =1.5
0
0
1
2
3
4
5
t /t
sin sout
Fall 2008
89
Leakage
Vd d
Vout
Drain Junction
Leakage
Sub-Threshold
Current
Sub-threshold current one of most compelling issues
in low-energy
circuit design!
Sub-Threshold
Current Dominant Factor
Fall 2008
90
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
2
JS = JS
1-5pA/
for a 1.2
technology
= 10-100
at 25
degCMOS
C for 0.25m
CMOS
mpA/m2
m
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature
Fall 2008
91
Subthreshold Leakage Component
Fall 2008
92
Static Power Consumption
Vd d
Istat
Vout
Vin =5V
CL
Pstat = P(In=1) .Vdd . Istat
Wasted •energy
… over dynamic consumption
Dominates
Should be avoided in almost all cases,
• Not a function of switching frequency
but could help reducing energy in others (e.g. sense amps)
Fall 2008
93
Principles for Power Reduction
 Prime choice: Reduce voltage!
 Recent years have seen an acceleration in supply
voltage reduction
 Design at very low voltages still open question (0.6 …
0.9 V by 2010!)
 Reduce switching activity
 Reduce physical capacitance
 Device Sizing: for F=20

Fall 2008
fopt(energy)=3.53, fopt(performance)=4.47
94
Digital Electronics
Fall 2008
95
Goals of Technology Scaling
 Make things cheaper:
 Want to sell more functions (transistors) per chip for the
same money
 Build same products cheaper, sell the same part for less
money
 Price of a transistor has to be reduced
 But also want to be faster, smaller, lower power
Fall 2008
96
Technology Scaling
 Goals of scaling the dimensions by 30%:
 Reduce gate delay by 30% (increase operating frequency
by 43%)
 Double transistor density
 Reduce energy per transition by 65% (50% power
savings @ 43% increase in frequency
 Die size used to increase by 14% per generation
 Technology generation spans 2-3 years
Fall 2008
97
Technology Generations
Fall 2008
98
Technology Evolution (2000 data)
International Technology Roadmap for Semiconductors
Year of
Introduction
1999
Technology node
[nm]
180
Supply [V]
1.5-1.8
Wiring levels
2000
2001
2004
2008
2011
2014
130
90
60
40
30
1.5-1.8
1.2-1.5
0.9-1.2
0.6-0.9
0.5-0.6
0.3-0.6
6-7
6-7
7
8
9
9-10
10
Max frequency
[GHz],Local-Global
1.2
1.6-1.4
2.1-1.6
3.5-2
7.1-2.5
11-3
14.9
-3.6
Max P power [W]
90
106
130
160
171
177
186
Bat. power [W]
1.4
1.7
2.0
2.4
2.1
2.3
2.5
Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm
Fall 2008
99
Technology Evolution (1999)
Fall 2008
100
ITRS Technology Roadmap Acceleration
Continues
Fall 2008
101
Technology Scaling (1)
Minimum Feature Size (micron)
10
10
10
10
2
1
0
-1
-2
10
1960
1970
1980
1990
2000
2010
Year
Minimum Feature Size
Fall 2008
102
Technology Scaling (2)
Number of components per chip
Fall 2008
103
Technology Scaling (3)
tp decreases by 13%/year
50% every 5 years!
Propagation Delay
Fall 2008
104
Technology Scaling (4)
/
4
x
3
1
0.1
0.01
80
MPU
DSP
85
90
Year
(a) Power dissipation vs. year.
95
1000

3
10
a rs
e
y
0.7

100

Power Dissipation (W)
100
rs
Power Density (mW/mm2 )
ea
x1.4 / 3 y
10
1
1
Scaling Factor 
（normalized by 4 m design rule ）
(b) Power density vs. scaling factor.
10
From Kuroda
Fall 2008
105