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Class 04
Overview
Static CMOS
Conventional Static CMOS Logic
Ratioed Logic
Pass Transistor/Transmission Gate Logic
Dynamic CMOS Logic
Domino
np-CMOS
Combinational vs. Sequential Logic
In
Logic
In
Circuit
Out
Logic
Out
Circuit
State
(a) Combinational
Output = f(In)
(b) Sequential
Output = f(In, Previous In)
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Static CMOS
VDD
In1
In2
In3
PUN
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
PMOS Transistors in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
Complementary CMOS Logic Style Construction (cont.)
Example Gate: NAND
Example Gate: NOR
Example Gate: COMPLEX CMOS GATE
VDD
B
A
C
D
OUT = D + A• (B+C)
A
D
B
C
Standard Cell Layout Methodology
metal1
VDD
Well
VSS
Routing Channel
signals
polysilicon
Dynamic CMOS
 In static circuits at every point in time (except
when switching) the output is connected to either
GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type) devices
 Dynamic circuits rely on the temporary storage of
signal values on the capacitance of high
impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type) transistors
13
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
Clk
CL
PDN
A
C
B
Me
Clk
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
15
1
Out
((AB)+C)
off
Me on
Conditions on Output
 Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
 Inputs to the gate can make at most one transition
during evaluation.
 Output can be in the high impedance state during
and after evaluation (PDN off), state is stored on
CL
16
Properties of Dynamic Gates
 Overall power dissipation usually higher than static
CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 no glitching
 higher transition probabilities
 extra load on Clk
 PDN starts to work as soon as the input signals
exceed V Tn, so VLT, VIH and VIL equal to V Tn
 low noise margin (NML)
 Needs a precharge/evaluate clock
17
Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Me
Evaluate
VOut
Precharge
Leakage sources
Dominant component is subthreshold current
18
Solution to ChargeKeeper
Leakage
Clk
Mp
A
Mkp
CL
B
Clk
Me
Same approach as level restorer for pass-transistor logic
19
Out
Issues in Dynamic Design 2:
Charge Sharing
Clk
Mp
Out
A
CL
B=0
Clk
20
CA
Me
CB
Charge stored originally on CL is
redistributed (shared) over CL and CA
leading to reduced robustness
Charge Sharing Example
Clk
Ca=15fF
B
Cc=15fF
A
A
B
B
C
C
Clk
21
Out
CL=50fF
!B
Cb=15fF
Cd=10fF
Issues in Dynamic Design
Clock Feedthrough
Clk
Mp
A
CL
B
Clk
22
Out
Me
Coupling between Out and Clk input
of the precharge device due to the gate
to drain capacitance. So voltage of Out
can rise above VDD. The fast rising
(and falling edges) of the clock couple
to Out.
Cascading Dynamic
Gates
V
Clk
Mp
Clk
Mp
Out1
Me
Clk
Out2
In
In
Clk
Clk
Me
Out1
V Tn
V
Out2
t
Only 0  1 transitions allowed at inputs!
23
Domino Logic
Clk
In1
In2
In3
Clk
24
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
00
01
In4
In5
Clk
PDN
Me
Out2
Domino Logic
 Domino logic is a CMOS-based evolution of the dynamic
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logic techniques based on either PMOS or NMOS
transistors.
It was developed to speed up circuits.
In Dynamic Logic, a problem arises when cascading one
gate to the next.
The precharge "1" state of the first gate may cause the
second gate to discharge prematurely, before the first gate
has reached its correct state.
This uses up the "precharge" of the second gate, which
cannot be restored until the next clock cycle, so there is no
recovery from this error.
Domino Logic
 various solutions to the problem of how to cascade dynamic
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logic gates.
One solution is Domino Logic, which inserts an ordinary static
inverter between stages.
While this might seem to defeat the point of dynamic logic,
since the inverter has a PFET (one of the main goals of Dynamic
Logic is to avoid PFETs where possible, due to speed),
Two reasons it works well.
First, there is no fanout to multiple PFETs.
The dynamic gate connects to exactly one inverter, so the gate is
still very fast.
And since the inverter connects to only NFETs in dynamic logic
gates, it too is very fast. Second, the PFET in an inverter can be
made smaller than in some types of logic gates.
Domino Logic
 In a domino logic cascade structure consisting of
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several stages, the evaluation of each stage ripples the
next stage evaluation,
similar to a domino falling one after the other.
Once fallen, the node states cannot return to "1" (until
the next clock cycle) just as dominos, once fallen,
cannot stand up.
The structure is hence called Domino CMOS Logic.
It contrasts with other solutions to the cascade
problem in which cascading is interrupted by clocks or
other means.
Important Domino Logic features:
 They have smaller areas than conventional CMOS
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logic (as does all Dynamic Logic).
Parasitic capacitances are smaller so that higher
operating speeds are possible.
Operation is free of glitches as each gate can make only
one transition.
Only non-inverting structures are possible because of
the presence of inverting buffer.
Charge distribution may be a problem.