Download CMOS_ch1.4_Pass Transistors

Chapter 1 Combinational CMOS Logic
Circuits
Lecture # 4 Pass Transistors and
Transmission Gates
Outline
•
•
•
•
•
•
A Brief History
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams
2
CMOS Logic Structures
Static logic circuits hold
their output values
indefinitely
Dynamic logic circuits
store the output in a
capacitor, so it decays with
time unless it is refreshed.
We will look at a few of
these structures
Pass Transistor
• Pass-transistor circuits are formed by dropping the PMOS
transistors and using only NMOS pass transistors
• In this case, CMOS inverters (or other means) must be used
periodically to recover the full VDD level since the NMOS
pass transistors will provide a VOH of VDD – VTn in some
cases
• The pass transistor circuit requires complementary inputs
and generates complementary outputs to pass on to the next
stage
Signal Strength
• Strength of signal
– How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• nMOS pass strong 0
– But degraded or weak 1
• pMOS pass strong 1
– But degraded or weak 0
• Thus nMOS are best for pull-down network
Pass Transistors
• We have assumed source is grounded
• What if source > 0?
– e.g. pass transistor passing VDD
VDD
• Vg = VDD
VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
• nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
• pMOS pass transistors pull no lower than Vtp
Pass Transistors
– The pass transistor is an nFET used as a switch-like element to connect logic
and storage.
VC = 1
VC
Vin
Vout
VC = 0
– Used in NMOS; sometimes used in CMOS to reduce cost.
– The voltage on the gate, VC, determines whether the pass transistor is “open” or
“closed” as a switch.
• If VC = H, it is “closed” and connects Vout to Vin.
• If VC = L, it is “open” and Vout is not connected to Vin.
– Consider Vin = L and Vin = H with VC = H. With Vin = L, the pass transistor is
much like a pull-down transistor in an inverter or NAND gate. So Vout, likewise,
becomes L. But, for Vin = H, the output becomes the effective source of the
FET. When VGS = VDD-VOUT =VTn , the nFET cuts off. The H level is VOUT =
VDD-VTn.
8
Pass Transistors
• Transistors can be used as switches
g
s
d
g
s
d
Pass Transistors
• Transistors can be used as switches
g=0
g
s
d
s
d
Input g = 1 Output
0
strong 0
g=1
s
d
g=0
g
s
s
g=1
Input
d
d
g=1
s
1
d
degraded 1
g=0
0
Output
degraded 0
g=0
strong 1
Pass Transistor
• This figure shows a simple
XNOR implementation
using pass transistors:
• If A is high, B is passed
through the gate to the
output
• If A is low, B’ is passed
through the gate to the
output
Pass Transistor
• At right,
– (a) is a 2-input NAND pass
transistor circuit
– (b) is a 2-input NOR pass
transistor circuit
• Each circuit requires 8
transistors, double that
required using conventional
CMOS realizations
Pass Transistor
• Pass-transistor logic gate can implement Boolean functions
NOR, XOR, NAND, AND, and OR depending upon the P1P4 inputs, as shown below.
–
–
–
–
–
P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR
P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XOR
P1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NAND
P1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = AND
P1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR
Circuit can be
operated with
clocked P pull-up
device or inverterbased latch
Transmission Gates
•
N-Channel MOS Transistors pass a 0 better than a 1
•
P-Channel MOS Transistors pass a 1 better than a 0
•
This is the reason that N-Channel transistors are used in the pull-down
network and P-Channel in the pull-up network of a CMOS gate.
Otherwise the noise margin would be significantly reduced.
TRANSMISSION GATES
 NMOS pass transistor passes a strong 0 and a weak 1.
 PMOS pass transistor passes a strong 1 and a weak 0.
 Combine the two to make a CMOS pass gate which will
pass a strong 0 and a strong 1.
TRANSMISSION GATES
 NMOS pass transistor passes a strong 0 and a weak 1.
 PMOS pass transistor passes a strong 1 and a weak 0.
 Combine the two to make a CMOS pass gate which will
pass a strong 0 and a strong 1.
• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well
TRANSMISSION GATE
Problems with transmission gates
 No isolation between the input and output.
 Output progressively deteriorates as it passes through various
stages.
However designs get simplified.
Series Parallel Structures (3)
N Switch
D
S
0
1
Passes “good zeros”
Passes “good ones”
G
S
D
G
S
S’
P Switch
1
0
Open Circuit, High Z
Bi-directional Switch
Transmission Gates
•
A transmission gate is a essentially a switch that connects two
points. In order to pass 0’s and 1’s equally well, a pair of
transistors (one N-Channel and one P-Channel) are used as
shown below:
When s = 1 the two transistors conduct and connect x and y
The top transistor passes x when it is 1 and the bottom transistor passes x
when it is 0
When s = 0 the two transistor are cut off disconnecting x and y
Transmission Gates
•
•
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
Four representations of CMOS Transmission Gate (TG)
a : Input
b : Output
g , gb : Control Signal
0, Z (high impedance)
g
 1, b  a
Analysis of CMOS TG (1/4)
A : Input
B : Output
C : Control Signal
0, Z (high impedance)
C
1, B  A
Transmission Gates (Pass Gates) (1/2)
– With body effect, for VDD = 5V, the value on Vout can be around 3.0 to 3.5
V. This reduced level diminishes NMH and the current drive for the gate or
gates driven by the pass transistor.
– For both NMOS and CMOS, the lack of current drive slows circuit
operation and NMH can be particularly problematic. As a consequence, in
CMOS, a pFET is added to form a transmission gate.
Transmission Gates
– Symbols:
C
C
A
B
C
Circuit
22
A
B
C
Popular Usage
Transmission Gates (2/2)
– Operation
• C is logic high  Both transistors are turned on and provide a
low-resistance current path between nodes A and B.
• C is logic low  Both transistors will be off, and the path
between nodes A and B will be open circuit. This condition is
called the high-impedance state.
– With the parallel pFET added, it can transfer a full VDD from
A to B (or B to A). It can also charge driven capacitance
faster.
– The substrates of NMOS and PMOS are connected to
ground and VDD, respectively. Therefore, the substrate-bias
effect must be taken into account.
23
Transmission Gate Circuits
• A CMOS TG is created by connecting an nFET and pFET in
parallel
– Bi-directional
– Transmit the entire voltage range [0, VDD]
y  x  s iff
s 1
Figure Transmission gate (TG)
Transmission Gate Circuits
• Exercise
y  x  s iff
s 1
XOR gate
XOR gate
B
A
F
0
0
0
0
1
1
1
0
1
1
1
0
Logic Design using TG (2/3)
• TG based XOR/XNOR
a b  a b  a b  a b
ab  ab  a b
(2.81)
(a) XOR circuit
(2.82)
(b) XNOR circuit
Figure 2.62 TG-based exclusive-OR and exclusive-NOR circuits
•
TG based OR gate
f  a  (a)  a  b
 a  a b
 ab
Figure 2.63 A TG-based OR gate
(2.83)
Logic Design using TG (3/3)
• Alternate XOR/XNOR Circuits
– Mixing TGs and FETs which are designed for exclusive-OR and
equivalence (XNOR) functions
– It’s important in adders and error detection/correction algorithms
Figure 2.64 An XNOR gate that used both TGs and FETs
TRANSMISSION GATE
 The 2:1 MUX can be modified to produced other useful function,
such as XOR & XNOR circuits.
s
P0
TG0
F
s
P1
s
b
a
TG1
b
a
ab
b
b
XOR
ab
b
b
XNOR
Tristates
• Tristate buffer produces Z when not enabled
EN
A
Y
0
0
Z
0
1
Z
1
0
0
1
1
1
EN
Y
A
EN
Y
A
EN
Nonrestoring Tristate
• Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y
EN
A
Y
EN
32
Tristate Inverter
• Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A
A
A
EN
Y
Y
Y
EN = 0
Y = 'Z'
EN = 1
Y=A
EN
Complementary Pass-Transistor Logic (CPL)
•
Utilizes CMOS transmission gate (or just the single polarity version of TG) to perform
logic
– Logical inputs may be applied to both the device gates as well as device source/drain regions
– Only a limited number of Pass Gates may be ganged in series before a clocked Pull-up (or pulldown) stage is required
•
(a) and (b) show simple XNOR implementation:
– If A is high, B is passed through the gate to the output
– If A is low, -B is passed through the gate to the output
•
(c) shows XNOR circuit including a cross-coupled input with P pull-up devices which
does not require inverted inputs
R. W. Knepper
SC571, page 5-23