Download Output Stages Class A, AB, and B Power Stages Laboratory

Milwaukee School of Engineering
© MSOE 2015
Dr.-Ing. Jörg Moßbrucker
Output Stages
Class A, AB, and B Power Stages
Laboratory Assignment
1
Introduction
To deliver a substantial amount of power into a relatively small load resistance, class B or
class AB push-pull output stages are used. Hereby used is a darlington configuration to
obtain a low output resistance and a relatively high input resistance. Quite often a VBE
multiplier is used to adjust the quiescent current through the power transistors.
2
Analysis
Given is a triple darlington push pull output stage using the small-signal transistors
BC546/BC556, the medium power transistors BD139/BD140, and the power transistors
BD809 and BD810. The triple is most often used in power stages delivering more than
app. 10W of signal power into a load. It allows a small current (app. 1mA) flowing
through the biasing VBE multiplier, hence improving the upper cutoff frequency due to
the gain-bandwidth product of the power transistors. The circuit shown in Figure 2.1
uses a DC voltage source for adjusting the quiescent current through the output transistors. The Emitter resistors allow a stable quiescent current somewhat independent of the
temperature of the power transistors (an increase of the quiescent current due to a temperature increase gives a higher voltage drop across the Emitter resistors, hereby reducing the quiescent current; this is negative feedback stabilizing the quiescent current). The
power supply voltages, here at +/- 40V, were chosen so that 50W can be delivered into
the load with sufficient headroom. The headroom usually is chosen to be somewhere
2
around 5V for class B and class AB stages. The headroom for class A stages must be
reduced as much as possible to reduce power absorption by the power transistors.
FIGURE 2.1: POWER OUTPUT STAGE USING A TRIPLE
2.1
Class B
Class B output stages are characterized by the fact that the quiescent current flowing
through the power transistors is zero for a zero input voltage. This gives a maximum efficiency of the entire stage, albeit at the cost of high distortions. Total harmonic distortions (THD) of power amplifiers usually are given at signal powers of 50mW, 5W, and
50W at a frequency of 1KHz and 20KHz into the load resistance.
Simulate the circuit shown in Figure 2.1. Change the power supply to +/- 35V
Set the bias voltages to zero, i.e. set the stage to class B.
Show that the quiescent currents through the power transistors is indeed 0
3
Set the input voltage so that the signal load power is 50mW. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
Set the input voltage so that the signal load power is 5W. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
Set the input voltage so that the signal load power is 50W. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
2.2
Class AB
Class AB output stages are characterized by the fact that the quiescent current flowing
through the power transistors is non-zero for a zero input voltage. This reduces the maximum efficiency of the entire stage gaining lower distortions.
Simulate the circuit shown in Figure 2.1. Change the power supply to +/- 35V.
Set the bias voltages so that the quiescent currents through the power transistors
is 200mA.
Show that the quiescent currents through the power transistors is indeed 200mA.
Set the input voltage so that the signal load power is 50mW. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
Set the input voltage so that the signal load power is 5W. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
Set the input voltage so that the signal load power is 50W. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
2.3
Class A
Push pull Class A output stages are characterized by the fact that the quiescent current
flowing through the power transistors is never zero for any input voltage.
Simulate the circuit shown in Figure 2.1. Change the power supply to +/- 30V
4
Set the bias voltages so that the quiescent currents through the power transistors
is 3.5A.
Show that the quiescent currents through the power transistors is indeed 3.5A.
Set the input voltage so that the signal load power is 50mW. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
Set the input voltage so that the signal load power is 5W. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
Set the input voltage so that the signal load power is 50W. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz. Determine the average power absorbed by the power transistors.
3
Design
Replace the two bias voltages with a VBE multiplier and adjust the multiplier so that the
quiescent current through the power transistors is 200mA.
Simulate the circuit with a power supply of +/- 35V.
Show that the quiescent currents through the power transistors is indeed 200mA.
Set the input voltage so that the signal load power is 50W. Show the form of the
output voltage and determine the THD @ 1KHz and 20KHz.