Download ec 6404 linear integrated circuits ltpc

EC 6404 LINEAR INTEGRATED CIRCUITS
LTPC
UNIT I: IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR IC
9
Current mirror and current sources, Current sources as active loads, Voltage sources,
Voltage References, BJT Differential amplifier with active loads, General operational amplifier
stages -and internal circuit diagrams of IC 741, DC and AC performance characteristics, slew
rate, Open and closed loop configurations.
UNIT II APPLICATIONS OF OPERATIONAL AMPLIFIERS
9
Sign Changer, Scale Changer, Phase Shift Circuits, Voltage Follower, V-to-I and I-to-V
converters, adder, subtractor, Instrumentation amplifier, Integrator, Differentiator,
Logarithmic amplifier, Antilogarithmic amplifier, Comparators, Schmitt trigger, Precision
rectifier, peak detector, clipper and clamper, Low-pass, high-pass and band-pass
Butterworth filters.
UNIT III ANALOG MULTIPLIER AND PLL
9
Analog Multiplier using Emitter Coupled Transistor Pair - Gilbert Multiplier cell –
Variable transconductance technique, analog multiplier ICs and their applications, Operation of
the basic PLL, Closed loop analysis, Voltage controlled oscillator, Monolithic PLL IC 565,
application of PLL for AM detection, FM detection, FSK modulation and demodulation
and Frequency synthesizing.
UNIT IV ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS
8
Analog and Digital Data Conversions, D/A converter – specifications - weighted resistor
2R Ladder types -type, R-2R Ladder type, Voltage Mode and Current-Mode R
switches for D/A converters, high speed sample-and-hold circuits, A/D Converters –
specifications - Flash type - Successive Approximation type - Single Slope type - Dual
Slope type - A/D Converter using Voltage-to-Time Conversion - Over-sampling A/D
Converters.
UNIT V WAVEFORM GENERATORS AND SPECIAL FUNCTION ICs
9
Sine-wave generators, Multivibrators and Triangular wave generator, Saw-tooth wave
generator, ICL8038 function generator, Timer IC 555, IC Voltage regulators - Three
terminal fixed and adjustable voltage regulators - IC 723 general purpose regulator Monolithic switching regulator, Switched capacitor filter IC MF10, Frequency to Voltage
and Voltage to Frequency converters, Audio Power amplifier, Video Amplifier, Isolation
Amplifier,
Opto-couplers
and
fibre
optic
IC.
TOTAL: 45 PERIODS
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 1
TEXT BOOKS
1. Sergio Franco, Design with operational amplifiers and analog integrated circuits, 3rd
Edition, Tata McGraw-Hill, 2007.
2. D.Roy Choudhry, Shail Jain, Linear Integrated Circuits, New Age International Pvt.
Ltd., 2000.
REFERENCES:
1. B.S.Sonde, System design using Integrated Circuits , New Age Pub, 2nd Edition,
2001
2. Gray and Meyer, Analysis and Design of Analog Integrated Circuits, Wiley
International, 2005.
3. Ramakant A.Gayakwad, OP-AMP and Linear ICs, Prentice Hall / Pearson Education,
4th Edition, 2001.
4. J.Michael Jacob, Applications and Design with Analog Integrated Circuits, Prentice
Hall of India, 1996.
5. William D.Stanley, Operational Amplifiers with Linear Integrated Circuits, Pearson
Education, 2004.
6. K Lal Kishore, Operational Amplifier and Linear Integrated Circuits, Pearson
Education, 2006.
7. S.Salivahanan & V.S. Kanchana Bhaskaran, Linear Integrated Circuits, TMH, 2008.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 2
UNIT- I
IC FABRICATION AND CIRCUIT CONFIGURATION FOR LINEAR IC
ANNA UNIVERSITY SOLVED 2 MARKS AND 16 MARKS QUESTIONS
1. Define an Integrated circuit. (MAY 2010), (MAY 2011)
An integrated circuit(IC) is a miniature, low cost electronic circuit consisting of active and passive
components fabricated together on a single crystal of silicon. The active components are transistors
and diodes and passive components are resistors and capacitors.
2. Mention the advantages of integrated circuits over discrete Components. (MAY 10),
(DEC 10)
 Miniaturization and hence increased equipment density.
 Cost reduction due to batch processing.
 Increased system reliability due to the elimination of soldered joints.
 Improved functional performance.
 Matched devices. *Increased operating speeds.
 Reduction in power consumption.
3. What are the two common methods for obtaining integrated capacitors?
 Monolithic junction capacitor
 Thin-flim capacitor
4. What are the basic processes involved in fabricating ICs using planar Technology?
( May 2011)
1. Silicon wafer (substrate) preparation
2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Isolation technique
8. Metallization
9. Assembly processing & packaging
5. What is active load? Where it is used and why? (MAY/JUNE 2010)
The active load realized using current source in place of the passive load in the collector
arm of differential amplifier makes it possible to achieve high voltage gain without requiring large
power supply voltage.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 3
6. Define virtual ground of a OP-Amp?
(May/June 2010)
A virtual ground is a ground which acts like a ground. It is a point that is at the fixed
ground potential (0v), though it is not practically connected to the actual ground or common
terminal of the circuit.
7. List out the steps used in the preparation of Si – wafers.
1. Crystal growth &doping
2. Ingot trimming & grinding
3. Ingot slicing
4. Wafer policing & etching
5. Wafer cleaning
8. Write the basic chemical reaction in the epitaxial growth process of pure silicon.
The basic chemical reaction in the epitaxial growth process of pure silicon is the
hydrogen reduction of silicon tetrachloride.
1200C SiCl4 + 2H2 <> Si + 4 HCl
9. What are the two important properties of SiO2?
1. SiO2 is an extremely hard protective coatng & is unaffected by almost all reagents
except by hydrochloric acid. Thus it stands against any contamination.
2. By selective etching of SiO2 , diffusion of impurities through carefully defined
windows in the SiO2 can be accomplished to fabricate various components.
10. Explain the process of oxidation.
The silicon wafers are stacked up in a quartz boat & then inserted into quartz furnace
tube. The Si wafers are raised to a high temperature in the range of 950 to 1150oC & at the same
time, exposed to a gas containing O2 or H2O or both. The chemical action is
Si + 2H2O > Si O2+ 2H2
11. What is meant by molecular beam epitaxy (MBE)?
In the molecular beam epitaxy, ilicon along with dopants is evaporated. The evaporated
species are transported at a relatively high velocity in a vacuum to the substrate. The relatively low
vapour pressure of silicon & the dopants ensures condensation on a low temperature substrate.
Usually, silicon MBE is performed under ultra high vacuum (UHV) condition of 10-8 to 10-10
Torr.
12. What are the advantages and limitations implantation of ion implantation? (DEC 10)
Advantages:
• Accurate control over doping
• Very good reproducibility
• Precise resistance value
• A room temperature process
Limitations:
• Annealing at higher temperature is required for avoiding the crystal damage
• The possibility of dopant implanting through various layers of wafer.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 4
13.Define input offset voltage.
A small voltage applied to the input terminals to make the output voltage as zero when the
two input terminals are grounded is called input offset voltage.
14. Define CMRR of an op-amp.
(MAY 08), (DEC 10), (MAY 2011)
The relative sensitivity of an op-amp to a difference signal as compared to a common –mode
signal is called the common –mode rejection ratio. It is expressed in decibels.
𝐶𝑀𝑅𝑅 =
Ad
Ac
15. Mention the advantages of Wilson current source.
(i) Provides high output resistance.
(ii) Offers low sensitivity to transistor base currents.
16. Define sensitivity.
Sensitivity is defined as the percentage or fractional change in output current per
percentage or fractional change in power-supply voltage.
17. What are the limitations in a temperature compensated zener-reference source?
A power supply voltage of atleast 7 to 10 V is required to place the diode in the
breakdown region and that substantial noise is introduced in the circuit by the avalanching diode.
18. What is the need for frequency compensation in practical op-amps?
Frequency compensation is needed when large bandwidth and lower closed loop gain is
desired. Compensating networks are used to control the phase shift and hence to improve the
stability.
19. Define slew rate.
(MAY 2008), (DEC 10), (MAY 11) (DEC 11)
The slew rate is defined as the maximum rate of change of output Voltage caused by a step
input voltage.An ideal slew rate is infinite which means that op-amp’s output voltage should
change instantaneously in response to input step voltage.
20. Why IC 741 is not used for high frequency applications?
IC741 has a low slew rate because of the predominance of capacitance present in the
circuit at higher frequencies. As frequency increases the output gets distorted due to limited slew
rate.
21. What causes slew rate. (MAY 2008)
There is a capacitor with-in or outside of an op-amp to prevent oscillation. The capacitor
which prevents the output voltage from responding immediately to a fast changing input.
22. What happens when the common terminal of V+ and V- sources is not grounded?
(DEC 09)
If the common point of the two supplies is not grounded, twice the supply voltage will get
applied and it may damage the op-amp
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 5
23.Give the basic concept of current source?(DEC 2007)
A constant current source makes use of the fact that for a transistor in the active mode of
operation, the collector current is relatively independent of collector voltage
24. In what way 741S is better than 741 ?
741S is a military grade op-amp with higher slew rate
25. What is an ideal op-amp?
(DEC 2006)
An op-amp is said to be ideal, if it has the following characteristics





Open loop voltage gain, AOL = ∞
Input resistance, RI = ∞
Output impedance, R0 = ∞
Band width, B.W = ∞
Zero offset, V0 = 0, where V1=V2=0
26. List out the non-ideal d.c characteristics of an op-amp? (MAY 2011)
The d.c characteristics of an op-amp are




Input bias current
Input off set current
Input offset voltage
Thermal drift
27. List out the popular IC packages? (MAY 2011)
There are three popular IC packages. They are



The metal can (TO) package
The dual-in-line package (DIP)
The flat package or flat pack
28. What is the input voltage range of an op-amp?
Input voltage range is the common mode voltage that can be applied to both input terminals with
out affecting the performance of the op-amp. For 741C, the range of input common mode voltage
is  13V
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 6
29. What is thermal drift?
In an op-amp the bias current, offset current and off set voltage changes with change in
temperature. Offset current drift is measured in nA/ 0C and offset voltage drift is measured in mV/
0
C. These indicate the change in offset current or voltage for each degree Celsius change in
temperature. Forced air cooling may be used to stabilize the ambient temperature
Input offset voltage drift = ΔVos/ΔT
Input offset current drift = ΔIos/ΔT
30. Why is IC741 op-amp not used for high frequency applications?
Op-amp IC741 has very low slew rate (0.5V/μS) and therefore can not be used for high
frequency applications
31. List out the different types of op-amp?





Bipolar op-amp
FET op-amp
MOSFET op-amp
Bi FET op-amp
BiMOS op-amp
32. What are the special features of CMOS op-amp?
The special features of CMOS op-amp are

high input resistance(1012Ω)

low input current(~1pA)

high slew rate(~10V/μS)
33. What is the gain cross over and phase cross over frequencies.
The gain cross over frequency is the frequency at which the magnitude of the open loop transfer
function is unity. It is denoted by (ωgc).
│AOL .β│ = 1
20 log (│AOL .β│) = 0
The frequency at which the phase of open loop transfer function is 180 0 or nП radius is called
phase cross frequency (ωpc).
34. Define gain margin and phase margin
Gain margin:
The gain measured at phase cross over frequency is called gain margin.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 7
Gain margin in dB = -20 log │G (jω) │ where ω=ωpc
Phase margin:
The phase margin is the amount of additional phase lag at gain cross over frequency ω gc required
to bring the system to the very large instability.
Phase margin = 180 + Фgc
Where Фgc =  [G (jω)/ ω] = ωgc
For negative values of phase margin and gain margin the system becomes unstable
35. What are the basic differential amplifier configurations?
The four basic differential amplifier configurations are




Dual input and balanced output differential amplifier
Dual input and unbalanced output differential amplifier
Single input and balanced output differential amplifier
Single input and unbalanced output differential amplifier
36. How is the effect of off set current minimized?
The effect of off set current can be minimized by using a small feed back resistor. But to obtain
high input impedance, Ri must be large with large Ri, Rf should also be kept large to obtain
reasonable gain. Taking all these points to consideration, T- feed back network is used.
Rf
Rt
Rt
RS
R1
VO
RCOMP
Vi=0
37. The out put of a certain op-amp circuit changes by 20V in 4μS. What is the slew rate?
Slew rate = dV0/dt = 20V/4μS
Slew rate = 5V/μs
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 8
38. Define RRR.
The ability of the circuit to reject input ripples are present at the output due to input is given by
the factor ripple rejection ratio (RRR)
RRR = 20 log10 [Vri / Vro]
Where
Vri – input ripple magnitude
Vro – output ripple magnitude
Higher the value of RRR, better in the performance of the circuit
39. Define line regulation or input regulation or supply regulation
The effect of change in input voltage or the output voltage is specified by line regulation, it is
defined as
Line regulation = ΔVC/Δ Vi
 VO 
VO 

% line regulation = 100 X 

 Vi 


It is expressed in mV/V or %/V. its value should be as low as possible and d.c output voltage must
remain constant irrespective of changes in input line voltage
40. Define load regulation
The ability of the circuit to maintain constant output voltage under varying load current condition
is given by load regulation. It is expressed in mV/mA or mV/A, depending upon output current
capability
Load regulation = ΔVo / Δ IL
 VO 
VO 

% load regulation = 

 Vi 


It is measured in %/mA or %/Ampere
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 9
16 MARK QUESTIONS
1. Define CMRR, PSRR and Slew rate of an Operational Amplifier? [DEC (2006)] [MAY 2010]
Definition of CMRR:
The ability of a differential amplifier to reject a common mode signal is expressed by ratio called
common mode rejection ratio (CMRR). It is defined as the ratio of the differential voltage gain (A d) to
common mode gain (Ac)
CMRR = ρ = │Ad/Ac│
Ideal value of Ac is zero; hence ideal value of CMRR is infinite
CMRR in dB = 20 log │Ad/Ac│ dB
Definition of PSRR or SVRR or PSS.
The power supply rejection ratio (PSRR) is defined as the ratio of change in input offset voltage
due to change in supply voltage constant. It is also called as power supply sensitivity (PSS) or supply
voltage rejection ratio (PSRR)
PSRR = ΔVios / ΔVcc, VEE is constant
Definition of slew rate:
The slew rate is defined as the maximum rate of change s of output voltage caused by a step input voltage
and is usually specified in V/µs. For example, a 1 V/µs slew rate means that the output changes by 1v in
one microsecond.
2. Draw and explain the circuit diagram of basic current mirror circuit. [Nov 2003] [DEC 2011]
(or)
Explain the working of a current source with a circuit diagram. [Apr 2005][NOV/DEC (2006)]
(8m)
(or)
Draw the circuit of a simple bipolar transistor current source and show that its output current is
independent on the β of the transistor? [NOV/DEC (2006)],[Apr 2008]
“The circuit in which the output current is forced to equal the input current is called as current mirror
circuit i.e. output current is mirror of input current.”
A constant current source makes use of the fact that for a transistor in the active mode of operation,
collector current is independent of collector voltage.
Base and emitter of Q1 and Q2 are tied together and thus have same VBE. Also Q1 is connected as a diode
by shorting its base and collector i.e. VBE1 = VBE2
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 10
+VCC
I ref
Circuit to be
biased
R1
IC1
IC2 = IO
Q1
IB1
IB2
Q2
The input current Iref flows through Q1 and establishes a voltage across Q1. In turn this voltage appears
across base and emitter of Q2. Since transistor Q2 is identical to Q1 , the emitter currents of both Q1 and Q2
are equal which is approximately Iref . Thus as long as Q2 as in active region, its collector current IC2 = I0
will be approximately equal to Iref . Since output current I0 is a reflection or mirror of reference current Iref ,
the circuit is called current mirror circuit. This mirror effect is only valid for large values of β. The
collector currents of Q1 and Q2 are given as,
IC1 = α IS eVBE1/VT
---------------------------------
IC2 = α IS eVBE2/VT
(1)
---------------------- (2)
Dividing (1) by (2) gives,
IC1 / IC2 = e (VBE1- VBE2) / VT
---------------------- (3)
Therefore we obtain,
IC1 = IC2 = IC = I0
Since both the transistors are identical β1 = β2 = β, KCL at collector of Q1 gives ,
Iref = IC1 + IB1 + IB2
= IC + (IC1/β1) + (IC2/β2)
= IC + IC (2/β)
Iref = IC (1+2/β)
IC = Iref ((β+2)/β)
---------------------- (A)
---------------------- (B)
From figure,
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 11
Iref = (VCC – VBE ) / R1
[ VBE  0.7 is small]
 I ref  VCC / R1
From equation (B), for β >> 1, β /β+2 is almost unity
 IC
 Iref  I0
For a constant value of R1, the circuit operates as current as long as Q2 is in active region.
V-I CHARACTERISTICS OF CURRENT MIRROR
IC2
Slope = (1/ro)
-VCE2
From the graph it is seen that VCE2 < 0.3V Q2 is Saturated. For VCE2 < 0.3V, transistor Q2 operates
in active region. The slope of the curve in the region gives the output resistance of the current
mirror.
3. Write short notes on dominant pole compensation used in op-amps? [NOV/DEC (2006)] (8m)
DOMINANT POLE COMPENSATION:
Vi
A
Vo'
R
Vo
C
Consider uncompensated transfer function, A of an op-amp in open loop condition is given by the
equation.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 12
A
AOL .1 . 2 .3
(S  1 )( S   2 )( S  3 )
Now we introduce dominant pole by RC network in series with op-amp as shown in figure. Now
compensated transfer function A becomes
A1 
A1 
but f d 
V0
 jX C


Vo ' R  jX C
1
1
jR
XC

 R
1  
  jX C



1
1  j 2fRC
1
2RC
 A1 
1
--------------------- (1)
jf
1
fd


1
A’=A.A1= A

jf
1
fd



A
A’= 

jf
1
fd

1












---------------------- (2)
but,
A=
AOL

f 
f 
f 
1  j 1  j 1  j 
f1 
f 2 
f3 

LINEAR INTEGRATED CIRCUITS
------------------ (3)
EGSPEC/DEPT. OF ECE/II YEAR
Page 13
A’ =
AOL

f 
f 
f
1  j 1  j 1  j
f d 
f1 
f2


f 
1  j 
f3 

-------- (A)
Where fd < f1 < f2 < f3,
The frequency Vs Gain plot is given as,
AO L (dB)
Uncompensated
-20dB/decade
-40dB/decade
Dominant Pole
Compensation
-60dB/decade
(-20dB/decade)
0
fd
f1
f2
f3
f (on log scale)
The values of R and C are selected in such a way that open loop gain drops to 0dB with a slope of 20dB/decade, at a frequency (f1) where the poles of uncompensated system contributes very small
phase shift. Generally, fd is selected so that magnitude plot of A’ passes through 0dB at pole f1 of
A. (i.e, ω gc = f1)
ADVANTAGES:

Since noise frequency components are outside smaller bandwidth, noise immunity of the
system is improved.

Adjusting the value of fd, adequate phase margin and the stability of the system is
assured.
LIMITATIONS:

It reduces the bandwidth from f1 to fd , thus bandwidth is drastically reduced

The poles should be real.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 14
4. Explain various stability criteria of opamp circuit? [NOV/DEC (2006)] (6m)
Op-Amp is rarely used in open loop configuration of its high gain. Consider a circuit with negative
resistive feedback,
R2
R1
Vo
V1
V2
For negative resistive feedback the closed loop gain can be written as,
ACL 
A
1  A
--------------------- (1)
Where, β  Feedback ratio,
A  Open loop gain.
If the characteristic equation, (1+A β) = 0, the circuit becomes unstable and leads to sustained
oscillation.
(1+A β) = 0
--------------------- (2)
 A β = -1
 A β = -1 + j 0
 A
=1
--------------------- (3)
 A β = 0° or 2nπ radians
--------------------- (4)
Equation (3) is called magnitude condition and equation (4) is called Phase condition. Both
conditions together called as Barkhausen’s criterion for sustained oscillations.
Gain cross over frequency:
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 15
The gain cross over frequency is the frequency at which the magnitude of the open loop transfer
function is unity. It is denoted by (ωgc)
│AOL .β│ = 1
20 log (│AOL .β│) = 0
Phase cross frequency:
The frequency at which the phase of open loop transfer function is 1800 or nπ radians is called
phase cross frequency (ωpc)
Gain margin:
The gain measured at phase cross over frequency is called gain margin
Gain margin in dB = -20 log │G (jω) │ where ω=ωpc
Phase margin:
The phase margin is the amount of additional phase lag at gain cross over frequency ωgc required
to bring the system to the very large instability
Phase margin = 180 + Фgc
Where Фgc = G ( j ) |    gc
For negative values of phase margin and gain margin the system becomes unstable.
STABILITY CRITERION:
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 16
20 log (Aβ) dB
0 dB
+ Ve G.M
|A β| < 0 dB
/A β > -180°
+ Ve P.M
-180°
ωgc
ωpc
Frequency (Hz)

When ω = ωgc = ωpc , the Barkhausen’s criterion is satisfied and the circuit
oscillates. The system is now called as marginally stable.

If the gain margin is to be positive at ω = ωpc, the system is said to be stable.
(i.e., 20 log (Aβ) < 0dB)

If the phase margin is positive at ω = ωgc, the system is stable (i.e., /A β > -180°)

More positive the value of G.M and P.M, more stable is the system.
5. Write brief note on frequency compensation in op-amp? [NOV/DEC (2006)] (10m) (or)
Explain the concept of frequency compensation and discuss any one of external compensation?
[NOV/DEC (2007)] (8m)
When lower closed loop gain and larger bandwidth is required for a system, suitable compensation
techniques are used. The two methods are
o External compensation
o dominant pole compensation
o pole-zero(lag) compensation
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 17
o Internal compensation
EXTERNAL COMPENSATION:
When op-amps are to be used for lower closed loop gain, they are compensated with externally
connected compensation components the compensating network alerts the open loop gain so that
roll-off rate is -20dB/decade over a wide range of frequency. The common methods are
DOMINANT POLE COMPENSATION:
Vi
Vo'
A
R
Vo
C
Consider uncompensated transfer function, A of an op-amp in open loop condition is given by the
equation.
A
AOL .1 . 2 .3
(S  1 )( S   2 )( S  3 )
Now we introduce dominant pole by RC network in series with op-amp as shown in figure. Now
compensated transfer function A becomes
A1 
A1 
but f d 
V0
 jX C


Vo ' R  jX C
1
1
jR
XC

1
 R
1  
  jX C



1
1  j 2fRC
1
2RC
 A1 
1
jf
1
fd
LINEAR INTEGRATED CIRCUITS
--------------------- (1)
EGSPEC/DEPT. OF ECE/II YEAR
Page 18


1
A’=A.A1= A

jf
1
fd



A
A’= 

jf
1
fd













---------------------- (2)
but,
A=
AOL
------------------ (3)

f 
f 
f 
1  j 1  j 1  j 
f1 
f 2 
f3 

A’ =
AOL

f 
f 
f 
f 
1  j 1  j 1  j 1  j 
f d 
f1 
f 2 
f3 

-------- (A)
Where fd < f1 < f2 < f3,
The frequency Vs Gain plot is given as,
AO L (dB)
Uncompensated
-20dB/decade
-40dB/decade
Dominant Pole
Compensation
-60dB/decade
(-20dB/decade)
0
fd
LINEAR INTEGRATED CIRCUITS
f1
f2
f3
EGSPEC/DEPT. OF ECE/II YEAR
f (on log scale)
Page 19
The values of R and C are selected in such a way that open loop gain drops to 0dB with a slope of 20dB/decade, at a frequency (f1) where the poles of uncompensated system contributes very small
phase shift. Generally, fd is selected so that magnitude plot of A’ passes through 0dB at pole f1 of
A. (i.e, ω gc = f1)
ADVANTAGES:

Since noise frequency components are outside smaller bandwidth, noise immunity of the
system is improved.

Adjusting the value of fd, adequate phase margin and the stability of the system is
assured.
LIMITATIONS:

It reduces the bandwidth from f1 to fd , thus bandwidth is drastically reduced

The poles should be real.
POLE ZERO (LAG) COMPENNSATION:
Compensating Network
}
Z1
Vi
A
Vo'
R1
Vo
}
R2
C
Z2
Consider the transfer function of a compensated Op-Amp with three break frequencies,
A=
AOL

f 
f 
f 
1  j 1  j 1  j 
f1 
f 2 
f3 

------------------ (4)
This transfer function A is modified by adding a pole and a zero with help of a compensating
network. The zero is added at high frequency, while pole is added at low frequency. The transfer
function of compensating n/w is say A1,
A1 =
Vo
Z2

Vo ' Z1  Z 2
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 20
Z1=R1, Z2 = R2 – j Xc2
Where,
A1 =
R 2 - j X c2
R 1  R 2 - j X c2
Dividing the above equation by jXc2, we get
R2
R
1
1 j 2
- j X c2
X c2
A1 =

(R 1  R 2 )
(R  R 2 )
1 1 j 1
- j X c2
X c2
=
1  jR2 (2fC2 )
1  j (R 1  R 2 )( 2fC2 )
f 

1 j 
f1 
A2 = 

f 
1 j 
fo 

where, f1 =
 Xc2 = 2π.f.C2
------------------(5)
1
1
, fo =
2R2 C 2
2 ( R1  R2 )C 2
AO L (dB)
Uncompensated
-20dB/decade
-40dB/decade
Compensated
(-20dB/decade)
0
f0
LINEAR INTEGRATED CIRCUITS
-60dB/decade
f1
f2
f3
EGSPEC/DEPT. OF ECE/II YEAR
f (on log scale)
Page 21
The values of R1,R2 and C2 are selected so that break frequency for zero matches with first corner
frequency,f1.While pole of the compensating network at f0 is selected in such a way that the
compensated transfer function A’ passes through 0 dB at second corner frequency f2.Resultant
loop gain is,
A’ = A.A1
------------------ (6)
Using (1), (2) and (3), we get,

f 
AOL 1  j 
f1 

A=

f 
f 
f
1  j 1  j 1  j
f 0 
f1 
f2


f 
1  j 
f3 

----------------- (B)
Where fo < f1 < f2 < f3.
Now fo is the first corner frequency and roll of rate is -20dB/decade. At f1, there is pole-zero
compensation roll-off rate maintains constant. The values of R1, R2, and C2 are selected such that
gain (AOL) drops to zero at f2 (i.e, ω gc = f2).
ADVANTAGE:
Comparing to dominant-pole compensation there is improvement in bandwidth equal to (f2-f1).
This is the advantage of pole-zero compensation.
INTERNAL COMPENSATION:
In recent Op-amps, compensation is provided internally with a capacitance C1 of 30pF that
internally shunts off signal current and hence reducing the output signals at high frequencies. This
causes AOL to roll off at -20dB/decade as assures a stable circuit. These Op-amps are called as
internally compensated Op-Amps and the technique is called as Miller effect compensation.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 22
AOL(dB)
104
103
102
10
1
10
100
1k
10k
f (Hz)
100k
6. Explain how the above circuit can be modified to make it less insensitive to β? [NOV/DEC (2006)]
+VCC
IC3 = IO
R1
IB3
I ref
Q3
'a'
'b'
IC1
IC2
Q1
IB1
IB2
Q2
High output resistance is the feature of Wilson current source, which is achieved due to the negative feed
back through Q=2. It also provides base current cancellation making I0 nearly equal to Iref.
Analysis:
Since
VBE1 = VBE2,
IC1 = IC2 and IB1 = IB2 = IB
At node ‘b’,
IE3 = 2 IB + IC2
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 23
IE3 = 2(IC2 / β) + IC2
2

IE3 =   1 IC2


IE3 is also equal to
---------------------- (1)
IE3 = IB3 + IC3
= IC3/β + IC3
1

IE3 = IC3   1


---------------------- (2)
From equations (1) and (2)
1

2

IC3   1 = IC2   1




  1
   2
 = IC3 
IC3 

  
  
   2

IC3 = I0 = IC2 
  1 
   2

IC3 = I0 = IC1 
  1 
------------- (3)
(here IC1 = IC2)
At node ‘a’
Iref = IC1 + IB3
  1 
 + I0 / β
= I0 
   2
  1 1 
 
= I0 
 2  
  2  2  2 

Iref = I0 
2
   2 
  2  2 

I0 = Iref  2


2


2


LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 24
Where,
Iref = (VCC – 2VBE) / R1
 r 
The output resistance of a Wilson current mirror is substantially greater   o  than basic current
 2 
mirror or Widlar current mirror.
7. Describe the causes of slew rate limiting and its effect on the highest frequency of undistorted
sinusoidal output? [NOV/DEC (2006)] (8m)
The slew rate is defined as maximum rate of change of output voltage with time. It is specified in V/μS.
Thus
 dV 
Slew rate = S =  0 
 dt  MAX
CAUSES:
Slew rate is caused due to limited changing rate of compensating capacitor, current limiting and
saturation of internal stages of op-amp, when a high frequency, large amplitude signal is applied. It is
given by,
dVC I

dt
C
For large charging rate, capacitor should be small or charging amount should be large. Hence slew rate of
op-amp is given by,
S
I max
C
Where, I max is the maximum internal capacitor charging current. The slew rate for non-inverting
amplifier is worst. Higher the value of slew rate better is the performance of op-amp.
SLEW RATE EQUATION:
LINEAR INTEGRATED CIRCUITS
VS=VO
EGSPEC/DEPT. OF ECE/II YEAR
Page 25
INPUT SIGNAL
Vm
VO
t
VS
-Vm
Let input signal VS is purely sinusoidal. Since the circuit is a voltage follower, the output is also purely
sinusoidal. In such circuit output voltage follows input voltage.
VS = Vm sinωt
V0 = Vm sinωt

dV0
 Vm ( cos t )
dt
 dV 
But  0 
is the slew rate S. The maximum value of cosωt is 1. Hence
 dt  MAX
 dV0 
is given by


 dt  MAX
 dV0 
= S = Vm (ω.1)


 dt  MAX
S = ω.Vm
S = 2.п.f.Vm in V/s
S
2. . f .Vm
10 6
----------------- (A)
in V/µs
This is the required slew rate equation.
The maximum signal frequency, fm is the maximum allowable frequency of input signal at which
undistorted output can be obtained.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 26
 fm 
S
2Vm
------------------ (B)
8. What is a current mirror? Discuss in detail the widlar current source? [APRIL/MAY
2007] (16m)
or
Explain the working of Widlar current source? [NOV/DEC-2008](6m)
“The circuit in which the output current is forced to equal the input current is called as current
mirror circuit i.e. output current is mirror of input current.”
ISOURCE
ISINK
CURRENT
MIRROR
ISOURCE = ISINK
Widlar Current Source:
I ref
Circuit to be
biased
R1
IC1
Q1
IC2 = IO
IB1
IB2
Q2
( IB2+IC2 )
RE
Whenever we need a low value of current source, the value of resistance R1 required is very high
and can not be fabricated economically in IC circuits. This is limitation of basic current mirror
circuit. So for low value of currents we go for Widlar current source where emitter resistance R E is
included in the emitter load of Q2. Due to this RE, VBE2 is less than VBE1. Hence current I0 is
smaller than IC1
The ratio of collector currents IC1 and IC2 is given by
IC1 / IC2 = e (VBE1- VBE2) / VT
LINEAR INTEGRATED CIRCUITS
---------------------- (1)
EGSPEC/DEPT. OF ECE/II YEAR
Page 27
Taking natural algorithm on both sides we get
VBE1 - VBE2 = VT ln (IC1/ IC2)
---------------------- (2)
Writing KVL for the base emitter loop,
VBE1 - VBE2 (IB2 + IC2) RE = 0
VBE1 - VBE2 = (IB2 + IC2) RE
I

=  C 2  I C 2  RE
 

1 
VBE1 - VBE2 =  1 IC2 RE
 
---------------------- (3)
Equating (2) and (3), we get
IC2 RE = VT ln (IC1/ IC2)
RE =
VT ln( I C1 / I C 2 )
1

  1 I C 2


---------------------- (A)
KCL at collector of Q1 gives,
Iref = IC1 + IB1 + IB2
Iref = IC1 +
I C1 I C 2
+


1  I
Iref = IC  1 + C 2
  
---------------------- (4)
In Widlar current source, IC2 << IC1 , so term IC2/β can be neglected in equation (4) , hence
1 
Iref = IC  1
 
  

I C  I ref 
  1
---------------------- (5)
Where,
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 28
Iref = (VCC – VBE) / R1
For β >> 1,
---------------------- (6)
IC1  Iref.
Hence small value of small currents can be obtained using small values of RE.
9.Explain :
a) band gap reference? (12m)
b)methds of improving slew rate? (4m) [APRIL/MAY 2007]
a) Band gap Reference:
A voltage reference circuit is primarily designed to provide constant d.c voltage which acts as a
reference for other circuits and is independent of changes in parameters like temperature ,input line
voltage ,load current etc. the basic requirements of a voltage reference circuit are accuracy and stability
with temperature and time.
We know that break down voltage for Zener diode and avalanche diodes are in range of 6 - 7V. So
supply voltage required is in range of 10V. Hence for lower supply voltages (≈ 25V), band gap reference
circuits are used.
+VCC
I
IO
Vref
IC2
R2
R1
IC3
Q3
Q2
Q1
R3
It uses a widlar current source with matched NPN transistors Q1 and Q2. Current density of Q1 is 10 times
greater than Q2.
Applying KVL to base emitter loop of Q1 and Q2 through R3 we get
VR3 = VBE1-VBE2 = ∆VBE
According to Eber-Molls equation
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 29
IC1 = IS eVBE1/VT
------------- (1)
IC2 = IS eVBE2 /VT
------------- (2)
Where, IS  Collector saturation current.
VT  Voltage equivalent of temperature.
(1) Divided by (2) gives
I C1
= e (VBE1 - VBE1) /VT
IC2
Taking natural logarithm on both sides, we get
 I  V  VBE 2 VBE VR 3
ln  C1   BE1


VT
VT
VT
 IC2 
I 
VR3  VT ln  C1 
 IC2 
------------- (3)
Current through R3 is,
I R3
I
VT ln  C1
V
 IC2
 R3 
R3
R3



Neglecting base current of Q2, we get
I C 2  I R3
I
VT ln  C1
 IC2

R3



--------------------
(4)
Thus IC2 is proportional to VT.
Applying KVL through R2, base emitter of Q3 and Vref we get
Vref = VBE3 + IC2.R2
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 30
Vref = VBE3 +
I 
R2
VT . ln  C1 
R3
 IC2 
------------- (5)
VBE3 has negative temperature coefficient (TC) while VT has positive temperature coefficient. By
designing proper values for ratios R2/R3 and IC1/IC2, zero TC can be achieved. We know that VT = k.T,
Where k is the Boltzmann’s constant ( k = 8.62X10-5eV/ 0K)
Vref  VBE3 
I 
R2
k.T ln  C1 
R3
 IC2 
------------ (6)
To obtain TC (Vref), differentiate (6) with respect to T
 TC (Vref ) 
Vref

T
I 
dVBE3 R2

k ln  C1  ------------- (7)
dT
R3
 IC2 
Where,
dVBE3
 TC (VBE3 )
dT
From p-n junction theory,
TC (VBE3 ) 
VBE  (VG 0  3VT )
T
V  VBE

TC (VBE 3 )    G 0
 3k 
T


------------- (8)
To have TC (Vref) = 0, we can write
TC (VBE 3 )  
I 
R2
.k . ln  C1 
R3
 IC2 
From equation (8), we get
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 31
I
R
V  VBE

  G0
 3k  =  2 .k . ln  C1
T
R3


 IC2



Multiplying by T on both sides and using VT = k.T , we get,
VBE  VG 0  3VT 
 I
R2
VT ln  C1
R3
  IC2



------------- (9)
Substituting (9) in (6), we get
Vref  VG 0  3VT 
 I
R2
.VT ln  C1
R3
  IC2
  R2
I
 
VT ln  C1
 R3
 IC2



Vref  VG 0  3VT
------------- (A)
Where, VG0 = band gap voltage
Thus reference voltage is constant and is determined by VG0; hence the circuit is called band gap
voltage reference circuit. The Vref of (1.2V) can be generated with this circuit
b) Methods of Improving Slew rate:
METHODS OF IMPROVING SLEW RATE:
C
vn
gm1
vp
a2
IO1
VO2
a2>>1
a3
VO
a3=1
VS
Consider the above op-amp model for analysis of the slew rate. The op-amp is used in voltage follower
mode so V0 = Vi. When input overdrives the input stage then Imax = I01(sat) which are saturation of current
levels of input stage. Under this condition the op-amp is operating under large signal conditions
I01 (sat) = C
d .v02
dt
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 32
d .v02 I 01( sat)

dt
C
d .v02  d .v02 

 S
dt
 dt  max
S 
I 01( sat)
--------------------- (1)
C
Analyzing the op-amp model used we can write,
V02 = drop across C = ZC.I01
--------------------- (2)
The input stage is the transconductance amplifier i.e, voltage input, and current output amplifier.
Hence
Output current = gm X (differential input)
 I01 = gm (Vp-Vn)
But V02 ≈ V0
---------------------- (3)
, a3 ≈ 1
 V02 = V0 = ZC [gm1 (Vp-Vn)]
 V0 = 1 [g m1 (Vp - Vn )]
jC
V0
g m1

V p  Vn
jC
 Op-amp gain
a.f 
a 
V0
g m1
g

 m1
V p  Vn
jC
C
gm1
2C
But ft = a .f is the unity gain bandwidth product,
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 33
 ft 
C 
g m1
2C
g m1
2f t
Substitute the value of C in (1), we get
S
2f t .I 01( sat )
g m1
From the above equation we discuss the methods of improving slew rate.
1. Increasing ft:
Higher the gain bandwidth product, ft, higher is the slew rate. To increase ft, the internal capacitor value
must be reduced. Frequency compensation schemes like feed-forward compensation can be used to
achieve higher ft and thus higher slew rate.
2. Increasing I01 (sat):
It is very difficult to increase I01(sat),since we can not control it externally by user. But without affecting
gm value we can increase I01(sat) by providing alternate path for rapid changing and discharging of C. this is
possible by using additional input transistor pair which conducts when large amplifier input signal is
applied.
3. Reducing gm:
The gain of the differential input stage can be reduced by using suitable resistances in series with
emitters of differential input transistors. This technique is called emitter degeneration. Reducing input
stage transconductance (gm) by this method, slew rate can be improved.
10. Draw the circuit of a differential amplifier with current mirror load. Draw its equivalent circuit
and derive an expression for its gain ?
[2011](16m)
The equation for differential mode gain Ad is
Ad 
h fe .RC
RS  hie
Hence it is clear that Ad is proportional to collector resistance RC. For high gain, RC value should be
high.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 34
But there are some limitations to select large value of RC such as,

For large values of RC, quiescent drop is more; hence high biasing voltage is required to
maintain the quiescent collector current.

High values of RC require large chip area. So it is not possible to increase the value RC beyond
certain limit.
These difficulties are circumvented by using a current mirror as load in the place of RC.
+VCC
Q3
Q4
I
I1
v1
I2
VO
[ To next Stage]
Q2
Q1
v2
IQ
The current mirror circuit has the d.c resistance of order of few kilo ohms, as quiescent voltage across it
is a fraction of supply voltage and a current is in milliamperes. However since it acts as a constant current
source, its dynamic resistance (a.c) is very high, so a current mirror can be used as a active load.
In above circuit, current mirror uses PNP transistors Q3 and Q4. Constant current IQ is obtained from
current mirror.
OPERATION:
Under quiescent condition, v1 = v2 = 0, from symmetry of Q1 and Q2, I1= I2=IQ/2 where base currents are
assumed to be neglected. Since Q3 and Q4 form a current mirror
I1= I2 = I. The load current IL entering the next stage is given by
IL= I1- I2 = 0
--------------------------- (A)
However when v1 increases over v2, current I1 increases where as I2 decreases, since
I1 + I2 = IQ (constant)
The load current is given by
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 35
IL= I - I2
( I1 = I)
IL= I1- I2
= gm.v1- gm.v2
= gm (v1- v2)
IL = gm.vd
--------------------------- (B)
Thus the circuit behaves as a transconductance amplifier.
+VCC
RC
Vo
RS
Q1
VS /
Ib
2
Fig: a.c Equivalent circuit for differential mode operation
The differential gain is obtained b taking VS1 = VS2 = VS / 2. The two emitter currents IC1, IC2 are equal in
magnitude and 1800 out of phase. Hence they cancel each other to get resultant a.c current through emitter
s zero. Thus for a.c purposes emitter terminal is grounded.
Since both the transistors are matched, the a.c equivalent circuit for the other transistor is identical to the
one shown in figure. This is called half circuit concept of analysis. The approximate hybrid model for
above circuit is.
RS
C
B
+
VS /
2
-
+
Ib
RC
hie
E
hfeIb
+
Vo
-
Applying KVL to input loop,
–Ib RS – Ib hie + VS / 2 = 0
VS / 2 = Ib (RS + hie)
LINEAR INTEGRATED CIRCUITS
---------------------- (1)
EGSPEC/DEPT. OF ECE/II YEAR
Page 36
Ib =
VS
2( RS  hie )
---------------------- (2)
Applying KVL to Output loop and considering the direction of current hfe Ib
V0 = -hfe Ib. Re
---------------------- (3)
Substituting (2) in (3) we get,
V0 = -hfe
VS RC
2( RS  hie )
VO
RC
= -hfe
VS
2( RS  hie )
The negative sign indicates the phase difference between input and output. The differential input
voltage Vd is
Vd = V1 – V2
Vd =
VS  VS 
  
2  2 
Vd = VS
The magnitude of differential gain Ad is
Ad = V0 / VS
Ad =
h fe RC
2( RS  hie )
This is the differential gain for the differential amplifier with unbalanced output. Hence for balanced
output taken across collectors of identical transistors Q1 and Q2, the gain Ad is double than that obtained
for unbalanced output.
Ad =
2h fe RC
2( RS  hie )
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 37
h fe RC
Ad =
( RS  hie )
--------------------- (A)
This the differential gain of dual input, balanced output differential amplifier
11. What is Slew rate? Discuss the methods of improving slew rate? [DEC-2008] ,[MAY 2010]
The slew rate is defined as maximum rate of change of output voltage with time. It is specified in V/μS.
Thus
 dV 
Slew rate = S =  0 
 dt  MAX
CAUSES:
Slew rate is caused due to limited changing rate of compensating capacitor, current limiting and
saturation of internal stages of op-amp, when a high frequency, large amplitude signal is applied. It is
dVC
I
given by,

dt
C
For large charging rate, capacitor should be small or charging amount should be large. Hence slew rate of
I
op-amp is given by, S  max
C
Where, I max is the maximum internal capacitor charging current. The slew rate for non-inverting
amplifier is worst. Higher the value of slew rate better is the performance of op-amp.
SLEW RATE EQUATION:
VS=VO
VO
VS
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 38
INPUT SIGNAL
Vm
t
-Vm
Let input signal VS is purely sinusoidal. Since the circuit is a voltage follower, the output is also
purely sinusoidal. In such circuit output voltage follows input voltage.
VS = Vm sinωt
V0 = Vm sinωt

dV0
 Vm ( cos t )
dt
 dV 
But  0 
is the slew rate S. The maximum value of cosωt is 1. Hence
 dt  MAX
 dV0 
is given by


 dt  MAX
 dV0 
= S = Vm (ω.1)


 dt  MAX
S = ω.Vm
S = 2.п.f.Vm in V/s
S
2. . f .Vm
10 6
----------------- (A)
in V/µs
This is the required slew rate equation.
The maximum signal frequency, fm is the maximum allowable frequency of input signal at which
undistorted output can be obtained.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 39
METHODS OF IMPROVING SLEW RATE:
C
vn
gm1
vp
VO2
a2
IO1
a2>>1
a3
VO
a3=1
VS
Consider the above op-amp model for analysis of the slew rate. The op-amp is used in voltage follower
mode so V0 = Vi. When input overdrives the input stage then Imax = I01(sat) which are saturation of current
levels of input stage. Under this condition the op-amp is operating under large signal conditions
I01 (sat) = C
d .v02
dt
d .v02 I 01( sat)

dt
C
d .v02  d .v02 

 S
dt
 dt  max
S 
I 01( sat)
--------------------- (1)
C
Analyzing the op-amp model used we can write,
V02 = drop across C = ZC.I01
--------------------- (2)
The input stage is the transconductance amplifier i.e, voltage input, and current output amplifier.
Hence
Output current = gm X (differential input)
 I01 = gm (Vp-Vn)
But V02 ≈ V0
---------------------- (3)
, a3 ≈ 1
 V02 = V0 = ZC [gm1 (Vp-Vn)]
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 40
 V0 = 1 [g m1 (Vp - Vn )]
jC
V0
g m1

V p  Vn
jC
 Op-amp gain
a.f 
a 
V0
g m1
g

 m1
V p  Vn
jC
C
gm1
2C
But ft = a .f is the unity gain bandwidth product,
 ft 
C 
g m1
2C
g m1
2f t
Substitute the value of C in (1), we get
S
2f t .I 01( sat )
g m1
From the above equation we discuss the methods of improving slew rate.
1. Increasing ft:
Higher the gain bandwidth product, ft, higher is the slew rate. To increase ft, the internal capacitor
value must be reduced. Frequency compensation schemes like feed-forward compensation can be used to
achieve higher ft and thus higher slew rate.
2. Increasing I01 (sat):
It is very difficult to increase I01(sat),since we cant control it externally by user. But without affecting gm
value we can increase I01(sat) by providing alternate path for rapid changing and discharging of C. this is
possible by using additional input transistor pair which conducts when large amplifier input signal is
applied.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 41
3. Reducing gm:
The gain of the differential input stage can be reduced by using suitable resistances in series with
emitters of differential input transistors. This technique is called emitter degeneration. Reducing input
stage transconductance (gm) by this method, slew rate can be improved.
12. what is an active load? Explain the CE amplifier with active load. [NOV/DEC-2008] (8m)
The equation for differential mode gain Ad is
Ad 
h fe .RC
RS  hie
Hence it is clear that Ad is proportional to collector resistance RC. For high gain, RC value should be
high.
But there are some limitations to select large value of RC such as,

For large values of RC, quiescent drop is more; hence high biasing voltage is required to
maintain the quiescent collector current.

High values of RC require large chip area. So it is not possible to increase the value RC beyond
certain limit.
These difficulties are circumvented by using a current mirror as load in the place of RC.
+VCC
Q3
Q4
I
I1
v1
I2
VO
[ To next Stage]
Q2
Q1
v2
IQ
The current mirror circuit has the d.c resistance of order of few kilo ohms, as quiescent voltage across it
is a fraction of supply voltage and a current is in milliamperes. However since it acts as a constant current
source, its dynamic resistance (a.c) is very high, so a current mirror can be used as a active load.
In above circuit, current mirror uses PNP transistors Q3 and Q4. Constant current IQ is obtained from
current mirror.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 42
OPERATION:
Under quiescent condition, v1 = v2 = 0, from symmetry of Q1 and Q2, I1= I2=IQ/2 where base currents are
assumed to be neglected. Since Q3 and Q4 form a current mirror
I1= I2 = I. The load current IL entering the next stage is given by
IL= I1- I2 = 0
--------------------------- (A)
However when v1 increases over v2, current I1 increases where as I2 decreases, since
I1 + I2 = IQ (constant)
The load current is given by
IL= I - I2
( I1 = I)
IL= I1- I2
= gm.v1- gm.v2
= gm (v1- v2)
IL = gm.vd
--------------------------- (B)
Thus the circuit behaves as a transconductance amplifier.
13. Explain pole zero compensation? [NOV/DEC-2008] (8m)
POLE ZERO (LAG) COMPENNSATION:
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 43
Compensating Network
}
Z1
Vi
Vo'
A
R1
Vo
}
R2
C
Z2
Consider the transfer function of a compensated Op-Amp with three break frequencies,
A=
AOL
------------------ (4)

f 
f 
f 
1  j 1  j 1  j 
f1 
f 2 
f3 

This transfer function A is modified by adding a pole and a zero with help of a compensating
network. The zero is added at high frequency, while pole is added at low frequency. The transfer
function of compensating n/w is say A1,
A1 =
Vo
Z2

Vo ' Z1  Z 2
Where,
A1 =
Z1=R1, Z2 = R2 – j Xc2
R 2 - j X c2
R 1  R 2 - j X c2
Dividing the above equation by jXc2, we get
R2
R
1
1 j 2
- j X c2
X c2
A1 =

(R 1  R 2 )
(R  R 2 )
1 1 j 1
- j X c2
X c2
=
1  jR2 (2fC2 )
1  j (R 1  R 2 )( 2fC2 )
LINEAR INTEGRATED CIRCUITS
 Xc2 = 2π.f.C2
EGSPEC/DEPT. OF ECE/II YEAR
Page 44
f 

1 j 
f1 
A2 = 

f 
1 j 
fo 

where, f1 =
------------------(5)
1
1
, fo =
2R2 C 2
2 ( R1  R2 )C 2
AO L (dB)
Uncompensated
-20dB/decade
-40dB/decade
Compensated
(-20dB/decade)
0
f0
-60dB/decade
f1
f2
f3
f (on log scale)
The values of R1,R2 and C2 are selected so that break frequency for zero matches with first corner
frequency,f1.While pole of the compensating network at f0 is selected in such a way that the
compensated transfer function A’ passes through 0 dB at second corner frequency f2.Resultant
loop gain is,
A’ = A.A1
------------------ (6)
Using (1), (2) and (3), we get,

f 
AOL 1  j 
f1 

A=

f 
f 
f
1  j 1  j 1  j
f 0 
f1 
f2


f 
1  j 
f3 

----------------- (B)
Where fo < f1 < f2 < f3.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 45
Now fo is the first corner frequency and roll of rate is -20dB/decade. At f1, there is pole-zero
compensation roll-off rate maintains constant. The values of R1, R2, and C2 are selected such that
gain (AOL) drops to zero at f2 (i.e, ω gc = f2).
ADVANTAGE:
Comparing to dominant-pole compensation there is improvement in bandwidth equal to (f2-f1).
This is the advantage of pole-zero compensation.
13. write about temperature independent biasing provided for differential amplifier? [NOV/DEC2007](6m)
For large CMRR, ACM should be as small as possible. Common mode gain, ACM = 0, as RE
= ∞. But there are practical limitations on the magnitude of RE because of the quiescent d.c voltage across
it. The use of constant current bias in the place of RE is found to be solution for this problem.
+VCC
RC
RC
vO1
vO2
Q2
Q1
v1
IQ
v2
R1
Q2
I3
D
R3
R2
-VEE
RE is replaced by a constant current transistor circuit in which R1, R2 and R3 can be adjusted to give the
same quiescent conditions for the transistors Q1 and Q2 . This modified circuit gives a very high effective
emitter resistance, RE even for small values of R3.
Writing KVL for the base circuit of Q3, we get
VBE3  I 3 R3  VD  (VEE  VD )
R2
R1  R2
------------------- (1)
Where
VD is the voltage drop across diode D
If base current is neglected
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 46
IQ  I3 
V .R
1  VEE .R2
 
 D 1  VBE3
R3  R1  R2 R1  R2
 -------------------- (2)
By neglecting proper values of R1 and R2, we get
VBE3 
VD .R1
R1  R2
-------------------- (3)
So equation (2) becomes,
IQ 
1  VEE .R1

R3  R1  R2



------------------ (A)
Hence the current IQ is constant and it is independent of signal voltage V1 and V2. The diode D makes IQ
independent of temperature. VBE3 decreases by 2.5mv/ 0C and diode D also has same temperature
dependence. Hence, the two variations cancel each other and IQ becomes independent of temperature. Two
diodes are used in place of D for effectively satisfying the equation 3.
With constant IQ, ACM is zero so that the circuit provides very high CMRR. Under quiescent conditions
(no a.c signal), IQ gets equal divided in Q1 and Q2 and IC1 + IC2 = IQ/2
If V1=V2, still there will be no change in collector currents ic1 and ic2 as IQ is constant. These small
signals current iC flowing through load resistor RC is zero, hence the output voltage is zero. Thus we can
state that differential amplifier, if supplied with constant current bias gives very high CMRR.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 47
14. Explain how the feed forward compensation extends the bandwidth of an op-amp?[APR/MAY2008](10m)
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 48
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 49
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 50
15. Discuss the analysis of differential amplifier using active load? [MAY/JUNE-07]
The equation for differential mode gain Ad is
Ad 
h fe .RC
RS  hie
Hence it is clear that Ad is proportional to collector resistance RC. For high gain, RC value should
be high.
But there are some limitations to select large value of RC such as,

For large values of RC, quiescent drop is more; hence high biasing voltage is required to
maintain the quiescent collector current.

High values of RC require large chip area. So it is not possible to increase the value RC
beyond certain limit.
These difficulties are circumvented by using a current mirror as load in the place of RC.
+VCC
Q3
Q4
I
I1
v1
I2
VO
[ To next Stage]
Q2
Q1
v2
IQ
The current mirror circuit has the d.c resistance of order of few kilo ohms, as quiescent voltage
across it is a fraction of supply voltage and a current is in milliamperes. However since it acts as a
constant current source, its dynamic resistance (a.c) is very high, so a current mirror can be used as
a active load.
In above circuit, current mirror uses PNP transistors Q3 and Q4. Constant current IQ is obtained
from current mirror.
OPERATION:
Under quiescent condition, v1 = v2 = 0, from symmetry of Q1 and Q2, I1= I2=IQ/2 where base
currents are assumed to be neglected. Since Q3 and Q4 form a current mirror
I1= I2 = I. The load current IL entering the next stage is given by
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 51
IL= I1- I2 = 0
--------------------------- (A)
However when v1 increases over v2, current I1 increases where as I2 decreases, since
I1 + I2 = IQ (constant)
The load current is given by
IL= I - I2
( I1 = I)
IL= I1- I2
= gm.v1- gm.v2
= gm (v1- v2)
IL = gm.vd
--------------------------- (B)
Thus the circuit behaves as a Tran’s conductance amplifier.
16. Explain the term epitaxy and describe the epitaxial growth process?
Epitaxial growth:
[NOV/DEC 2010]
The first step in transistor fabrication is creation of the collector region. We normally require a low
resistivity path for the collector current. This is due to the fact that, the collector contact is
normally taken at the top, thus increasing the collector series resistance and the VCE(Sat) of the
device.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 52
The higher collector resistance is reduced by a process called buried layer as shown in figure. In
this arrangement, a heavily doped ‗N‘region is sandwiched between the N-type epitaxial layer and
P – type substrate. This
buried N+
layer provides a low resistance path in the active collector
region to the collector contact C. In effect, the buried layer provides a low resistance shunt path for
the flow of current.
For fabricating an NPN transistor, we begin with a P-type silicon substrate having a resistivity of
typically lQ-cm, corresponding to an acceptor ion concentration of 1.4 * 1015 atoms/cm3 . An oxide
mask with the necessary pattern for buried layer diffusion is prepared. This is followed by masking
and etching the oxide in the buried layer mask.
The N-type buried layer is now diffused into the substrate. A slow-diffusing material such as
arsenic or antimony us used, so that the buried layer will stay-put during subsequent diffusions. The
junction depth is typically a few microns, with sheet resistivity of around 20Q per square.
Then, an epitaxial layer of lightly doped N-silicon is grown on the P-type substrate by placing the
wafer in the furnace at 12000 C and introducing a gas containing phosphorus (donor impurity). The
resulting structure is shown in figure.
The subsequent diffusions are done in this epitaxial layer. All active and passive components are
formed on the thin N-layer epitaxial layer grown over the P-type substrate. Obtaining an epitaxial
layer of the proper thickness and doping with high crystal quality is perhaps the most formidable
challenge in bipolar device processing.
17. Describe in details the processing steps involved in the fabrication of monolithic IC?
Construction of a Monolithic Bipolar Transistor:
[Nov 2010]
The fabrication of a monolithic transistor includes the following steps.
1. Epitaxial growth
2. Oxidation
3. Photolithography
4. Isolation
5. Diffusion
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 53
6. Base diffusion
7. Emitter diffusion
8. Contact mask Aluminium
9. Metallization Passivation
The letters P and N in the figures refer to type of doping, and a minus (-) or plus (+) with P and N indicates
lighter or heavier doping respectively.
1. Epitaxial growth:
The first step in transistor fabrication is creation of the collector region. We normally require a low
resistivity path for the collector current. This is due to the fact that, the collector contact is normally taken at
the top, thus increasing the collector series resistance and the VCE(Sat) of the device.
The higher collector resistance is reduced by a process called buried layer as shown in figure. In this
arrangement, a heavily doped ‗N‘ region is sandwiched between the N-type epitaxial layer and P – type
substrate. This
buried N+ layer provides a low resistance path in the active collector. region to the
collector contact C. In effect, the buried layer provides a low resistance shunt path for the flow of current.
For fabricating an NPN transistor, we begin with a P-type silicon substrate having a resistivity of typically
lQ-cm, corresponding to an acceptor ion concentration of 1.4 * 1015 atoms/cm3 . An oxide mask with the
necessary pattern for buried layer diffusion is prepared. This is followed by masking and etching the oxide
in the buried layer mask.
The N-type buried layer is now diffused into the substrate. A slow-diffusing material such as arsenic or
antimony us used, so that the buried layer will stay-put during subsequent diffusions. The junction depth is
typically a few microns, with sheet resistivity of around 20Q per square.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 54
Then, an epitaxial layer of lightly doped N-silicon is grown on the P-type substrate by placing the wafer in
the furnace at 12000 C and introducing a gas containing phosphorus (donor impurity). The resulting structure
is shown in figure.
The subsequent diffusions are done in this epitaxial layer. All active and passive components are formed on
the thin N-layer epitaxial layer grown over the P-type substrate. Obtaining an epitaxial layer of the proper
thickness and doping with high crystal quality is perhaps the most formidable challenge in bipolar device
processing.
2. Oxidation:
As shown in figure, a thin layer of silicon dioxide (SiO2) is grown over the N-type layer by exposing
the silicon wafer to an oxygen atmosphere at about 10000 C.
3. Photolithography:
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 55
As shown in figure, the surface of the oxide is first covered with a thin uniform layer of photosensitive
emulsion (Photo resist). The mask, a black and white negative of the requied pattern, is placed over the
structure. When exposed to ultraviolet light, the photo resist under the transparent region of the mask
becomes poly-merized. The mask is then removed and the wafer is treated chemically that removes the
unexposed portions of the photoresist film.
The polymerized region is cured so that it becomes resistant to corrosion. Then the chip is dipped in an
etching solution of hydrofluoric acid which removes the oxide layer not protected by the polymerized
photoresist. This creates openings in the SiO2 layer through which P-type or N-type impurities can be
diffused using the isolation diffusion process as shown in figure. After diffusion of impurities, the
polymerized photoresist is removed with sulphuric acid and by a mechanical abrasion process.
4. Isolation Diffusion:
The integrated circuit contains many devices. Since a number of devices are to be fabricated on the
same IC chip, it becomes necessary to provide good isolation between various components and their
interconnections. The most important techniques for isolation are:
1. PN junction Isolation
2. Dielectric Isolation
In PN junction isolation technique, the P+ type impurities are selectively diffused into the N-type epitaxial
layer so that it touches the P-type substrate at the bottom. This method generated N-type isolation regions
surrounded by P-type moats. If the P-substrate is held at the most negative potential, the diodes will become
reverse-biased, thus providing isolation between these island .
The individual components are fabricated inside these islands. This method is very economical, and is the
most commonly used isolation method for general purpose integrated circuits. In dielectric isolation method,
a layer of solid dielectric such as silicon dioxide or ruby surrounds each component and this dielectric
provides isolation. The isolation is both physical and electrical. This method is very expensive due to
additional processing steps needed and this is mostly used for fabricating IC‘s required for special
application in military and aerospace.
The PN junction isolation diffusion method is shown in figure. The process take place in a furnace using
boron source. The diffusion depth must be atleast equal to the epitaxial thickness in order to obtain complete
isolation. Poor isolation results in device failures as all transistors might get shorted together. The N-type
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 56
island shown in figure forms the collector region of the NPN transistor. The heavily doped P-type regions
marked P+ are the isolation regions for the active and passive components that will be formed in the various
N-type islands of the epitaxial layer.
5 Base diffusion:
Formation of the base is a critical step in the construction of a bipolar transistor. The base must be aligned,
so that, during diffusion, it does not come into contact with either the isolation region or the buried layer.
Frequently, the base diffusion step is also used in parallel to fabricate diffused resistors for the circuit. The
value of these resistors depends on the diffusion conditions and the width of the opening made during
etching.
The base width influences the transistor parameters very strongly. Therefore, the base junction depth and
resistivity must be tightly controlled. The base sheet resistivity should be fairly high (200- 500Ω per square)
so that the base does not inject carriers into the emitter. For NPN transistor, the base is diffused in a furnace
using a boron source.
The diffusion process is done in two steps, pre deposition of dopants at 9000 C and driving them in at about
12000 C. The drive-in is done in an oxidizing ambience, so that oxide is grown over the base region for
subsequent fabrication steps. Figure shows that P-type base region of the transistor diffused in the N-type
island (collector region) using photolithography and isolation diffusion processes.
6. Emitter Diffusion:
Emitter Diffusion is the final step in the fabrication of the transistor. The emitter opening must lie wholly
within the base. Emitter masking not only opens windows for the emitter, but also for the contact point,
which provides a low resistivity ohmic contact path for the emitter terminal.The emitter diffusion is
normally a heavy N-type diffusion, producing low-resistivity layer that can inject charge easily into the
base. A Phosphorus source is commonly used so that the diffusion time id shortened and the previous layers
do not diffuse further.
The emitter is diffused into the base, so that the emitter junction depth very closely approaches the base
junction depth. The active base is then a P-region between these two junctions which can be made very
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 57
narrow by adjusting the emitter diffusion time. Various diffusion and drive in cycles can be used to fabricate
the emitter. The Resistivity of the emitter is usually not too critical.
The N-type emitter region of the transistor diffused into the P-type base region is shown below. However,
this is not needed to fabricate a
resistor where the resistivity of the P-type base region itself will serve
the purpose. In this way, an NPN transistor and a resistor are fabricated simultaneously.
7.Contact Mask:
After the fabrication of emitter, windows are etched into the N-type regions where contacts are to be made
for collector and emitter terminals. Heavily concentrated phosphorus N+ dopant is diffused into these
regions simultaneously.The reasons for the use of heavy N+ diffusion are explained as follows: Aluminium,
being a good conductor used for interconnection, is a P-type of impurity when used with silicon. Therefore,
it can produce an unwanted diode or rectifying contact with the lightly doped N-material. Introducing a high
concentration of N+ dopant caused the Si lattice at the surface semi-metallic. Thus the N+ layer makes a very
good ohmic contact with the Aluminium layer. This is done by the oxidation, photolithography and isolation
diffusion processes.
8.Metallization:
The IC chip is now complete with the active and passive devices, and the metal leads are to be formed for
making connections with the terminals of the devices. Aluminium is deposited over the entire wafer by
vacuum deposition. The thickness for single layer metal is 1μ m. Metallization is carried out by evaporating
aluminium over the entire surface and then selectively etching away aluminium to leave behind the desired
interconnection and bonding pads as shown in figure.
Metallization is done for making interconnection between the various components fabricated in an IC and
providing bonding pads around the circumference of the IC chip for later connection of wire
9. Passivation/ Assembly and Packaging:
Metallization is followed by passivation, in which an insulating and protective layer is deposited over the
whole device. This protects it against mechanical and chemical damage during subsequent processing steps.
Doped or undoped silicon oxide or silicon nitride, or some combination of them, are usually chosen for
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 58
passivation of layers. The layer is deposited by chemical vapour deposition (CVD) technique at a
temperature low enough not to harm the metallization.
Problems:
1. A 741C Op-Amp whose slew rate is 0.5V/μs is used as an inverting amplifier with a gain of 50.The
voltage gain Vs frequency curve of 741C is flat up to 20 kHz. What maximum peak to peak input
signal can be applied without distorting the output [Nov/ Dec 2003]
Given:
S = 0.5V/μs
f =20 kHz
Gain = 50
Solution:
Slew rate, S =
 Vm =
2fVm
V/μs
10 6
S
0.5 *10 6
= 3.98 V

2f 2 * 20 *10 3
Vo = 2 Vm = 2(3.98) = 7.96 V
We know that, Gain =
 Vi = V
o
gain
Vo
 3.98
Vi
50
 1.59mV
Hence for the output to be undistorted the maximum peak to peak input signal of 1.59mV can be applied.
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 59
2. A square wave peak-to-peak amplitude of 50mV has to be amplified to a peak-to-peak amplitude of
3V, with rise time of 4 μs or less. Can a 741 be used?
Solution:
Since the output is greater than 1V, Slew rate is limiting factor. Required Slew rate =
v
.But from
t
definition of rise time,
Δv = (0.9-0.1) 3 = 2.4 V
S=
v 2.4V
=
= 0.6 V/μs
t
4 s
Since the slew rate of 741 is 0.5 V/μs, it is too slow and cannot be used
LINEAR INTEGRATED CIRCUITS
EGSPEC/DEPT. OF ECE/II YEAR
Page 60
LINEAR INTEGRATED CIRCUITS
SCE/DEPT. OF ECE/II YEAR
Page 61