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4/29/2017 840946789 1/3 The Input Offset Voltage for MOSFET Differential Pairs Just as with the BJT differential pair, we find that some DC offset voltage is present, even when the differential input signal is zero! The reason is likewise the same as with the BJT differential pair—our transistors and resistors can never be made perfectly identical! For example, we find that the two MOSFETs will be slightly dissimilar (i.e., mismatched), such that: K1 K 2 and/or Vt 1 Vt 2 Using a similar analysis to that conducted for mismatched BJT differential pairs, we find that the input offset voltage due to mismatch in K is : V V K VOS GS t 2 K where K is the average value and K is the difference value of K1 and K2. 4/29/2017 840946789 2/3 Look at what this means! Similar to the BJT, the Input Offset Voltage VOS is proportional to the geometric (i.e., “percent”) error of K. However, note that this error is multiplied by one-half of the excess gate voltage VGS –Vt. The excess gate voltage is typically much larger than the BJT thermal voltage VT (a few volts versus 25 mV) ! As a result, the Input Offset Voltage for a MOSFET differential pair can be fairly large (e.g., >> 10 mV). Similarly, we find that the Input Offset Voltage created by a mismatch in threshold voltage Vt is: VOS Vt Yikes! In this case, the Input Offset Voltage is simply equal to the numeric difference in threshold voltages. This can likewise lead to a relatively large (>>10mV) value for VOS. Finally, we examine the effect of drain resistor mismatch. Again performing an analysis like we conducted for BJT differential pairs, we find that: V V R VOS GS t D 2 RD 4/29/2017 840946789 3/3 where RD and RD are again the average and difference values of RD1 and RD2. This result is no better than the previous ones. Again we see that the input offset voltage is proportional to the excess gate voltage, and thus again we find that VOS --this time due to drain resistor mismatch—can be relatively large for MOSFET differential pairs.