Download L-39: Numericals on PLDs

Q. Draw the interconnection of the 8x3 ROM and Explain it.
A block diagram of ROM is shown in the Figure below. It consists of k inputs and n outputs. The inputs
provide the address for the memory and the outputs give the data bits of the stored word which is selected
by the address. The number of words in a ROM is determined from the fact that k address input lines are
needed to specify 2 k words.
Figure 1 ROM Structure
The figure (a) and (b) shows two structure involving the fusible links of diode or transistors. The size of
the ROM shown here is 8x3 ROM. The unit consists of 8 words of 3 bits each. There are three input lines
that form the binary numbers from 0 through 7 for the address. The Figure shows the internal logic
construction of the ROM. The three inputs are decoded into 8 distinct outputs by means of a 3x8 decoder.
Each output of the decoder represents a memory address. The 8 outputs of the decoder are connected to
each of the eight OR gates.
Each OR gate must be considered as having 8 inputs. Each output of the decoder is connected to one of
the inputs of each OR gate. Since each OR gate has 8 input connections and there are 3 OR gates, the
ROM contains 8x3 = 24 internal connections. In general, a 2k x n ROM will have an internal k x 2k
decoder and n OR gates. Each OR gate has 2k inputs, which are connected to each of the outputs of the
decoder.
PLA Programmable logic array
Ex-1:
Implement the following equations using PLA
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Solution:
Programming the PLA
Figure 2: PLA Programming table
PLA Implementation is given in figure below:
Figure 3: PLA Implementation
Example-2: Magnitude Comparator implementation using PLA
A magnitude comparator is a
combinational circuit that compares two
numbers and displays the result as equal,
not equal, greater than, less than. The
block diagram of a magnitude
comparator shows the input output ports.
Figure 4: Block Diagram of Magnitude Comparator
The truth table is given below:
Input-2
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Input-1
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Output
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EQ
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
LT
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
GT
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
Figure 5: K-map solution of Magnitude comparator
K-Map solution of the output equations
Programming table for t56he PLA implementation of
the Magnitude comparator is shown below:
Figure-3 shows the PLA implementation of the
magnitude comparator. Here ABCD and its
complement act as the bus bar. The AND and the OR
plane both are programmable. The input side shows the
crosses at those input points which are required minterm
in the solution for the EQ, LT, GT equations. The OR
plane shows the cross points at those AND outputs
Figure 6: PLA Implementation
which are required in the solution are programmed in the OR plane and are shown by the cross
points.
Ex 3: Design a BCD to Excess-3 code converter using PLA
Solution Hint:1. Construct the truth table with 4-bit BCD input and 4-bit XS-3 output.
2. Simplify the output equations using K-Map or any other tool
3. Program both the input and output section of the PLA.
PROGRAMMABLE ARRAY LOGIC (PAL)
The programmable array logic (PAL) is a programmable logic device with a fixed OR array and a
programmable AND array. Because only the AND gates are programmable the PAL is easier to program,
but is not as flexible as the PLA. One of the outputs is connected to a buffer inverter gate and then fed
back into two inputs of the AND gates.
Ex-4: REALIZATION OF A COMBINATIONAL CIRCUIT USING PAL :Implement the following
functions using PAL
W (A,B,C,D) = Σ (2,12,13)
X (A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15)
Y (A,B,C,D) = Σ (0,2,3,4,5,6,7,8,10,11,15)
Z (A,B,C,D) = Σ (1,2,8,12,13)
Solution: Simplify the four functions to a minimum number of terms result in the following Boolean
functions
W=ABC’+A’B’CD’
X=A+BCD
Y=A’B+CD+B’D’
Z=ABC’+A’B’CD’+AC’D’+A’B’C’D =
W + AC’D’ + A’B’C’D.
The function for z has four product terms. The logical sum of two of these terms is equal to w. By using
w, it is possible to reduce the number of terms for z from four to three. The PAL Programming Table is
shown in Table
The table is divided into four sections with three product terms. The first two sections need only two
product terms to implement the Boolean function. The last section for output z needs four product terms.
Using the output from w, we can reduce the function to three terms.
The fuse map for the PAL as specified in the programming table is shown in fig below: