Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Introduction Programmic realisation PC PC ? BUS Micro controller RAM CPU ROM Timer PORT PORT ? Hardware realisation PCB with logical circuit composed of integral circuits. Own micro circuit Description Design Technology for designing Micro circuits Own micro circuit ASIC - Application Specific Integrated Circuit ? ASIC ASIC – Application Specific Integrated Circuit Pros: Cons: Cheaper to manufacture in case of large volumes; Security; Smaller number of components; Greater density of components decreases loss of energy and increases working speed. High cost of projecting and creating the prototype in case of small volumes; Long duration of introduction and creation of prototype; Difficult to alter Design could be: Full Custom Design – a special microcircuit is created for the product (CAD – Computer Aided Design, Silicon Compiler); Semicustom Design – ready-made blanks are the concrete part realising the necessary product is designed (gate arrays, standard cells). Programmablev logic Demands for the elements to be programmed: Small surface of the crystal; Low resistance at ON and large resistance at OFF Low capacity; Possibility to manufacture a large number of programming elements in the same technology as the rest of the matrix Programming technologies: Static RAM cells – flip-flops of static RAM Anti-fuse – burnable joints EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Programmable Read Only Memory) and Flash – ROM elements commanded by floating gate SRAM technology. SRAM trigger SRAM trigger MUX SRAM trigger Characteristics of the SRAM technology: Functional blocks and joints are commanded by SRAM flip-flops; Joint elements are located on the surface of the same crystal; Configuration is not a destructive process; Programming takes place after turning power on. It is possible to reconfigure while working. In order to configure while power is being turned on external device with memory is needed. Configuration device is kept at the device. SRAM elements are large (5 transistors) and they require power, information lines, ground and selection lines; It is possible to manufacture together with other logic in the same CMOS technology; The design of SRAM memory elements has been thoroughly studied. ANTI-FUSE technology. Metal Amorphous silicon Metal Characteristics of the Anti-Fuse technology: Modified CMOS technology and necessary stage for manufacturing separately; a very thin isolation layer is created between the conductors; Programming is destructive – burned joint is not restorable; Programming takes place at tension much higher than the power, thus auxiliary isolation layer is needed at many places; Impossible to read the configuration file; Suitable for manufacturing multiplexers EPROM-itechnology MOSFET – Metal Oxide Semiconductor Fielt Effect Transistor p-MOS Vgg Gate Silicon fixed gate Vss Vdd Silicon floating gate Source n Drain n p n-MOS Vgg Gate Silicon fixed gate Vss Vdd Silicon floating gate Source p Drain p n Characteristics of EPROM, EEPROM and Flash technologies: Compatible with standard CMOS technology; The process is not destructive; Scattering of charges as a drawback; In case of EEPROM and Flash technology it is possible to programme without splitting microcircuit Terminology. SPLD – Simple Programmable Logic Device o ROM – Read Only Memory o PAL – Programmable Array Logic o PLA – Programmable Logic Array o GAL – Generic Array Logic (Lattice) o PLD – Programmable Logic Device CPLD – Complex Programmable Logic Device o EPLD – Erasable Programmable Logic Device o EEPLD – Electrically Erasable Programmable Logic Device o MAX – Multiple Array matriX (Altera) FPGA – Field Programmable Gate Array o LCA – Logic Cell Array o pASIC – programmable ASIC (QuickLogic) o FLEX, APEX (Altera) o ACT (Actel) o ORCA (Lucent) o Virtex (Xilinx) MPGA – Mask Programmable Gate Array SPLD ja CPLD SPLD x1 x2 xn ... Buffer AND . . . OR y1 y2 ... ym CPLD Connection array PLA PLA PLA PLA PLA PLA PLA PLA PLA PLA PLA PLA PLA PLA PLA PLA Macrocell Logic Block FPGA - Field Programmable Gate Array S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell S/V block I/O Cell LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell S/V block I/O Cell LB Logic Block LB Logic Block LB Logic Block S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell S/V block I/O Cell Comparison of FPGA and MPGA . Characteristics of FPGA: Slower, Smaller density; Cheaper prototype; Large series are remarkably more expensive; Always possible to introduce flexible changes; Faster into manufacturing. Characteristics of MPGA: Faster; Larger density; Expensive prototype; Large series remarkably cheaper; Impossible to introduce flexible changes; Takes time to be introduced into manufacturing. Price MPGA FPGA Capacity of the series