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Programmable Logic Devices
Tulika Mitra
[email protected]
Copyright © 2001 Tulika Mitra
Embedded Systems Technology



Programmable Processors
Application Specific Processor (ASIP)
Single purpose hardware
2
Embedded System Technology

Differ in their customization for the problem at hand
Desired
functionality
General-purpose
processor
Vahid & Givargis
total = 0
for i = 1 to N loop
total += M[i]
end loop
Application-specific
processor
Single-purpose
hardware
3
General-purpose processors

Programmable device used in a
variety of applications


Features



Program memory
General datapath with large register file
and general ALU
User benefits



Also known as “microprocessor”
Low time-to-market and NRE costs
High flexibility
Example: Pentium, ARM, …
Vahid & Givargis
Controller
Datapath
Control
logic and
State register
Register
file
IR
PC
Program
memory
General
ALU
Data
memory
Assembly code
for:
total = 0
for i =1 to …
4
NRE and unit cost metrics

Unit cost


NRE cost (Non-Recurring Engineering cost)



the monetary cost of manufacturing each copy of the system,
excluding NRE cost
The one-time monetary cost of designing the system
total cost = NRE cost + unit cost * # of units
per-product cost
= total cost / # of units
= (NRE cost / # of units) + unit cost
Vahid & Givargis
5
Application-specific processors


Programmable processor optimized
for a particular class of applications Controller
having common characteristics
Control
logic and
Features
State register




Benefits


Vahid & Givargis
Program memory
Optimized datapath
Special functional units
Datapath
Registers
Custom
ALU
IR
PC
Program
memory
Data
memory
Some flexibility, good performance, sizeAssembly code
for:
and power
Example: DSP, Media Processor
total = 0
for i =1 to …
6
Single-purpose hardware

Digital circuit designed to execute
exactly one program


Features



coprocessor, accelerator
Contains components needed to
execute a single program
No program memory
Benefits



Vahid & Givargis
Fast
Low power
Small size
Controller
Datapath
Control
logic
index
total
State
register
+
Data
memory
7
IC technology

Three types of IC technologies



Vahid & Givargis
Full-custom/VLSI
Semi-custom ASIC (gate array and standard cell)
PLD (Programmable Logic Device)
8
Full-custom/VLSI

All layers are optimized for an embedded system’s
particular digital implementation




Benefits


Placing transistors
Sizing transistors
Routing wires
Excellent performance, small size, low power
Drawbacks

Vahid & Givargis
High NRE cost (e.g., $300k), long time-to-market
9
Semi-custom

Lower layers are fully or partially built


Benefits


Good performance, good size, less NRE cost than
a full-custom implementation (perhaps $10k to
$100k)
Drawbacks

Vahid & Givargis
Designers are left with routing of wires and maybe
placing some blocks
Still require weeks to months to develop
10
PLD (Programmable Logic Device)

All layers already exist




Benefits


Low NRE costs, almost instant IC availability
Drawbacks

Vahid & Givargis
Designers can purchase an IC
Connections on the IC are either created or
destroyed to implement desired functionality
Field-Programmable Gate Array (FPGA) very
popular
Bigger, expensive (perhaps $30 per unit), power
hungry, slower
11
Technology
Performance/
Cost
Time until
running
Time to high
performance
Time to change code
functionality
ASIC
Very High
Very Long Very Long
Impossible
FPGA
Medium
Medium
Long
Medium
ASIP/
DSP
High
Long
Long
Long
Generic
Low-Medium Very
Short
Not
Attainable
Very Short
Flexibility
Speed
Comparison
12
Roadmap





PROM
PLA
PAL
CPLD
FPGA
13
Reading

Digital Logic Circuit Analysis and Design by
Nelson, Nagle, Carrol, and Irwin : Chapter
5.3, 5.4, 5.5, 11.2

Architectures of FPGAs and CPLDs: A Tutorial
by Stephen Brown and Jonathan Rose [
Available on the web: check out the link from
lectures page]
14
PLD Definition

Programmable Logic Device (PLD):


An integrated circuit chip that can be configured
by end use to implement different digital hardware
Also known as “Field Programmable Logic Device
(FPLD) “
15
PLD Advantages


Nonrecurring engineering cost
Short design time
Less expensive at low
volume
PLD
ASIC
Volume
16
PLD Categorization
PLD
HCPLD
SPLD
High Capacity PLD
Simple PLD
PLA
PAL
Programmable Array Logic
CPLD
Complex PLD
FPGA
Field Programmable Gate Array
17
Programmable ROM (PROM)
N input
2
N
xM
ROM
M output
Address: N bits; Output word: M bits
ROM contains 2
N
words of M bits each
The input bits decide the particular word that becomes available
on output lines
18
Logic Diagram of 8x3 PROM
Sum of minterms
19
Combinational Circuit Implementation
using PROM
I0 I1 I2 F0 F1 F2
0 0
0 0
0 1
0 1 0 0
1 0 1 0
0 0 1 1
0 1
1 0
1 0
1 1 0 0
0 0 1 0
1 0 0 1
1 1
1 1
0 1 0 0
1 0 1 0
F0
F1
F2
20
PROM Types

Programmable PROM



Erasable PROM (EPROM)



Break links through current pulses
Write once, Read multiple times
Program with ultraviolet light
Write multiple times, Read multiple times
Electrically Erasable PROM (EEPROM)/ Flash
Memory


Program with electrical signal
Write multiple times, Read multiple times
21
PROM: Advantages and
Disadvantages



Widely used to implement functions with
large number of inputs and outputs
Design of control units (Micro-programmed
control units)
For combinational circuits with lots of don’t
care terms, PROM is a wastage of logic
resources
22
Programmable Logic Array
n x k links
k AND
gates
m OR gates
k X m links
m outputs
n inputs n x k links
Programmable AND array + programmable OR array
n x k x m PLA has 2n x k + k x m links
Sum of products
23
PLA 4 X 6 X 2
24
Logic Implementation with PLA



Finite number of AND gates => simplify
function to minimum number of product
terms
Number of literals in a product term is not
important since we have all the input
variables
Sharing of product terms between outputs
=> multiple-output minimization
25
Design with PLA
26
Programmable Array Logic (PAL)


Programmable AND array
Fixed OR array


Each output line permanently connected to a
specific set of product terms
Number of switching functions that can be
implemented with PAL are more limited than
PROM and PLA
27
PAL Logic Diagram
28
PAL Implications


Number of product terms per output >
number of product terms in each sum-ofproduct expression
No sharing of product terms between outputs
29
Design with PAL
30
Logic
Block
I/O
Logic
Block
Programmable
Interconnect
CPLD
Logic
Block
I/O
Logic
Block
31
CPLD Logic Block

Simple PLD






Inputs
Product-term array
Product term allocation function
Macro-cells (registers)
Logic blocks executes sum-of-product expressions
and stores the results in micro-cell registers
Programmable interconnects route signals to and
from logic blocks
32
Major CPLD Resources



Number of macro-cells per logic block
Number of inputs from programmable
interconnect to logic block
Number of product terms in logic block
33
Structure of FPGA (Xilinx)
Logic Block
I/O Block
Interconnect
34
Configurable Logic Block CLB
35
Logic Function



Implemented as look-up table (LUT)
K
K-input LUT corresponds to 2 x 1 bit
memory
K-input LUT can implement any k-input 1output logic function
36
Configuring FPGA



Configure CLB and IOB
Configure interconnect
Interconnect technology



SRAM
Anti-fuse (program once)
EPROM / EEPROM
37
Programming Technology
Name
Re-programmable
Volatile
EPROM
yes (out of circuit)
no
EEPROM
yes (in circuit)
no
SRAM
yes (in circuit)
yes
Antifuse
no
no
38
FPGA Applications






Glue Logic (replace SSI and MSI parts)
Rapid turnaround
Prototype design
Emulation
Custom computing
Dynamic reconfiguration
39
PLD Logic Capacity


SPLD: about 200 gates
CPLD



Altera FLEX (250K logic gates)
Xilinx XC9500
FPGA



Xilinx Vertex-E ( 3 million logic gates)
Xilinx Spartan (10K logic gates)
Altera
40
FPGA Design Flow
Design Entry
Design Implementation
Design Verification
FPGA Configuration
41
Design Entry
(DK1 in our case)
Schematic
HDL
Compile
Logic Equations
Minimize
Test vectors
Reduced
Logic Equations
(Netlist)
Simulation
42
Design Implementation


Input: Netlist Output: bitstream
Map the design onto FPGA resources



Break up the circuit so that each block has
maximum n inputs
NP-hard problem
However, optimal solution is not required
43
Design Implementation (Cont.)

Place: assigns logic blocks created during
mapping process to specific location on FPGA



Goal: minimize length of wires
Again NP-hard
Route: routes interconnect paths between
logic blocks

NP-hard
44
Design Implementation Techniques




Simulated annealing
Genetic algorithm
Mincut method
Heuristic method
45
Design Verification & FPGA
Configuration



Functional Simulation
Timing Simulation
Download bitstream into FPGA
46