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Programmable Logic Devices
Tulika Mitra
[email protected]
Copyright © 2001 Tulika Mitra
Embedded Systems Technology
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Programmable Processors
Application Specific Processor (ASIP)
Single purpose hardware
2
Embedded System Technology

Differ in their customization for the problem at hand
Desired
functionality
General-purpose
processor
Vahid & Givargis
total = 0
for i = 1 to N loop
total += M[i]
end loop
Application-specific
processor
Single-purpose
hardware
3
General-purpose processors

Programmable device used in a
variety of applications
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Features
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Program memory
General datapath with large register file
and general ALU
User benefits
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Also known as “microprocessor”
Low time-to-market and NRE costs
High flexibility
Example: Pentium, ARM, …
Vahid & Givargis
Controller
Datapath
Control
logic and
State register
Register
file
IR
PC
Program
memory
General
ALU
Data
memory
Assembly code
for:
total = 0
for i =1 to …
4
NRE and unit cost metrics
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Unit cost
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NRE cost (Non-Recurring Engineering cost)
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the monetary cost of manufacturing each copy of the system,
excluding NRE cost
The one-time monetary cost of designing the system
total cost = NRE cost + unit cost * # of units
per-product cost
= total cost / # of units
= (NRE cost / # of units) + unit cost
Vahid & Givargis
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Application-specific processors
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Programmable processor optimized
for a particular class of applications Controller
having common characteristics
Control
logic and
Features
State register
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Benefits

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Vahid & Givargis
Program memory
Optimized datapath
Special functional units
Datapath
Registers
Custom
ALU
IR
PC
Program
memory
Data
memory
Some flexibility, good performance, sizeAssembly code
for:
and power
Example: DSP, Media Processor
total = 0
for i =1 to …
6
Single-purpose hardware
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Digital circuit designed to execute
exactly one program
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Features
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coprocessor, accelerator
Contains components needed to
execute a single program
No program memory
Benefits



Vahid & Givargis
Fast
Low power
Small size
Controller
Datapath
Control
logic
index
total
State
register
+
Data
memory
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IC technology
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Three types of IC technologies
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Vahid & Givargis
Full-custom/VLSI
Semi-custom ASIC (gate array and standard cell)
PLD (Programmable Logic Device)
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Full-custom/VLSI
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All layers are optimized for an embedded system’s
particular digital implementation
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Benefits
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Placing transistors
Sizing transistors
Routing wires
Excellent performance, small size, low power
Drawbacks
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Vahid & Givargis
High NRE cost (e.g., $300k), long time-to-market
9
Semi-custom
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Lower layers are fully or partially built
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Benefits
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Good performance, good size, less NRE cost than
a full-custom implementation (perhaps $10k to
$100k)
Drawbacks

Vahid & Givargis
Designers are left with routing of wires and maybe
placing some blocks
Still require weeks to months to develop
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PLD (Programmable Logic Device)
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All layers already exist
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Benefits
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Low NRE costs, almost instant IC availability
Drawbacks
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Vahid & Givargis
Designers can purchase an IC
Connections on the IC are either created or
destroyed to implement desired functionality
Field-Programmable Gate Array (FPGA) very
popular
Bigger, expensive (perhaps $30 per unit), power
hungry, slower
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Technology
Performance/
Cost
Time until
running
Time to high
performance
Time to change code
functionality
ASIC
Very High
Very Long Very Long
Impossible
FPGA
Medium
Medium
Long
Medium
ASIP/
DSP
High
Long
Long
Long
Generic
Low-Medium Very
Short
Not
Attainable
Very Short
Flexibility
Speed
Comparison
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Roadmap
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PROM
PLA
PAL
CPLD
FPGA
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Reading
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Digital Logic Circuit Analysis and Design by
Nelson, Nagle, Carrol, and Irwin : Chapter
5.3, 5.4, 5.5, 11.2
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Architectures of FPGAs and CPLDs: A Tutorial
by Stephen Brown and Jonathan Rose [
Available on the web: check out the link from
lectures page]
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PLD Definition
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Programmable Logic Device (PLD):
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An integrated circuit chip that can be configured
by end use to implement different digital hardware
Also known as “Field Programmable Logic Device
(FPLD) “
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PLD Advantages
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Nonrecurring engineering cost
Short design time
Less expensive at low
volume
PLD
ASIC
Volume
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PLD Categorization
PLD
HCPLD
SPLD
High Capacity PLD
Simple PLD
PLA
PAL
Programmable Array Logic
CPLD
Complex PLD
FPGA
Field Programmable Gate Array
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Programmable ROM (PROM)
N input
2
N
xM
ROM
M output
Address: N bits; Output word: M bits
ROM contains 2
N
words of M bits each
The input bits decide the particular word that becomes available
on output lines
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Logic Diagram of 8x3 PROM
Sum of minterms
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Combinational Circuit Implementation
using PROM
I0 I1 I2 F0 F1 F2
0 0
0 0
0 1
0 1 0 0
1 0 1 0
0 0 1 1
0 1
1 0
1 0
1 1 0 0
0 0 1 0
1 0 0 1
1 1
1 1
0 1 0 0
1 0 1 0
F0
F1
F2
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PROM Types
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Programmable PROM
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Erasable PROM (EPROM)
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Break links through current pulses
Write once, Read multiple times
Program with ultraviolet light
Write multiple times, Read multiple times
Electrically Erasable PROM (EEPROM)/ Flash
Memory
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Program with electrical signal
Write multiple times, Read multiple times
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PROM: Advantages and
Disadvantages
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Widely used to implement functions with
large number of inputs and outputs
Design of control units (Micro-programmed
control units)
For combinational circuits with lots of don’t
care terms, PROM is a wastage of logic
resources
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Programmable Logic Array
n x k links
k AND
gates
m OR gates
k X m links
m outputs
n inputs n x k links
Programmable AND array + programmable OR array
n x k x m PLA has 2n x k + k x m links
Sum of products
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PLA 4 X 6 X 2
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Logic Implementation with PLA
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Finite number of AND gates => simplify
function to minimum number of product
terms
Number of literals in a product term is not
important since we have all the input
variables
Sharing of product terms between outputs
=> multiple-output minimization
25
Design with PLA
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Programmable Array Logic (PAL)
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Programmable AND array
Fixed OR array
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Each output line permanently connected to a
specific set of product terms
Number of switching functions that can be
implemented with PAL are more limited than
PROM and PLA
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PAL Logic Diagram
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PAL Implications
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Number of product terms per output >
number of product terms in each sum-ofproduct expression
No sharing of product terms between outputs
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Design with PAL
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Logic
Block
I/O
Logic
Block
Programmable
Interconnect
CPLD
Logic
Block
I/O
Logic
Block
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CPLD Logic Block
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Simple PLD
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Inputs
Product-term array
Product term allocation function
Macro-cells (registers)
Logic blocks executes sum-of-product expressions
and stores the results in micro-cell registers
Programmable interconnects route signals to and
from logic blocks
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Major CPLD Resources
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Number of macro-cells per logic block
Number of inputs from programmable
interconnect to logic block
Number of product terms in logic block
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Structure of FPGA (Xilinx)
Logic Block
I/O Block
Interconnect
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Configurable Logic Block CLB
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Logic Function
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Implemented as look-up table (LUT)
K
K-input LUT corresponds to 2 x 1 bit
memory
K-input LUT can implement any k-input 1output logic function
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Configuring FPGA
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Configure CLB and IOB
Configure interconnect
Interconnect technology
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SRAM
Anti-fuse (program once)
EPROM / EEPROM
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Programming Technology
Name
Re-programmable
Volatile
EPROM
yes (out of circuit)
no
EEPROM
yes (in circuit)
no
SRAM
yes (in circuit)
yes
Antifuse
no
no
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FPGA Applications
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Glue Logic (replace SSI and MSI parts)
Rapid turnaround
Prototype design
Emulation
Custom computing
Dynamic reconfiguration
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PLD Logic Capacity
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SPLD: about 200 gates
CPLD
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Altera FLEX (250K logic gates)
Xilinx XC9500
FPGA
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Xilinx Vertex-E ( 3 million logic gates)
Xilinx Spartan (10K logic gates)
Altera
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FPGA Design Flow
Design Entry
Design Implementation
Design Verification
FPGA Configuration
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Design Entry
(DK1 in our case)
Schematic
HDL
Compile
Logic Equations
Minimize
Test vectors
Reduced
Logic Equations
(Netlist)
Simulation
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Design Implementation
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Input: Netlist Output: bitstream
Map the design onto FPGA resources
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Break up the circuit so that each block has
maximum n inputs
NP-hard problem
However, optimal solution is not required
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Design Implementation (Cont.)
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Place: assigns logic blocks created during
mapping process to specific location on FPGA
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Goal: minimize length of wires
Again NP-hard
Route: routes interconnect paths between
logic blocks
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NP-hard
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Design Implementation Techniques
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Simulated annealing
Genetic algorithm
Mincut method
Heuristic method
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Design Verification & FPGA
Configuration
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Functional Simulation
Timing Simulation
Download bitstream into FPGA
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