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Lesson 2.4 Key Terms Introduction to Programmable Logic Devices (PLDs) Definition Term Complex PLD (CPLD) A digital device consisting of several programmable sections with internal interconnections between the sections. Compiler The process used by CPLD design software to interpret design information (such as a schematic or text file) and create required programming information for a CPLD. Design Entry The process of using software tools to describe the design requirements of a PLD. Design entry can be done by entering a schematic or a text file that describes the required digital function. Field Programmable Gate Array (FPGA) Class of PLDs that contain an array of more complex logic cells that can be very flexibly interconnected to implement high-level logic circuits. Fitting Assigning internal PLD circuitry, and input and output pins, to a PLD design. Integrated Circuit (IC) An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package. JTAG Port A four-wire interface specified by the Joint Test Action Group (JTAG) used for loading test data or programming data into a PLD installed in a circuit. JEDEC Joint Electron Device Engineering Council. JEDEC File An industry standard form of text file indicating which fuses are blown and which are intact in a programmable logic device. JTAG Joint Test Action Group. A standards body that developed the format for testing and programming devices while they are installed in a system. Programmable Logic Device (PLD) Digital integrated circuit that can be programmed by the user to implement any digital logic function. Programming Transferring design information from the computer running PLD design software to the actual PLD chip. © 2014 Project Lead The Way, Inc. Digital Electronics Lesson 2.4 Introduction to PLDs Key Terms – Page 1 Schematic Entry A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD. Simple PLD (SPLD) A PLD with a few hundred logic gates and possibly a few programmable macro cells available. Target Device The specific PLD for which a digital design is intended. TCK Test Clock. The JTAG signal that drives the JTAG downloading process from one state to the next. TDI Test Data In. In a JTAG port, the serial input data to a device. TDO TMS Test Data Out. In a JTAG port, the serial output data from a device. Test Mode Select. The JTAG signal that controls the downloading of test or programming data. © 2014 Project Lead The Way, Inc. Digital Electronics Lesson 2.4 Introduction to PLDs Key Terms – Page 2