Download Fast Pulse Width Modulation (FPWM) Technology for DC

Reduces the Output Voltage Fluctuation to Less Than Half at the Point
of a Rapid Load Change as Compared with the Conventional Method
TECHNICAL
Fast Pulse Width Modulation (FPWM) Technology
for DC-DC Converter, Featuring High-speed
Response with a Clock-Synchronized Comparator
Control method
ANALYSIS
The comparator control method achieves extremely stable output voltage
compared with the voltage/current control method for rapid changes of
the load current.
Furthermore, Fujitsu's proprietary technology (FPWM) enables the converter
to fully synchronize with the clock. This means that the electromagnetic
compatibility (EMC), particularly a self-jamming noise for wireless devices,
can be reduced.
a reference voltage. Therefore, the
changes can be reduced to less than
comparator control method features
half, as compared with the conventional
Fujitsu designed its power management
“high speed load transient response
method. This technology reduces the
ICs with a focus on multi-channel
characteristics”
. However, this method
EMC for wireless devices, improves the
features for portable digital devices.
has a problem which oscillation
power consumption for portable devices,
Fujitsu's clock-synchronized comparator
frequency changes according to input/
and meets the recent requirement for high
control method, the FPWM technology,
output condition or load current. The
voltage accuracy for the SOC. Furthermore,
can be employed in those products.
FPWM method is compatible with fully
a built-in Pulse Frequency Modulation
The comparator control method
synchronized to the clock and high speed
(PFM) function improves efficiency
performs switching operations by
load transient response characteristics.
under light loads, which is essential
changing the duty ratio every cycle, and
With this technology, voltage
for today's energy-efficient products.
comparing the output voltage against
fluctuation at the time of rapid load
Both stable-constant-voltage output
Introduction
and high-energy efficiency can be
realized with this technology.
Figure 1　Block Diagram
Features
DRVH
R Q
<Error Comp.>
Comp out
② VFB
FB
S
method
Drive
Logic
・High-speed load transient response
③ VSLOPE
Vin
Slope
VR
CLK
①
・Clock-synchronized comparator control
DRVL
Less than 20mV voltage fluctuation
with the change of 0 to 450mA/2μs
(output capacitance 10μF)
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Fast Pulse Width Modulation (FPWM) Technology
・Power supply voltage range:
frequency is stable. Therefore, this
Figure 2　Timing Diagram
2.9V to 5.5V
・Output voltage range: 0.7V to 1.4V
CLK
・Built-in PFM function
・E x t e r n a l p h a s e c o m p e n s a t i o n
components, not required
VFB
VSLOPE
・Built-in FET for output voltage discharge
VFB≒VR
③
High-side
FET gate
Pch
Low-side
FET gate
Nch
PFM function
In the automatic PFM/PWM switching
mode, this device operates either in
PFM or PWM mode, according to the
ILX
- 2 Amps
function
②
Comp out
・Capable of a maximum output current
・Buit-in Load-independent soft start
the design of wireless devices.
①
・Switching frequency: 3.0 MHz to 4.5 MHz
・Built-in over-current protection circuit
comparator control method simplifies
FET Fixed ON period at low side
load current.
In the PFM mode, the oscillation
frequency is reduced at light load to
improve efficiency, increasing the
・Ceramic capacitors can be used
battery life for portable devices.
FPWM (measured waveform)
Key Features
A block diagram is shown in Figure 1, a
timing chart in Figure 2, and the load
transient response characteristics of
Io=0ｍA → 450mA/2μs
Figure 3　Load-Transient response Characteristics
Vo（20mV/div DC）
FPWM (measured waveform)
21.2mV
Io=0ｍA → 450mA/2μs
21.2mV
Io：0mA⇔450mA/2μs
fosc=3MHz
L=1.5μH (multilayer)
Co=10μF
Io（200mA/div）
this method in Figure 3.
VIN=3.6V
Vo（20mV/div DC）
10μs
VIN=3.6V
Io：0mA⇔450mA/2μs
circuit monitors output current enabling
engineers to design a highly reliable
DC/DC converter.
L=1.5μH (multilayer)
Io（200mA/div）
control method
A built-in over-current protection
fosc=3MHz
Co=10μF
Clock-synchronized comparator
Various protection functions
Evaluation Board
Fujitsu provides an evaluation
10μs
This method enables stable operation
board for single-chip evaluation of the
by synchronizing with the internally
method.
generated clock. The method provides
ultra-high-speed response by periodically
Current mode (measured waveform)
＊The evaluation board does not support the
Io=0ｍA → 450mA/2μs
comparing and detecting the internal
slope voltage and the output voltage,
with simultaneous feedback to the
comparator. Highly accurate output
VIN=3.6V
Vo（20mV/div DC）
Current mode (measured waveform)
41.2mV
Io=0ｍA → 450mA/2μs
conventional comparator method is
unnecessary.
In addition, because of the clock-
PFM function.
Io：0mA⇔450mA/2μs
fosc=3MHz
L=1.5μH (multilayer)
Co=10μF
Io（200mA/div）
voltage is achieved because the
output ripple voltage required for the
■
Vo（20mV/div DC）
10μs
41.2mV
VIN=3.6V
Io：0mA⇔450mA/2μs
fosc=3MHz
L=1.5μH (multilayer)
Co=10μF
Io（200mA/div）
10μs
synchronized method, the higher
harmonic component of oscillated
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