Download Digital Examination - Philadelphia University Jordan

Form No. T651
Philadelphia University
Faculty of Engineering
Student Name:
Student Number:
Dept. of Communications and Electronics Engineering
Course Title: Digital Electronics & Techniques
Course No: 650344, 630330
Lecturer: Dr. Wagah F. Mohammad
Section:
This question is general: Tick (√) the correct answer.
1- If the electronic chip contains 104 devises, it is called.
 Large scale integration
 Very large scale integration
 Medium scale integration.
2- Periodic pulse waveform is a repetitive pulse with predetermined:
 Frequency.
 Voltage.
 Current
3- If the voltage across the capacitor is constant that means the current through the
capacitor is:
 Constant.
 Maximum.
 Zero.
4- Bipolar transistor operated in saturation region when the base –collector junction is:
 Reverse biased.
 Forward biased.
 Not biased.
5- Faster turn on of the transistor requires the value of Rb to be :
 Large.
 Small.
 Any value.
6- Choosing small value of the load resistor (Rc), the current that flow through the output
transistor is:
 Large.
 Small.
 Not changed
7- When the digital output is low, the current will flow:
 Outside the circuit (Sourcing current).
 Inside the circuit (Sinking Current).

No current will flow.
Vcc
8- At high output TTL too many loads
R2
causing larger drop across R2, T3and D
T3
thereby Voh is :
D
Vin
 Increased
Voh
 Decreased.
T4
 Not affected.
9- Unused inputs of NOR gates should be connected to the:
 Power supply.
 Used input.
 Left floating.
10- The job of top transistor (T3) in totem pole output is to provide a path for the output ;
 High impedance.
 Low impedance..
 None of the above
11- In order to increase the switching speed of MOSFET logic, the channel length must
be:
 Increased.
 Decreased.
 Not changed.
12- The number of transistors needed to build a dynamic-NMOS Inverter of n-input is:
 2n.
 n2.
 n + 2.
13- The advantages of connecting NEMOS & PEMOS in Transmission gate is to transmit:
 High level voltage.
 Entire input voltage.
 Zero level voltage.
14- Monostables multivibraters are a digital circuit has:
 No stable state.
 One stable state.
 Two stable states
15- The main disadvantage of dynamic storage cell memory is;
 Occupy large silicon area.
 Use complex circuitry.
 Loose data due to leakage.
 Use very simple circuitry.
16- Transmission CMOS gate is created by connecting NEMOS in parallel with PEMOS in
order to transmit:
 The high level voltage.
 The low level voltage.
 The entire level voltage.
17- The number of unique addresses of 210x8 ROM is:
 210 bits.
 10 bits.
 8 bits.
18- The duty cycle of monostables output is proportional to:
 Width of the input signal.
 External RC circuit.
 Internal RC circuit.
19- Nonretriggerable monostables respond to the input signal as long as the output in:
 Stable state.
 Quisistable state.
 Both states.
20- One of the disadvantages of binary-weighted Digital to analogue converter is:
 Non-weighted.
 Slow speed.
 Low resolution.
 High value of input resistances.
1- Calculate the minimum input voltage
for the transistor to be saturated. Suppose
Vbe=0.7 V, Vce=0.2 V, βmin=10 and Ϭ =0.6.
VCC=5 V
ICsat
0.8K
3K
Vin
IBsat
Vb
Β =10
es
at
VCC=5V
40K
Rext=4.7K
IOL
IIL1
Vo
TL1
IOLmax=4mA
Iext
2- Calculate the low fan out (Flow) of the
TTL open collector circuit, suppose
Vbe=0.7 V, Vce=0.3V:
3- Calculate the duty cycle of the 555
timer connected as an astable is:
Vin
T4
Vcc
2R
R
Cext
Discharge
555 Timer
Threshold
Trigger
Q
0utput
1- What are the advantages and disadvantages of binary encoded analogue to digital converter (B
E A/D C)? What is the digital output of the above converter of 4-bit correspond to 2.5 V input?
Suppose the reference voltage is 5 V. Calculate the resolution.
Question
This question is about MOSFET family;
Design and draw the following Boolean function using CMOS technology.
HINT: Draw the Karnouph map and minimize the function then use DeMorgans theory to draw
the final design.
F (A, B, C, D) = ∑ (0, 1, 2, 3, 6, 10, 12, 13, 14, 15)