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University of Portland School of Engineering 5000 N. Willamette Blvd. Portland, OR 97203-5798 Phone 503 943 7314 Fax 503 943 7316 Design Project RNG: Radiation-based Random Number Generator Team Members: Ashley Donahoo Colton Hamm Alex Brotherston Matt Johnson Industry Representatives: Mr. John Haner Faculty Advisors: Dr. VanDeGrift Dr. Hoffbeck Dr. Osterberg Other Contributers: Mr. Tony Chang UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: <TEAM LEADER”S NAME HERE> . . . . Revision History. . . Rev. Date Author . . Team 0.1 30 Oct 2010 FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 0.2 3 Nov 2010 Alex Brotherston 0.3 0.4 3 Nov 2010 3 Nov 2010 Colton Hamm Alex and Colton 0.5 0.51 0.9 0.91 5 Nov 2010 5 Nov 2010 5 Nov 2010 11 Nov 2010 Matt Johnson Colton Hamm Team Ashley Donahoo 0.911 0.912 14 Nov 2010 15 Nov 2010 Colton Hamm Alex and Colton .92 15 Nov 2010 Matt and Ashley .93 .95 .96 18 Nov 2010 19 Nov 2010 29 Nov 2010 Team Team Ashley UNIVERSITY OF PORTLAND PAGE II Reason for Changes Initial draft. Contains partial intro and Architecture diagram. Also added updated milestones. Completed development approach section and added preliminary mechanical component section. Added introduction Completed analog and user interface sections Architecture Added Added figure to test plan Edited document Made some initial edits to the whole document Addressed comments Addressed analog comments and added references Addressed the digital part of the document Addressed various comments Approved by advisors. Added risk to Risk section as requested by industry representative SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . . Table of Contents . . Introduction............................................................................................................................... 8 . . Design ....................................................................................................................................... 8 FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE III Architecture ........................................................................................................................ 8 User Interface Component ................................................................................................ 9 Power Switch............................................................................................................... 9 Hold Switch ................................................................................................................. 9 Reset Button ................................................................................................................ 9 Display ......................................................................................................................... 9 Analog Systems ................................................................................................................. 9 Pulse Generator ......................................................................................................... 10 Voltage Multiplier ..................................................................................................... 10 Voltage Divider ......................................................................................................... 11 Pulse Shaping ............................................................................................................ 11 Digital Systems ................................................................................................................ 11 Integrated Circuits............................................................................................................ 12 Mechanical Component................................................................................................... 14 Approach ................................................................................................................................ 14 System Test Plan .................................................................................................................... 15 Test #1: Pulse Generator ................................................................................................ 15 Test #2: Transformer. ..................................................................................................... 15 Test #3: High Voltage Supply........................................................................................ 16 Test #4: MOSIS Chip test 1 ........................................................................................... 16 Test #5: MOSIS Chip test 2 ........................................................................................... 16 Test #6: Display, Overall ................................................................................................ 17 UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . Test #7: Display, Seven-Segment Display. ................................................................... 17 . . Development Plan .................................................................................................................. 18 . . Assumptions ........................................................................................................................... 19 . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE IV Risks........................................................................................................................................ 19 Power Supply ................................................................................................................... 19 Milestones............................................................................................................................... 20 Customer Interview ......................................................................................................... 21 Functional Specification Draft .90 .................................................................................. 21 MOSIS Chip: Timer built and tested in B^2logic .......................................................... 21 Functional Specification Draft .95 .................................................................................. 21 Functional Specification Final ........................................................................................ 21 Simulate the Pulse Generator and Transformer in PSPICE: ......................................... 21 MOSIS Chip: Comparator built and tested in B^2logic ................................................ 22 Simulate the voltage multiplier in PSPICE .................................................................... 22 Deliver .edf file to Dr. Osterberg .................................................................................... 22 Design Document first draft Completed......................................................................... 22 MOSIS Memory tested and completed .......................................................................... 22 Simulate the pulse generator, transformer, and voltage multiplier interfacing in PSPICE .......................................................................................................................................... 22 Design Document version .95 Completed...................................................................... 22 .edf file testing completed ............................................................................................... 22 .edf file Completed and sent to Dr. Osterberg ................................................................ 22 Simulate the pulse generator, transformer, voltage multiplier, and load interfacing in PSPICE .......................................................................................................................................... 23 Design Document version 1.0 Completed...................................................................... 23 All parts ordered .............................................................................................................. 23 UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . pulse generator/transformer ........................................................ 23 Construct and test the . . prototype voltage multiplier ....................................................... 23 Construct and test the . . final voltage multiplier (w/ high voltage components) ............. 23 Construct and test the . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE V Test the interface between the pulse generator, transformer, and voltage multiplier ... 23 Final Report First Draft Completed ................................................................................ 23 Test the interface between the pulse generator, transformer, voltage multiplier and load .......................................................................................................................................... 23 Case built and the device completed............................................................................... 23 Final Report version .95 Completed ............................................................................... 24 Final Report 1.0 Approved .............................................................................................. 24 Founders Day Presentation Complete ............................................................................ 24 Final Budget ........................................................................................................................... 24 1.1 Output......................................................................................................................... 25 1.2 Serial Cable ................................................................................................................ 25 1.3 Oscillator .................................................................................................................... 25 1.4 Transformer ............................................................................................................... 25 1.5 Voltage Multiplier ..................................................................................................... 25 1.6 Sensing ....................................................................................................................... 25 1.7 Power Source ............................................................................................................. 25 Conclusions ............................................................................................................................ 25 References: ............................................................................................................................. 26 Appendix A: ........................................................................................................................... 27 555 Timer ............................................................................................................................... 27 Appendix B:............................................................................................................................ 28 Overall Schematic .................................................................................................................. 28 UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . List of Figures . . . Figure 1: Random Number Generator block diagram. ................................................................. 8 . . ..................................................................................................... 9 Figure 2: User Interface Layout FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE VI Figure 3: Analog Block Diagram................................................................................................. 10 Figure 4: PSPICE Layout of Analog Circuit ............................................................................... 10 Figure 5: MOSIS Digital Output Circuitry.................................................................................. 11 Figure 6: BCD to 7-segment decoder (left) and 7-segment display (right) ............................... 12 Figure 7: MOSIS Block Diagram ................................................................................................ 12 Figure 8: MOSIS B2logic Diagram ............................................................................................. 14 Figure 9: MOSIS Chip Test Circuit ............................................................................................. 17 Figure 10: Overall development process. .................................................................................... 18 Figure 11: Pin Layout of 555 Chip .............................................................................................. 27 Figure 12: Overall Schematic....................................................................................................... 28 UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . List of Tables . . . Table 1: Project risks and contingencies ...................................................................................... 19 . . Table 2: Milestones....................................................................................................................... 20 FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 7 Table 3: Final Budget ................................................................................................................... 24 Table 4: Pin Descriptions for 555 Chip ....................................................................................... 27 UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . . Introduction . . Chub is to design and construct a working prototype of a device that The overall goal of Team Oregon . based on the detection of radioactive particles. This is accomplished generates truly random numbers . the time between radiation events. by measuring and comparing FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 8 The system is composed of four major units; the radiation sensor, the high-voltage supply, the integrated circuit, and the display units. The radiation sensor is a Geiger–Müller tube, a device which creates a current spike at the output when ionizing radiation passes through it. This spike is then shaped into a pulse using resistors and capacitors. Once the pulse is shaped, it is sent to the logic unit, which is composed of an application-specific integrated circuit known as a MOSIS chip. The MOSIS chip uses timers to compare the time between radiation events. Based on these times, it produces a random bit. By combining 8 random bits, an 8-bit random number is created. The random number is displayed in decimal format using three 7-segment displays. This document contains both the high-level overview and detailed low-level design of both the analog and digital components of the random number generator. Also contained within this document are the test-cases for ensuring the device works as expected, as well as predicted budget and timeline for completion of the prototype device. This document is intended for use by the faculty of University of Portland, the members of Team Oregon Chub, the team’s industry representative, Mr. John Haner of Bonneville Power Administration, as well as fellow students in the Electrical Engineering/Computer Science Department. Design Architecture The Radiation Based Random Number Generator consists of five major components as shown below in Figure 1. These components detect radiation, record the time between radiation events and calculate a random number then display the number on seven segment displays. Figure 1: Random Number Generator block diagram. The high-voltage supply drives the Geiger tube, which requires 500 volts to detect radiation events. The Geiger tube then produces a momentary current spike when a radioactive event is detected. This spike is sent through pulse shaping circuitry to transform the signal into an appropriate input to the logic unit, which is a MOSIS chip. The MOSIS chip therefore receives logic 1 whenever a radiation event is detected. Based on the timing between these radiation events the MOSIS chip collects 8 random bits and outputs them in seven segment display format as well as 8 raw bits. The seven UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . segment displays will show.the random number in decimal format and 8 raw bits could be used for a serial/USB output to a computer. . . User Interface Component . . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 9 The user interface of the random number generator features three user inputs: a power switch, a hold switch, and a reset button. The output of the device is shown on a series of three 7-segment displays, as shown in the figure below. Figure 2: User Interface Layout Power Switch The power switch allows the user to activate or deactivate the device. Hold Switch The hold switch allows the user to freeze the output of the display. For more information on how this feature is used, see the Use Case section of the functional specification document. [1] Reset Button Pressing the reset button clears the MOSIS memory and resets the counters to zero. Display Three 7-segment displays show the most recently generated random number in decimal format. Analog Systems The analog system, as shown in Figures 3 and 4 below, provides the voltage necessary for the Geiger tube to detect ionizing radiation and the components to shape the output of the Geiger tube into a usable input for the MOSIS chip. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO FUNCTIONAL SPECIFICATIONS RNG . . . . . . . . . REV. 0.96 PAGE 10 Figure 3: Analog Block Diagram A 9 volt battery provides 9 volts DC to a 555 chip acting as an oscillator, creating a 9 volt square wave. The square wave is fed to the base of a P2907A transistor, which provides enough current to drive the transformer. The step-up transformer and voltage multiplier circuit raise the voltage to 500 V recommended for optimal Geiger tube performance. The Geiger tube generates an impulse when it detects a radioactive particle, which is sent through the pulse shaping circuit to create a clean signal for the MOSIS input. Figure 4: PSPICE Layout of Analog Circuit Pulse Generator A 555 chip is operated in astable mode in order to create 9 volt pulses at a desired frequency. To determine this frequency a value was chosen for R2 and C1, and a potentiometer used in place of R1. While monitoring the output of the voltage multiplier using an oscilloscope, R1 was changed until the measured output voltage matched the desired output voltage of 500 volts. The potentiometer was then removed from the circuit and replaced with a resistor of equal value. Voltage Multiplier The voltage multiplier circuit consists of three D1N4002 diodes and three .01 uF capacitors. The circuit amplifies the magnitude of sinusoidal input using passive components, and then rectifies the amplified sinusoid into a DC voltage. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . Voltage Divider . . The voltage divider .consists of a 10 Mohm and a 1.11 Mohm resistor, as recommended by the manufacturer of the .Geiger tube. . Pulse Shaping FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 11 A 50 pF capacitor will be used to clean the signal coming from the output of the Geiger tube to be sent to the MOSIS input. Digital Systems The digital systems of the Random Number Generator consist of the 7-segment decoders and the 7segment displays. The MOSIS chip has three BCD outputs which are then connected to three 7segment decoders. These decoders are then connected to three 7-segment displays as shown in Figure 5. This figure shows the basic inputs and outputs of the MOSIS Chip to the other digital systems. Figure 5: MOSIS Digital Output Circuitry Below is a picture of the BCD to 7-segment decoder and a 7-segment display. This allows for the output of the MOSIS chip to be able to display onto the 7-segment displays. The seven segment displays are what display the random number in decimal format. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO FUNCTIONAL SPECIFICATIONS RNG . . . . . . . . . REV. 0.96 PAGE 12 Figure 6: BCD to 7-segment decoder (left) and 7-segment display (right) Integrated Circuits Figure 7 shows the block diagram of the MOSIS chip. It shows all the basic inputs and outputs of the chip. Figure 7: MOSIS Block Diagram UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . . . The output from the analog .circuit is the input to the MOSIS along with a 555 clock signal. The 8-bit timers use the clock signal .to record the interval between voltage spikes from the Geiger tube. Each timer consists of eight T-flip . flops, allowing it to count from 0-255. The timers are controlled by a FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 13 Control Counter. This counter increments when it receives spikes from the Geiger tube. The first radiation event, “first spike” enables the first timer, to start counting. The second radiation event stops the first timer and enables the second timer to start counting. The third radiation event stops the second timer. Also, on the third spike the Control Counter resets, along with the first and second timers, and starts the process again. The process repeats every three pulses. Each of the 8 bits from the timers are compared to each other using a series of AND and OR gates. The most significant bits are compared first, with the circuitry cascading down to the least significant bit. The new random bit is a 1 if the first timer is less than the second timer, 0 if the first timer is larger than the second timer, and the bit is thrown out (not saved in memory) if there is a tie. On the third pulse (the Memory Selector selects (with a counter) the first memory slot (D-Flip Flop) and increments the current random bit into that slot. On the next third pulse the Memory Selector stores the new random bit in the second memory slot. This continues until all 8 positions are filled. There is another set of D-FFs before the output so the number only shows when it is complete. When the last position is filled the Memory selector increments the final series of D-FFs and stores that last bit. This outputs the new 8-bit random number. In the case where there is a tie between the timers, then it will take another pulse to generate the random bit. As a result of the extra pulse, it will take longer to generate the random number. Once the 8-bit random number is generated it goes through four bit conditional adders, in order to convert binary to BCD. This allows the outputs to be connected to three BCD to seven segment decoders and three seven segment displays. The random number is also directly outputted from the memory so that it can be used for a serial or a USB connection. Figure 8 shows the logic diagram of the MOSIS chip from B2logic.blt UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO FUNCTIONAL SPECIFICATIONS RNG . . . . . . . . . REV. 0.96 PAGE 14 Figure 8: MOSIS B2logic Diagram Mechanical Component The electrical components of the device, including the analog circuitry and the MOSIS chip, will be housed inside a Plexiglas casing. The exact size of the casing cannot be determined at this time, but it is expected that the device will be handheld. The casing will feature space for the electrical components and a standard 9 volt battery. The front of the case will contain the 7-segment display, power and hold switches, and reset button, as seen in Figure 2: User Interface Layout. Approach There have not been major decisions that have stood out in our design process; however there are a few smaller notable decisions. First off, the Geiger tube needs 500 volts to operate. Since it is operating at such a high voltage we decided to use a 9V battery as our power source. The Geiger tube does not need very much current so the 9V battery will be able to supply enough power while remaining safe. Another decision that we made was to use two timers in the MOSIS chip. These timers ultimately compare the interval between voltage spikes. One timer could have been used to count up and then down, however it was more convenient to implement two identical counters in B2Logic.blt. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . functionality to the generator. This was not absolutely necessary, but it The hold switch added more . user-friendly. This decision was made to allow the user to pause the allows the generator to be more . display so it does not display. a new number before the user is done with the old one. While the switch is on hold, the random bits. will still be generated. Once the hold switch is set to logic 0 the next random number will be displayed . if all 8-bits have been generated. FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 15 It was also decided to use seven-segment displays with a serial port upgrade for the output. The team was unsure if there would be time to implement an output to a computer, so the generator is designed to use seven-segment displays and also have an output which could be connected to a computer, in which the numbers would be written to a file. System Test Plan Test #1: Pulse Generator In this test, the user will determine if the pulse-generator component of the high-voltage power supply is functioning properly. Initial Conditions: 1. The device has a good 9v battery, and the power switch is in the ‘on’ position. Steps to run the test case: 1. The user measures the voltage drop across at pin 3 of the 555 timer using an oscilloscope. Expected behavior: The oscilloscope should display a square wave with a frequency of f=1/(ln(2)*C1*(R1+2*R2)), or 1.1 kHz. Test #2: Transformer In this test, the user will determine if the transformer in the high-voltage power supply is functioning properly. Initial Conditions: 1. The device has a good 9v battery, and the power switch is in the ‘on’ position. Steps to run the test case: 1. The user measures the voltage across the primary winding of the transformer using an oscilloscope. 2. The user measures the voltage across the secondary winding of the transformer using an oscilloscope. Expected behavior: The oscilloscope should display a waveform with amplitude of roughly 8.3 volts on the primary side, and a distorted sinusoidal waveform with amplitude of nearly 200 volts on the secondary side. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . Test #3: High Voltage Supply . . will determine if the high-voltage power supply is functioning In this test, the user . properly. . . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 16 Initial Conditions: 1. The output capacitor has been removed, and the Geiger tube has been replaced with a short circuit. 2. The device has a good 9v battery, and the power switch is in the ‘on’ position. Steps to run the test case: 1. The user measures the voltage drop across R5 using an oscilloscope with a 1.1Mohm probe. Expected behavior: The oscilloscope should show a dc voltage of roughly 45 volts. This is because when the Geiger tube is short-circuited, the 500 volt output of the high-voltage supply is being divided by the voltage divider circuit. An output of 45 volts across the 1.1Mohm resistor is equivalent to a 500 volt drop across the entire output. Test #4: MOSIS Chip test 1 In this test, the user will determine if the MOSIS chip is functioning correctly. Initial Conditions: 1. The high-voltage supply and Geiger tube have been removed, and the circuit shown in Figure 9 has been attached to the input pin of the MOSIS chip. 2. The device has a good 9v battery, and the power switch is in the ‘on’ position. Steps to run the test case: 1. The user taps the switch to simulate a radiation event. The switch is tapped again at 3 and 10 seconds after the initial simulated event. 2. The entire process is repeated 8 times. 3. A voltmeter is used to measure the voltage of the 8-bit serial output. Expected behavior: All pins should have an output indicating logic 0. Test #5: MOSIS Chip test 2 In this test, the user will determine if the MOSIS chip is functioning correctly. Initial Conditions: 1. The high-voltage supply and Geiger tube have been removed, and the circuit shown in Figure 9 has been attached to the input pin of the MOSIS chip. 2. The device has a good 9v battery, and the power switch is in the ‘on’ position. Steps to run the test case: 1. The user taps the switch to simulate a radiation event. The switch is tapped again at 7 and 10 seconds after the initial simulated event. 2. The entire process is repeated 8 times. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . is used to measure the voltage of the serial binary output pins. 3. A voltmeter . All pins should measure a voltage indicating logic 1. Expected behavior: . . . . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 17 Figure 9: MOSIS Chip Test Circuit Test #6: Display, Overall In this test, the user will determine if the display is working correctly. Initial Conditions: 1. The device has a fresh 9v battery, and the power switch is in the ‘on’ position. Steps to run the test case: 1. After letting the device produce at least one random number, the user activates the ‘hold’ switch, freezing the display. 2. A volt meter is used to measure the voltage of the pins. 3. The user converts the 8 bit binary number into a decimal number. Expected behavior: The number converted by the tester should match the number being displayed on the seven-segment displays. Test #7: Display, Seven-Segment Display. In this test, the user will determine if a segment of the seven-segment display is not functioning properly. Initial Conditions: 1. The device is in the off position, or the display is removed for easy testing. Steps to run the test case: UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . 1. The user.tests each segment of the display by applying an appropriate voltage to each of the . input pins. Expected behavior: . A voltage applied to an input pin should cause one segment to light up. If a segment.fails to light up, or if multiple segments light up, the display should be replaced . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 18 Development Plan The device will be taken from concept to reality in three main phases, as seen in the figure below: design, build, and integration. The bulk of the documentation requirements will be divided evenly among the team members to ensure no one person becomes overwhelmed. In general, the team of 4 will work on the design and implementation of the project in groups of two, which will allow us to check each other's work as we go, resulting in less editing and corrections later in the process. Colton and Alex are responsible for the analog aspects (left branch of Figure 8, below), while Ashley and Matt are responsible for MOSIS chip design along with the full display unit (right branch of Figure 8). The team will place priority on this project over other classes, and set personal deadlines well before official deadlines to keep the project consistently ahead of schedule. Figure 10: Overall development process. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . Design . . The design phase is estimated . to be August 30, 2010 to late October. This phase will consist primarily of device design .and documentation. The team will work together on the two important documents due during . this phase, the functional specification and design document. FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 19 Two members will focus on simulating the analog circuitry in PSPICE, while the other two will be tasked with the complete MOSIS chip design. Build The build phase is estimated to be late October, 2010 to mid-March, 2011. This phase will consist primarily of physically constructing and testing any aspects of the device not dependent on the MOSIS chip. Two team members will build and test the analog front end, while two members focus on the 7-segment display and device housing unit. Integration The integration phase is estimated to be mid-March, 2011 to April 12, 2011. This phase will consist of final device construction and documentation. The team will work together to integrate the analog front end, MOSIS chip, and display to create the finished product. We expect a lot of testing and debugging to occur during this phase. The team will also work together to create the final report. Assumptions See Team Chub’s Functional Specification Document for the assumptions of the project [1]. Risks Table 1: Project risks and contingencies Risk Power Supply Severity Likelihood Med Med Power Supply The power supply of this device is a 9-volt battery. The risk with using a battery is how long of a life it will have with the load connected. The 9-volt battery is responsible for powering the Geiger tube, the MOSIS, and the display. This is a lot of load for the small battery. In case the battery cannot supply to all parts of the device, a second 9-volt battery will be used or a separate power supply that can be plugged in will be used. See Team Chub’s Functional Specification Document for other risks of this project [1]. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . . Milestones . . set by Team Oregon Chub to keep the project going, and to mark the The following are milestones . progress being made each week. . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 20 Table 2: Milestones Number Description 1 2 Customer Interview Completed Functional Specification Draft .90 Completed MOSIS Chip: Timer built and tested in B^2logic Functional Specification Draft .95 Approved Functional Specification Final Approved Simulate the pulse generator and transformer interfacing in PSPICE MOSIS Chip: Comparator built and tested in B^2logic Simulate the voltage multiplier in PSPICE Deliver .edf file to Dr. Osterberg Design Document first draft Completed MOSIS Memory built and tested in B^2logic.blt Simulate the pulse generator, transformer, and voltage multiplier interfacing in PSPICE Design Document version .95 Completed .edf file testing completed .edf file completed and sent to Dr. Osterberg Simulate the pulse generator, transformer, voltage multiplier, and load interfacing in PSPICE Design Document version 1.0 Completed All parts ordered Construct and test the pulse generator/transformer Construct and test the prototype voltage multiplier Construct and test the final voltage multiplier 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING Completion Date Present 9-16-10 9-24-10 9-16-10 9-24-10 10-3-10 10-3-10 10-8-10 10-15-10 10-15-10 10-17-10 10-31-10 10-31-10 11-5-10 11-7-10 11-14-10 11-19-10 11-19-10 11-19-10 Target 10-8-10 10-4-10 9-29-10 10-16-10 10-28-10 10-28-10 11-5-10 11-5-10 11-14-10 11-19-10 11-21-10 11-21-10 11-30-10 12-3-10 12-17-10 1-31-10 2-14-11 2-21-11 CONTACT: ASHLEY DONAHOO . . . . (w/.high voltage components) . between the pulse generator, Test the interface . and voltage multiplier transformer, . Final Report First Draft Completed . FUNCTIONAL SPECIFICATIONS RNG 20 21 22 23 24 25 26 REV. 0.96 Test the interface between the pulse generator, transformer, voltage multiplier and load Case built and the device completed Final Report version .95 Completed Final Report 1.0 Approved Founders Day Presentation Complete PAGE 21 3-7-11 3-13-10 3-14-11 3-29-10 4-1-10 4-8-10 4-12-10 Customer Interview As part of the Senior Design Project Requirements, a customer was found and interviewed. Team Chub interviewed Tony Chang from Google. Tony works on Google Chrome, which uses random number generation in a variety of ways. Tony shared ways that he receives random numbers and how he uses them. It was very helpful in getting a customer’s perspective for the project. Functional Specification Draft .90 It was critical for Team Chub to have the functional specification draft .90 be done by September 24th in order to give Dr. VanDeGrift and Dr. Hoffbeck enough time to make comments on the document. MOSIS Chip: Timer built and tested in B^2logic The timer part of the MOSIS chip design will be built in B^2Logic.blt. Also, once the timer is constructed in B2logic.blt the .edf file will be sent to Dr. Osterberg in order to know the size of the chip layout thus far. Testing is incorporated with the design. Functional Specification Draft .95 The Industry Representative will review this draft. After draft .90 has been approved, it will automatically become draft .95. It is critical to have this done on time in order to give the Industry Representative plenty of time to review it. Functional Specification Final This is after the advisors, Dr. VanDeGrift and Dr. Hoffbeck, and the Industry Representative have both approved version 0.95. Once approved this final specification is called version 1.0 Simulate the Pulse Generator and Transformer in PSPICE: Simulate the circuit in PSPICE to provide help with the actual building and implementation of the analog circuit. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . built and tested in B^2logic MOSIS Chip: Comparator . . of the MOSIS chip design will be built in B^2logic.blt. This week the comparator part . . Simulate the voltage multiplier in PSPICE . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 22 Simulate a voltage multiplier in PSPICE to provide insight in how the circuit will work. Deliver .edf file to Dr. Osterberg Send initial .edf file to Dr. Osterberg. This is so he can keep track of how big the layout is getting for the MOSIS chip. Design Document first draft Completed The required design document first draft will be completed by November 5th to allow time for corrections and comments. MOSIS Memory tested and completed This week the memory needed in the MOSIS chip in order to store 8-bits will be constructed in B^2logic.blt. Simulate the pulse generator, transformer, and voltage multiplier interfacing in PSPICE Simulating the pulse generator, transformer, and voltage multiplier in PSPICE to understand how interfacing between each will work. Design Document version .95 Completed The Industry Representative will review this draft. After draft .90 has been approved, it will automatically become draft .95. It is critical to have this done on time in order to give the Industry Representative plenty of time to review it. .edf file testing completed Testing will be done on the .edf file constantly to ensure the correctness of the circuit. The testing must be done by November 19th. .edf file Completed and sent to Dr. Osterberg The final edf file of the MOSIS chip will be sent to Dr. Osterberg. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . transformer, voltage multiplier, and load interfacing in Simulate the pulse generator, . PSPICE . . The pulse generator, transformer, . voltage multiplier, and load interfacing will be done in PSPICE to help with the understanding.of how they will work in a real life scenario. FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 23 Design Document version 1.0 Completed This is the final version of the design document. This document is approved after Dr. VanDeGrift, Dr. Hoffbeck, and Mr. Haner have signed off on approval. All parts ordered All of the parts needed for the project will be ordered at this time. Construct and test the pulse generator/transformer The pulse generator and transformer will be constructed in Shiley 206. Construct and test the prototype voltage multiplier A prototype voltage multiplier will be constructed and tested in Shiley 206. Construct and test the final voltage multiplier (w/ high voltage components) The final voltage multiplier will be constructed with the high voltage components in Shiley 206. Test the interface between the pulse generator, transformer, and voltage multiplier The pulse generator, transformer, and voltage multiplier will be interfaced at this time after each component being tested several times. Final Report First Draft Completed The final report first draft will be completed at this date to ensure enough time to respond to all comments given. Test the interface between the pulse generator, transformer, voltage multiplier and load Connect the entire analog portion together. Doing this early allows for lots of time to debug the circuit if needed. Case built and the device completed The case will be built for the device, and the device will be interfaced with all components. This will leave two weeks of purely testing the device. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . Final Report version .95 .Completed . will review this draft. After draft .90 has been approved, it will The Industry Representative . automatically become draft..95. It is critical to have this done on time in order to give the Industry Representative plenty of time . to review it. FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 24 Final Report 1.0 Approved This is the final version of the final report. This document is approved after Dr. VanDeGrift, Dr. Hoffbeck, and Mr. Haner have signed off on approval. Founders Day Presentation Complete The Founders Day presentations are scheduled for April 12, 2011. Team Chub expects the project to be entirely completed and presentation well rehearsed by this date. Final Budget Table 3: Final Budget contains the budget for Team Chub’s project: Table 3: Final Budget Line Category 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Description Number Materials Seven Segment Display LED Serial Cable 555 Timer Resistor Capacitor 20-1 Step-up Transformer Diode, high voltage Capacitor, high voltage Geiger Tube 1Mohm Resistor 10Mohm Resistor Filtering Capacitor, high voltage 9V Battery TOTAL UNIVERSITY OF PORTLAND Rate Amount # of parts 3 1 1 1 2 2 1 3 3 1 1 1 $15 .95 $8 .95 .25 .45 10.95 .15 .45 93.95 .25 .25 $45 .95 $8 .95 .50 .90 10.95 .45 1.35 93.95 .25 .25 1 4 .45 4.00 .45 16.00 $179.95 SCHOOL OF ENGINEERING Subtotal CONTACT: ASHLEY DONAHOO . . . . . . 1.1 Output . . of the MOSIS chip, 3 seven segment displays will be required. An In order to show the 8- bit output . FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 25 LED will be required to show when a particle is detected. 1.2 Serial Cable A serial cable is required for the optional output expansion that allows the device to interface with a computer. 1.3 Oscillator A 555 timer, two standard resistors, and two standard capacitors are required for the oscillator. 1.4 Transformer A 20-1 step-up transformer is required to achieve the voltage needed for the Geiger tube to operate correctly. 1.5 Voltage Multiplier Three diodes and three capacitors are required to further amplify the voltage for the Geiger tube. 1.6 Sensing The sensing unit requires a Geiger tube, 1 Mohm resistor, 1 10Mohm resistor, and a high voltage filtering capacitor. 1.7 Power Source A 9-V battery is required to power the device. Conclusions The main goal of this project is to generate a truly random number. This is done by the use of a Geiger counter, MOSIS chip, and seven-segment displays. The Radiation-based Random Number Generator uses a 9-volt battery to power the Geiger counter, the Geiger counter signals the MOSIS chip when radiation is detected, and the MOSIS chip sends a number to the seven-segment displays. The purpose of the seven-segment display is to show the user the random number produced. The device will be portable, and contain two switches: reset and hold. The reset switch allows the user to reset the display and the hold switch stops the device from displaying any other numbers. The purpose of this project is to detect, calculate, and produce a truly random number. UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . . References: . . [1] Team Chub Functional Specification version 1.0 . http://teaching.up.edu/srdesign/AY11/Chub/documents.htm . FUNCTIONAL SPECIFICATIONS RNG UNIVERSITY OF PORTLAND REV. 0.96 SCHOOL OF ENGINEERING PAGE 26 CONTACT: ASHLEY DONAHOO FUNCTIONAL SPECIFICATIONS RNG Appendix A: 555 Timer . . . . . . . . . REV. 0.96 PAGE 27 Figure 11: Pin Layout of 555 Chip Table 4: Pin Descriptions for 555 Chip UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO . . . . . Appendix B: . Overall Schematic. . . This shows Team Chubs overall schematic for the Random Number Generator. FUNCTIONAL SPECIFICATIONS RNG REV. 0.96 PAGE 28 Figure 12: Overall Schematic UNIVERSITY OF PORTLAND SCHOOL OF ENGINEERING CONTACT: ASHLEY DONAHOO