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TABLE OF SPECIFICATIONS |ITS Gain| BW-3db Input Noise Current Power Dissipation |Gain Flatness| Group Delay Flatness Unit Ω GHz uA Specifications 1000 7.5 1 mW 50 ±0.5 dB ±10 % Hand Analysis 1238 15GHz ~0.7 28.2 --------------+6.5 Sim Results 1010 10GHz 1.5 (+3.4dB spec) 31mW +0.04 ±17 (+4dB spec) OVERALL CIRCUIT DESIGN STRATEGY The input stage of any broadband circuit is one of the most crucial components of the design. Noise generate in this input stage gets amplified with each additional stage that follows. Furthermore, bandwidth achieved in the input stage gets compromised with the introduction of additional capacitance and resistance from other stages. Choosing this stage was most probably the most challenging aspect of the project. One of the biggest hurdles to overcome in the design of a transimpedance amplifier is the pole generate by the photodiode capacitance. This requires designing a circuit with fairly low input resistance. For this reason, circuits that employ common gate topologies are typically used. I decided upon a regulated cascode for this reason, and because it applies feedback to generate an additional zero. This zero (variable with the value of R2) is capable of reducing the effect of the dominant pole Wp1. I tried to keep the value of R2 relatively low to prevent excessive peaking from the system. I appropriately had to adjust R1 to properly bias my circuit and meet specs. Achieving sizable gain is not extremely challenging. The challenging part is preserving that gain and operating bandwidth. A common association with high gain in one stage is a high Rout. However, Rout in shunt with parasitic capacitances also induces large poles. For this reason, I distributed my gain over a couple stages— each with fairly low output impedance. To compensate for this reduced output impedance, I applied a relatively large channel width as to maintain a high Gm (Gm*Rout remained high). I also optimized my circuit by employing the CherryHooper method of bandwidth enhancement. By adding capacitive degeneration in shunt with resistive degeneration, I was able to generate very specific zeros capable of the canceling the poles of each gain stage. My methodology is attached in the following pages. I lastly had to address the buffer. Because of the 50ohm load resistance, it was not easy preserving the gain of the system. To accommodate, I applied a common source buffer with a high current and low drain resistance. The low drain resistance in parallel with the load created a fairly low Rout and as a result a fairly weak pole at the output. The high current—satisfied by a very large channel width—increased Gm enough to compensate for this otherwise devastating loss of gain. Prior to designing, I tried to keep in mind that the number of capacitive stages should be kept to a minimum because of the phase shift capacitors induce. Additional capacitance in the system would increase group delay. Also, the addition of more stages would result in more power consumption. I tried to aspire for efficiency throughout the design while achieving the best specs possible. PROCESS/PROBLEM SOLVING I first tried to solve for my necessary equations in terms of variables. The following equations are what I derived. Parasitic and small signal values extracted from spice. 0 Frequency Gain Zero Frequency input impedance Mid Frequency input impedance Dominant Pole Approximation Cherry Cooper …. This is for solving M4 degeneration. M5 used R5, C5, R6, and C6 components but employed the same equation. Input Referred noise (neglecting the last two low gain stages) ANALYSIS AND DICREPANCIES As predicted, my gain increased with additional stage while my bandwidth became incrementally narrower. As my in equation predicted, noise exponentially grew with frequency after a certain point. My hand calculations over and underestimated my simulated results. This could be attributed to approximations I made for the sake of practicality as well as specifications accounted for by the simulation unbeknownst to me. I believe my input referred current noise was under what it should be because 1) I heavily approximated integration 2) I did not account for the last two stages of my design 3) I did not account for flickr noise. My bandwidth was overcompensated because again, I heavily approximated my poles—taking my primary pole mostly into account. I did find my low frequency gain, however, to be surprisingly accurate. As with most hand calculation, mine weren’t extremely accurate but were nonetheless helpful in understanding relations. SUGGESTIONS FOR IMPROVEMENT Peaking, while beneficial, contributes to group delay and subsequently hinders linearity of the system. To account for this, one should compromise bandwidth enhancement to better improve linearity if specifications are still satisfied. Another factor to consider is power dissipation of the system. My design consumed a staggering 30mW of the allotted 50mW. Past labs have required far less. Provided more time I would consider a more current efficient design—most probably involving changing the buffer. SPICE NETLIST * C:\Users\Jehan Sagadevan\Desktop\final.asc * Single Ended * AC Coupled M1 3 2 1 1 CMOSN l=65n w=13u Vdd Vdd 0 1.5 R1 Vdd 3 0.25k Cpd 1 0 .25pF I1 1 0 0 AC 1 0 C1 4 3 5p R2 Vdd 2 0.7k M2 2 1 0 0 CMOSN l=65n w=26u R3 1 0 1K M4 5 4 N001 N001 CMOSN l=65n w=26u R4 Vdd 5 0.4k Rb12 Vdd 4 100K Rb11 4 0 70k C2 6 5 5p RL Vout 0 50 M6 Vout 8 0 0 CMOSN l=65n w=52u R6 Vdd Vout 50 Rb32 Vdd 8 100K Rb31 8 0 100K R4s N001 0 50 C4s N001 0 0.5p M5 7 6 N002 N002 CMOSN l=65n w=26u R5 Vdd 7 0.4k Rb22 Vdd 6 100K Rb21 6 0 70k R5s N002 0 50 C5s N002 0 0.5p C3 8 7 5p .model NMOS NMOS .model PMOS PMOS .lib C:\program files\ltc\ltspiceiv\lib\cmp\standard.mos .MODEL CMOSN NMOS ( LEVEL +VERSION = 4.3 BINUNIT = 1 MOBMOD +CAPMOD = 2 EPSROX = 3.9 TOXE +NGATE = 3E20 RSH = 12.5 VTH0 +K1 = 0.3288759 K2 = -0.0158543 K3 +K3B = -2.1457348 W0 = 4.161996E-7 LPE0 8 +LPEB = -1.306998E-9 DVT0 = 0.0218474 DVT1 +DVT2 = -5.027235E-5 DVTP0 = 0 DVTP1 +DVT0W = 0 DVT1W = 0 DVT2W +U0 = 241.6713196 UA = 9.94508E-12 UB 18 +UC = -2.92397E-13 EU = 0.0187797 VSAT +A0 = 1.5477984 AGS = 0.7044088 B0 +B1 = 1E-7 KETA = -0.0534235 A1 +A2 = 1 WINT = 5.922209E-15 LINT 14 +DWG = -3.146107E-8 DWB = -1.244296E-8 VOFF +NFACTOR = 1.3762145 ETA0 = 9.143629E-3 ETAB +DSUB = 0.1733722 CIT = 0 CDSC = = = = = = 54 2 2.5E-9 0.4739505 40.7854328 7.081782E- = = = = 0.0775716 0 -0.032 3.607248E- = = = = 8.405035E4 9.45047E-8 0 3.007816E- = -0.1368755 = -1.7567E-3 = 2.4E-4 +CDSCB = 0 +PDIBLC1 = 1.953204E-3 +DROUT = 0.450015 +PVAG = 0 +RDSW = 233.1815191 +RDWMIN = 0 +PRWG = 1.0222753 +XPART = 0.5 +CGBO = 1E-12 +CJD = 1E-4 +MJSWS = 0.55 +CJSWD = 1E-10 +MJSWGS = 0.33 +PBSWS = 1 +PBSWGD = 1 +PRDSW = 1.0618694 +LKETA = 0.015308 +PVSAT = -200 19 +PUB = -1.64146E-20 .ac dec 100 100meg 10g .measure ns INTEG inoise .backanno .end cgs~ 8E-15 cgd~1.65E-15 CDSCD PDIBLC2 PSCBE1 DELTA RDSWMIN RSW PRWB CGSO CF MJS MJSWD CJSWGS MJSWGD PBSWD TNOM PK2 PKETA PU0 ) = = = = = = = = = = = = = = = = = = 0 0.01 7.984016E8 8.821768E-3 100 100 5.438136E-3 1.5E-10 0 0.9 0.55 5E-10 0.33 1 27 9.998152E-6 1.259635E-3 -5E-3 PCLM PDIBLCB PSCBE2 FPROUT RDW RSWMIN WR CGDO CJS MJD CJSWS CJSWGD PB PBSWGS PVTH0 WKETA PETA0 PUA = = = = = = = = = = = = = = = = = = 0.5083422 -1E-3 3E-6 0 100 0 1 1.5E-10 1E-4 0.9 1E-10 5E-10 1 1 1E-4 0.0106065 0 -1.64182E- --- Operating Point --V(3): V(2): V(1): V(vdd): V(4): V(5): V(n001): V(6): V(vout): V(8): V(7): V(n002): Id(M5): Ig(M5): Ib(M5): Is(M5): Id(M6): Ig(M6): Ib(M6): Is(M6): Id(M4): Ig(M4): Ib(M4): Is(M4): Id(M2): Ig(M2): Ib(M2): Is(M2): Id(M1): Ig(M1): Ib(M1): Is(M1): I(C3): I(C5s): I(C4s): I(C2): I(C1): I(Cpd): I(I1): I(R5s): I(Rb21): I(Rb22): I(R5): I(R4s): I(Rb31): I(Rb32): I(R6): I(Rl): I(Rb11): I(Rb12): I(R4): I(R3): I(R2): I(R1): I(Vdd): 1.36841 1.12661 0.526347 1.5 0.617647 1.12703 0.0466218 0.617647 0.596813 0.75 1.12703 0.0466218 0.000932435 0 -1.0804e-012 -0.000932435 0.00612746 0 -5.96814e-013 -0.00612746 0.000932435 0 -1.0804e-012 -0.000932435 0.000533415 0 -1.12661e-012 -0.000533415 0.000526347 0 -8.42067e-013 -0.000526347 -1.88513e-024 2.33109e-026 2.33109e-026 -2.54689e-024 -3.75383e-024 1.31587e-025 0 0.000932435 8.82353e-006 8.82353e-006 0.000932435 0.000932435 7.5e-006 7.5e-006 0.0180637 0.0119363 8.82353e-006 8.82353e-006 0.000932435 0.000526347 0.000533415 0.000526347 -0.0210135 voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage voltage device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current device_current SOURCES Sackinger, E.; Guggenbuhl, W.; , "A high-swing, high-impedance MOS cascode circuit," Solid-State Circuits, IEEE Journal of , vol.25, no.1, pp.289-298, Feb 1990 doi: 10.1109/4.50316 URL: http://ieeexplore.ieee.org.libproxy.usc.edu/stamp/stamp.jsp?tp=&a rnumber=50316&isnumber=1839 Sung Min Park; Hoi-Jun Yoo; , "1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications," Solid-State Circuits, IEEE Journal of , vol.39, no.1, pp. 112- 121, Jan. 2004 doi: 10.1109/JSSC.2003.820884 URL: http://ieeexplore.ieee.org.libproxy.usc.edu/stamp/stamp.jsp?tp=&a rnumber=1261293&isnumber=28187 Class notes! EE448 FALL 2012 Final Project: Design of a Broadband Transimpedance Amplifier Jehan Sagadevan 9501-3286-58