Download Novel sampling algorithm for dsp controlled 2 kW PFC converter

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 2, MARCH 2001
217
Novel Sampling Algorithm for DSP Controlled 2 kW
PFC Converter
Jinghai Zhou, Zhengyu Lu, Zhengyu Lin, Yuancheng Ren, Zhaoming Qian, Senior Member, IEEE, and
Yousheng Wang
Abstract—This paper proposes a novel sampling algorithm for
digital signal processing (DSP) controlled 2 kW power factor correction (PFCs) converters, which can improve switching noise immunity greatly in average-current-control power supplies. Based
on the newly developed DSP chip TMS320F240, a 2 kW PFC stage
is implemented. The novel sampling algorithm shows great advantages when the converter operates at a frequency above 30 kHz.
Index Terms—Digital signal processing, power factor correction,
sampling algorithm.
I. INTRODUCTION
D
IGITAL signal processing (DSP) has been widely used in
telecommunications, intelligent control, and motion control etc. Because of its high speed computation ability, high
reliability, and cost reduction, DSP is expected to be applied
in switching mode power supplies, such as dc–dc converters,
power factor correction (PFC) converters, and high frequency
PWM inverters etc. [1]–[4]. Compared to analog control [5],
[6] the DSP solution can add a PFC stage to power electronics
system without an extra control chip. It is recognized that in
these applications, the switching frequency is usually above 20
kHz in order to eliminate the acoustic noise and to increase the
power density. Most of DSP chips can successfully deal with
such a frequency range if the duration of sampling and A/D conversion is not concerned. However, it is necessary to sample the
analog voltage and current to realize the proper feedback control
in these applications; moreover, the sampling speed is greatly
limited by the A/D conversion speed of DSP chips which can
not be easily abbreviated.
Based on the traditional control circuits of PFC converters,
the implementation of such function by DSP is proposed, the
conventional single sampling in one period (SSOP) method
in average current-mode control is discussed in detail, and a
novel sampling algorithm is proposed in this paper that can
improve the switching noise immunity greatly. A 2 kW PFC
stage based on the newly developed DSP chip TMS320F240
is implemented.
Manuscript received January 17, 2000; revised December 12, 2000. This
work was supported by the Zhejiang Province Academician Fund. Recommended by Associate Editor J. Qian.
J. Zhou and Y. Ren were with the Electrical Engineering College, Zhejiang
University, Hangzhou 310027, China. They are now with the Center for Power
Electronics Systems, Virginia Polytechnic Institute and State University,
Blacksburg, VA 24061 USA.
Z. Lu, Z. Lin, Z. Qian, and Y. Wang are with the Electrical Engineering College, Zhejiang University, Hangzhou 310027, China (e-mail:
[email protected]).
Publisher Item Identifier S 0885-8993(01)02191-3.
II. PRINCIPLE
CONTROL STRATEGY
DSP-BASED PFC
OF THE
OF
The system diagram and DSP control stage of the PFC converter is shown in Fig. 1. A boost topology is adopted to obtain
high power factor. The converter must control the input current
and the output voltage
both. The current loop is proso that the input to
grammed by the rectified line voltage
the converter will appear to be resistive. The output voltage
is controlled by changing the average amplitude of the current
. A multiplier creates the current proprogramming signal
by multiplying the rectified line voltage
gramming signal
with the output voltage of the voltage compensator EA1
in voltage loop.
In order to realize the digital control in the proposed PFC
converter, the discrete expressions of the transfer function is
required. For a convenient purpose, Laplace transformation
is used in initial step. According to Fig. 1(a), the continuous
transfer function of voltage compensator EA1 can be expressed
as
(1)
where
Considering the first order sampling and holding effect, (1) becomes
(2)
The transfer function in discrete expression form is derived then
(3)
,
where
and is the sequence number of sampling. From (3), it is obvious that the output voltage of the voltage compensator EA1 in
the voltage loop at the present sampling period is determined by
, as given by
its previous value and
0885–8993/01$10.00 © 2001 IEEE
(4)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 2, MARCH 2001
(a)
(b)
Fig. 1.
(a) System diagram and (b) DSP control stage of PFC converter.
Similarly, the transfer function of the compensator EA2 in the
current loop can be derived according to Fig. 1(a)
(5)
, and
where
tion in discrete expression is
. So the transfer func-
(6)
Fig.1(b) is the control stage based on a DSP chip. Three main
electrical values are sampled: inductor current , rectified input
and output voltage
. All these values are samvoltage
pled and then converted into digital ones, which participate in
the succeeding computation process of the DSP. Among these
three signals, the two voltage signals are mainly low frequency
signals compared with the switching frequency. However, it is
strongly recommended that the inductor current be fed back instantaneously, which can be easily implemented in an analog
controller. Because of speed limitation of sampling and A/D
conversion, it seems impossible to meet this requirement in digital signal processing. In the practical sampling algorithm, the
present sampled signal is used to calculate the pulse width of
the succeeding period. Such SSOP method might be suitable
for average current-mode control and will be discussed in detail
in Section III.
III. DRAWBACKS OF SSOP METHOD
It is well known that in a typical PFC design with an analog
control chip such as UC3854, the inductor current should be
real-time sensed with a resistor [3], [6]. For a digital controlled
PFC, SSOP makes the controller more sensitive to the noise
ZHOU et al.: NOVEL SAMPLING ALGORITHM FOR DSP CONTROLLED 2 kW PFC CONVERTER
219
(a)
(a)
Fig. 2.
(b)
(b)
Inductor current with high frequency noises. (a) 10 s/div. (b) 5A/div.
(c)
Fig. 4. Three sampling modes when varies. (a) T > T
. (c) T < T
.
T < T
=
+
+
. (b)
Fig. 3. Minimum ontime versus switching frequency at different line voltage.
than its analog counterpart. A high peak often appears at the
switching point due to switching noise coupled to the current
sensor, which stimulates oscillations for a considerable period
(Fig. 2). All these noises make difficulties to keep system proper
operation. The best solution is to adjust the sampling point to
keep away from the switching point and its succeeding oscillations. On the other hand, the applied DSP chips limit the speeds
of sampling and A/D conversion, for example, TMS320F240’s
minimum sampling and A/D time are 1 s and 6.5 s, respectively [7]. During each 1 s sampling period, any switching
noise may cause system instability.
Based on the above analysis, the only possible sampling solution is to use SSOP method. By doing so, new problems happen:
how can we decide a fixed sampling point in each switching
cycle and how can the conditions mentioned above be satisfied
all the time? In PFC applications, things become even worse.
The input current has to follow the sinusoidal input voltage and
the output dc voltage has to be kept constant. Therefore, PWM
duty ratio has to change with a wide range. The duty ratio varies
from near unity to a minimum value while sinusoidal ac voltage
Fig. 5. Flow chart of the proposed algorithm.
varies from zero to peak value. The minimum duty ratio is given
by
(7)
Usually, for a universal input voltage PFC converter, its output
voltage is designed to be around 385 V. For 110 V line input
will not be a problem. However, for 220 V line
voltage,
is 0.12–0.22 only. If considering 10% main
input voltage,
will decrease further.
voltage variation,
to unity at each line
Since the duty ratio varies from
cycle, it may be possible to keep away from switching noise if
the sampling process finishes within on-time. However, for PFC
is too small to be satisfied. As a rewith a high line voltage,
sult, the on-time of the power switch becomes the main limitation factor of increasing switching frequency in DSP-controlled
PFC converter. Fig.3 shows the minimum on-time as a function
220
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 2, MARCH 2001
(a)
(b)
(c)
Fig. 6. Waveforms of the inductor current under three sampling modes (5 s/div, 5 A/div). (a) T > T
.
T
+
of the switching frequency at different line voltages. Because of
the oscillation, when the ontime decreases to several microseconds, it is very difficult to sample the current properly during the
ontime period. It is impossible to decide a fixed point meeting
above requirements within the entire line cycle.
IV. PRINCIPLE OF THE PROPOSED SAMPLING ALGORITHM
Because of its strong computation ability, DSP can eliminate the drawbacks mentioned above by using a simple algorithm. Assume that the circuit operates at the fixed frequency
, the switching noise oscillation maintains for a pe, and the sampling period is
. The value
should
riod
ensure cover the varying parasitic parameters in power train.
+
. (b) T < T
=
. (c) T < T
The following requirements must be satisfied to guarantee the
immunity to the switching noise.
1) No sampling happens during the
interval after the
switch turns on or off.
interval
2) No switching transition happens during the
after the sampling occurs as any disturbance may cause
wrong sampling results.
Considering the above conditions, two candidate sampling
and
are defined as follows:
moments
(8)
(9)
and
are relatively fixed
It should be noted that both
and
are determined. As result, domain
as soon as
ZHOU et al.: NOVEL SAMPLING ALGORITHM FOR DSP CONTROLLED 2 kW PFC CONVERTER
221
(13)
From (12) and (13), we have
(14)
The above conversion process is illustrated as a flow chart
shown in Fig. 5. By this conversion, the sampled data immunized from switching noise are equivalent to the value obtained
from SSOP method.
V. EXPERIMENTAL IMPLEMENTATIONS AND RESULTS
Fig. 7. Input line voltage and current of the proposed PFC stage. Outer: V ,
100 V/div. Inner: I , 10A/div. Time-base: 5ms/div.
stability analysis can be applied to the controller. A maximal
switching frequency can be calculated as
(10)
was calculated from the
Since the temporal pulse width
sampling value obtained one cycle before, the proper sampling
is greater than
time is decided according to whether
. If
is greater than
, as shown in Fig. 4(a),
is the appropriate sampling point and vice-versa.
is sampled. However,
If
can not be used to calculate pulse width directly since there
and
, which can not be
is an error between
eliminated through the integration algorithm in the current comfrom
pensation loop. So it is necessary to evaluate
, the more accurate value in this period. In order to con, two situations need to be considered, shown
vert into
in Fig. 4(b)–(c).
1)
In this situation, two candidate-sampling moments are
both located at the off-time of the switching cycle as
shown in Fig. 4(b). The difference between two sampling
results is
(11)
A 2 kW PFC stage by using proposed sampling algorithm
is successfully implemented. A switching frequency of 33 kHz
is selected so as to improve efficiency and to avoid acoustic
noise. The DSP chip TMS320F240 is used as a controller, whose
is approximately one mimaximum sampling duration
after each switching trancrosecond. The oscillation period
sition is about 6 microseconds. According to (8) and (9), the
and
are chosen as 6 s and 13 s,
sampling points
respectively. Input and out put voltages are 220–240 V and
400 V , respectively. The parameters of components are listed
as follows:
Boost switch : two IRFP460 devices in parallel;
Diode : HFA30PA60C;
750 H, iron powder ring core;
Inductor :
470 F/450 V;
Capacitor :
load resistor : 80 .
Fig.6 shows the waveforms of the inductor current in three
different circumstances. The input line voltage and input current are shown in Fig. 7. The system exhibits high immunity to
the switching noise. The measured total harmonic distortion of
the line input current is 6.4% and the measured power factor is
higher than 0.98.
VI. CONCLUSION
A novel sampling algorithm for DSP controlled PFC stage
is proposed. The method is suitable for average-current-control mode. It saves a lot of system resources compared to the
real-time sampling and maintains good performance. The saved
resources then can be utilized to control the succeeding dc–dc
or dc–ac stages and one-DSP chip controlled system becomes
feasible. The proposed PFC stage is implemented successfully,
and the one-chip solution cuts down the total hardware cost to
the minimum level.
REFERENCES
2)
In this situation, two candidate-sampling moments are
located at the on-time and off-time of the switch , respectively, as shown in Fig. 4(c). The following equations
can be obtained:
(12)
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 16, NO. 2, MARCH 2001
[3] S. J. Park and H.-W. Park, “Development of a high performance single
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Jinghai Zhou received the B.S. and M.S. degrees
in electrical engineering from Zhejiang University,
Hangzhou, China, in 1995 and 1998, respectively,
and is now pursuing the Ph.D. degree in electrical
engineering at the Virginia Polytechnic Institute and
State University, Blacksburg.
From 1996 to 2000, he did research in the area
of power electronics in lighting at Zhejiang University, where he was involved in several industry-sponsored research projects. His main research interests
include designing electronic ballast for HID lamps,
power factor correction techniques, and high-frequency power converter topologies. He is the primary author for several international conference papers. His
research area is on electronic ballast.
Zhengyu Lu received the B.S. degree in industrial
automatic control from Sea & River University,
China, in 1982 and the Ph.D. degree in power
electronics from Zhejiang University, Hangzhou,
China, in 1987.
From 1996 to 1998, he was a visiting scholar and
researcher at the University of Birmingham, and
Imperial College, London, U.K. He is a Professor
with Zhejiang University and Deputy Director of the
China National Power Electronics Laboratory, and
Deputy Director of the Power Electronics Institute,
Zhejiang University, China. Since 1982, he has been involved in teaching and
research work on power electronic devices and power converters for almost 20
years with the Zhejiang University of China. Now, his main research interests
include DSP control in power electronics, EMC in power electronics, and
active power filter.
Zhengyu Lin was born in Hangzhou, China, in April
1976. He received the B.S. degree in electrical engineering from Zhejiang University, Hangzhou, China,
in 1998 where he is now pursuing the M.S. degree in
electrical engineering.
His main research interests include DSP control in
power electronics and inverter control techniques.
Yuancheng Ren was born in Sichuan, China, in Oct.
1975. He received the B.S. and M.S. degrees from
Zhejiang University, Hangzhou, China, in 1997 and
2000, respectively, and is currently pursuing the Ph.D
degree at the Center for Power Electronics Systems
(CPES), Virginia Polytechnic Institute and State University (Virginia Tech), Blacksburg.
He is a Research Assistant with the Center for
Power Electronics Systems (CPES), Virginia Tech.
His research interests are switching power supplies,
resonant power conversion, and high power factor
correction.
Zhaoming Qian (SM’92) received the B.S. degree
in radio engineering from the Electrical Engineering
Department, Zhejiang University, Hangzhou, China,
in 1961 and the Ph.D. degree in applied science
from the Catholic University of Leuven and the
Interuniversity Microelectronics Center (IMEC),
Leuven, Belgium, in 1989.
Since 1961, he has been teaching and doing
research work on electronics, electronic measurements, photovoltaic, and power electronics for
almost 40 years at the Zhejiang University of China.
He was promoted to Professor of the Electrical Engineering Department,
Zhejiang University, in 1992. He has been the Director of the Power Electronics
Research Institute. He is currently the Deputy Director of National Engineering
Research Center for Applied Power Electronics, Zhejiang University, and the
Deputy Director of the Scientific Committee, National Key Laboratory of
Power Electronics, Zhejiang University. His main professional interests include
power electronics and its industrial applications, as well as EMC in power
electronics etc.
Dr. Qian received the Excellent Education Awards from the China Education
Commission and from Zhejiang University in 1993, 1997, and 1999, respectively, the Science and Technology Development Award from the China Education Commission, in 1999, and several Excellent Paper Awards. He has been
serving as a Vice-Chairman of IEEE PELS Beijing Chapter since 1994.
Yousheng Wang was born in Hangzhou, China, in
August 1928. He received the B.S. degree from the
Electrical Engineering Department, Zhejiang University, Hangzhou, China, in 1950.
Since 1950, he has been doing teaching and
research work on power electronics in Zhejiang
University. He was promoted to Professor of
the Electrical Engineering Department, Zhejiang
University, in 1975, and as an Academician of the
Chinese Academy of Engineering in 1994. He is
currently the Director of Technique Committee,
National Engineering Research Center for Applied Power Electronics, Zhejiang
University. In 1958, he joined the research work on double-water inner-cooled
generator as a leading member. In 1970, he led the research group that worked
on high-power parallel resonant mode thyristor medium frequency (MF)
induction heating power source that is the first one in China. Afterward, he
led the research group worked on control technology for MF induction heating
powers source, and extended its applications to heat treatment, jointing, etc.
His main research interests include induction heating power systems, power
electronic devices, and industrial power electronic equipment.
Mr. Wang received the National Invention First Class Award and the National
Science and Technology Progress First Class Award.