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Linear Current Starved Delay Element ICEST 2005, Niš Goran S. Jovanović and Mile K. Stojčev Faculty of Electronic Engineering, Niš, Serbia and Montenegro Definitions of some standard terms Variable delay elements (VDEs)-definition VDEs are inverter–based circuits used for fine, precise, and accurate pulse delay control in a high-speed digital and mixed integrated circuits. How is achieved variable delay? Using delay line (DL). A chain of VDEs forms DL. Where we meet delay lines? DLs are constituents of: • • • • DLLs (Delay Locked Loops), TDCs (Time-to-Digital Converters), VCOs (Voltage Controlled Oscillators), PWCLs (Pulse-Width Control Loops), etc. Typical Applications of DLs • DLs are used as constituent in DLLs in order to: – achieve correct synchronization between different digital blocks (CPU and SDRAM interface, ...), – eliminate clock skew and jitter within VLSI ICs. • Vernier delay patterns implemented as TDCs, usually composed with two DLs. • DLs connected in a ring are building blocks of VCO in PLLs. • DLs are constituents of Duty Cycle Correctors (DCCs) in systems with feedback loop. Classification of delay line elements Variable delay line elements are classified as: • Digital- Controlled Delay Elements (DCDEs) realized as series of delay elements of variable length (the number of elements in a chain determines the amount of the delay). • Voltage-Controlled Delay Elements (VCDEs) efficient in applications where small, accurate, and precise amount of delay is necessary to achieve. VCDEs are realized using: shunt capacitor, current starved. Shunt capacitor delay element capacitive loaded inverter in Vdd M2 800 M6 out Time tp [ps] Vdd 840 720 M1 M5 VC M3 M7 640 M4 M8 560 3 3.5 Shunt capacitor delay element: (a) scheme 4 4.5 voltage Vc [V] (b) typical characteristic delay in term of control voltage Shunt capacitor delay element has the following disadvantages: a) the output capacitor occupies large silicon area; b) the amount of a delay and the range of voltage regulation are small;. 5 Current starved delay elements implemented using current inverters 2400 Vdd 2000 Vdd M4 M2 M6 in out C 1600 1200 M5 M1 VBN Time tp [ps] VBP M3 800 600 2.6 Current starved delay element: (a) scheme 3 3.4 voltage Vc [V] (b) typical characteristic delay in term of control voltage The current starved delay element has a) simple structure; b) relatively wide delay range of regulation;. 3.8 4 Common to both VCDLs Advantages: • Simple structures • Fine delay resolution Disadvantages: • Shunt Capacitor and Current Starved DLs have non-linear transfer function, delay variation in term of control voltage Problem of VCDL realization was considered by: • • • Y. Moon, et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance”, IEEE JSSC, vol.35, No. 3, pp. 377-384, March 2000. M. Maymandi-Nejad, M. Sachdev, “A digitally Programmable Delay Element: Design and Analysis”, IEEE Trans. on VLSI Systems, vol. 11, No. 5, October 2003. G. Jovanović, M. Stojčev, “Voltage Controlled Delay Line for Digital Signal”, Facta Universitatis, Series: Electronics and Energetic, vol. 16. No. 2, pp. 215-232, August 2003... What we propose • Linearization of VCDL’s transfer function • We use Current Starved DE. • Why: – Simple structure – Relatively wide range of delay regulation • How we achieve linear VCDL? – We modify the bias circuit. – We use a non-linear bias circuit which is based on the square-law characteristics of a MOS transistor in saturation. – By a cascade connection of two non-linear elements, the bias circuit and the current starved delay element, we obtain a linear transfer function (delay in terms of control voltage). Delay Line Element – standard solution Cascade composition of a bias circuit and VCDL Vdd 1.5/21 VBP Vctrl bias circuit C Vsw I cp Vdd Vdd Icp M5 M2 IN VBN tdelay VBP M1 2/21 OUT 2/7 VBN Cload M3 M4 1.5/7 2/21 Icp 2/7 M6 voltage control delay element where: tdelay - delay time, C - parasitic output capacitance, Vsw clock buffer (inverter) swing voltage, Icp - charging/discharging current of C. Bias circuit with reciprocal current regulation Proposal V V dd dd 6/28 MB2 6/28 Vctrl 4/28 MB4 4/28 MB5 3/28 Vdiff 6/21 I1 WA / LA MA1 VBN VB2 MS1 B1 MS2 IBss B2 BN Icp MS3 WA / LA I2 MA2 VBP - OF - - CVC - BP 2/28 I2 Output Follower Icp 6/21 B1 VB1 Vdd MD2 R 2/28 Vdiff Vdiff+ - VCC - Current to Voltage Converter Vdd I0'' Vdiff I1 Current Starved Delay Elements 3/28 R MD1 Voltage to Current Converter VdiffMB6 d_BPc I0' Vdiff+ - ASF - d_BP Fro ban m d-g circ ap uit AGND MB3 Asymmetrical to Symmetrical Folower To Delay Line MB1 6/7 out in Schematic of a bias circuit Vdd Vdd MB1 6/28 MB2 6/28 4/28 MB3 3/28 MB5 MB4 4/28 d_BP d_BPc I0' Vdiff 3/28 6/21 VB1 I1 Vtn kn I1 B1 2/28 WA / LA MA1 I1 I 0' Vdiff R I2 B1 MS2 IBss B2 BN MS3 WA / LA I 2 I 0'' I Bss A B I1 C I1 BP 6/21 Vdiff+ MS1 MD2 R 2/28 Vdd I0'' Vdiff R MD1 Vdiff - MB6 To Delay Line Fro ban m d-g circ ap uit AGND MA2 Vdiff R 6/7 A V 4 kp B dd 2Vtp Vtn k p 2 Vdd 2Vtp Vtn 4 1 kp C 4 kn kn 2 Analytical model of a bias circuit 1.5 22 16 I 2 I 0'' R 1.2 I1 4 I1 I 0' -1 -0.8 -0.4 0 Vdiff [V] Vdiff 0.8 Icp [A] 1 1 -1 -0.8 -0.4 a) I cp A B I1 C I1 30 26 22 18 VB 2 R 0.4 5.5 34 Transfer function of current-tovoltage converter V B1 1.1 36 Chargedischarge current variation in terms of control voltage V B2 I1 Vtn kn 1.3 12 8 VB1 1.4 Vdiff VB1, VB2 [V] I2 Vdiff0 [V] I2 Vtn kn 0.4 0.8 1 b) 4 x10 Reciprocal of Chargedischarge current variation in terms of control voltage 5 1/Icp [1/A] Transfer function of voltage-tocurrent converter I1, I2 [A] 20 I cp ~ 1 Vdiff 4 3 -1 -0.8 -0.4 0 Vdiff [V] 0.4 0.8 1 c) 2.5 -1 -0.8 -0.4 0 Vdiff [V] 0.4 0.8 1 d) Technological and operating parameters for 1.2 m CMOS technology: Cox=1.41e-3 F/m2; mp=195E-4 m2/V*s; mn=555E-4 m2/V*s; kn=0.5*78.255 mA/V2; kp=0.5*27.495 mA/V2; Vtn=0.6259V; Vtp=1.14V; I0=12.5mA; R=120kW; Vdd=5V; HSpice simulation of a bias circuit 0.08 1/ I cp [1/A] Icp [A] 28 26 0.07 LA=10m LA=12m LA=14m 22 0.06 LA=10m LA=12m LA=14m 0.05 0.04 18 -0.8 -0.4 0 Vdiff [V] 0.4 0.8 1 -0.4 0 Vdiff [V] 0.4 0.8 1 b) Reciprocal of Charge-discharge current variation in terms of control voltage a) Charge-discharge current variation in terms of control voltage LA - is a transistors channel length in Current-to-Voltage Converter Relative approximation error of the reciprocal charge-discharge current variation in terms of control voltage Approximation Error [%] 14 0.035 -0.8 2 1 0 -1 LA=10m LA=12m LA=14m -2 -3 -4 -0.8 -0.4 0 Vdiff [V] 0.4 0.8 1 c) Current starved VCDL with linear delay regulation VBN Vdiff+ Vdiff- VCDE 1 Voltage to Current Converter - VCC - I1 VBN Current to Voltage VB1 Output Follower - OF - CVC - VB2 VBN VCDE 3 CLKout4 delay element 4 VBP VBN OB 4 VBP VCDE 2 VCDE 4 VBP Converter I2 CLKout3 CLKout2 VBP delay element 3 OB 3 VBP delay element 2 bias CLKin OB 1 Vdd delay element 1 OB 2 CLKout1 - Complete design - VBN Schematic of four stage DL HSpice delay line simulation – results relate to CLKout4 – 3000 60 tdelay [ns] 2500 2000 50 1500 tdelay [ps] 1000 40 500 30 25 0 -500 -0.8 -0.4 0 Vdiff [V] 0.4 0.8 Time delay, tdelay , in term of control voltage Vdiff a) 1 -1000 -0.8 - 0.4 0 Vdiff [V] 0.4 0.8 b) Relative approximation error of time delay, tdelay , in term of control voltage Vdiff 1 Conclusion ►An implementation of a linear VCDL is proposed. ►Current starved DL is used. ►Linearization is achieved by modifying the bias circuit of current starved DL. ► HSpice simulation results points to the fact that for 1.2 m CMOS technology high delay linearity (error is less then 500 ps) within the full range of regulation (from 28 to 55 ns) is achieved. ►VCDL is used as a constituent of DLL, TDC, PWCL, VCO,… Q&A