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DIGITALELECTRONICS:LOGICANDCLOCKS LAB9INTRO:INTRODUCTIONTODISCRETEDIGITALLOGIC,MEMORY,ANDCLOCKS GOALS In this experiment, we will learn about the most basic elements of digital electronics, from which more complexcircuits,includingcomputers,canbeconstructed. Proficiencywithnewequipmentandapproaches: o o Logicgates,memorycircuits,digitalclocks Combiningcomponents&Booleanlogic DEFINITIONS Dutycycle–percentageoftimeduringonecyclethatasystemisactive(+5Vinthecaseofdigitallogic) Truthtable–tablethatshowsallpossibleinputcombinationsandtheresultingoutputsofdigitallogiccomponents Flip-flop-acircuitthathastwostablestatesandcanbeusedtostorestateinformation. Logicgates–aphysicaldevicethatimplementssomeBooleanlogicoperation DIGITALCIRCUITS-GENERAL Inalmostallexperimentsinthephysicalsciences,thesignalsthatrepresentphysicalquantitiesstartoutas analogwaveforms.Todisplayandanalyzetheinformationcontainedinthesesignals,theymostoftenareconverted into digital data. Often this is done inside a commercial instrument such as an oscilloscope or a lock-in amplifier, whichisthenconnectedtoacomputerthroughadigitalinterface.Inothercases,dataacquisitioncardsareaddedto a computer chassis, allowing analog signals to be input directly to the computer. Scientists usually buy their data acquisitionequipmentratherthanbuildit,sotheyusuallydon’thavetoknowtoomuchaboutthedigitalcircuitry thatmakesitwork.Almostalldataareeventuallyanalyzeddigitallywithacomputer. AnaloginformationcanbetranslatedintodigitalformbyadevicecalledanAnalog-to-DigitalConverter(A/D N converter or ADC). A set of N bits has 2 possible different values, as you might recall from Lab #5. If you try to 7 representananalogvoltageby7bits,yourminimumuncertaintywillbeabout1%,sincethereare2 =128possible combinations of 7 bits. For higher accuracy you need more bits. The corresponding device that can convert digital databackintoananalogwaveformiscalledaDigital-to-AnalogConverter(D/AconverterorDAC),whichwebuiltin Lab#5. Logicgatesalonecanbeusedtoconstructarbitrarycombinatoriallogic(theycangenerateanytruth-table), buttocreateamachinethatstepsthroughasequenceofinstructionslikeacomputerdoes,wealsoneedmemory andaclock.Thefundamentalsingle-bitmemoryelementofdigitalelectronicsiscalledaflip-flop.Wewillstudytwo types,calledSR(orRS)andJK.Theflip-flopswehavechosenarefromtheTTL(Transistor-transistorlogic)family.A digital clock is a repeating digital waveform used to step a digital circuit through a sequence of states. We will introduce the 555 timer chip and use it to generate a clock signal. Digital circuits that are able to step through a sequenceofstateswiththeaidofflip-flopsandaclockarecalledsequentiallogic. 1 DIGITALLOGICSTATES Thevoltageinadigitalcircuitisallowedtobeinonlyoneoftwostates:HIGHorLOW.HIGHistakentomean logical(1)orlogicalTRUE.LOWistakentomeanlogical(0)orlogicalFALSE.IntheTTLlogicfamily(seeFigure1),the “ideal”HIGHandLOWvoltagelevelsare5Vand0Vbutanyinputvoltageintherange2to5.0Visinterpretedas HIGH,andanyinputvoltageintherange0to0.8VasLOW.Voltagesoutsidethisrangeareundefined,andtherefore “illegal,”exceptiftheyoccurbrieflyduringtransitions.IftheinputtoaTTLcircuitisavoltageinthisundefinedrange, the response is unpredictable, with the circuit sometimes interpreting it as a “1” and sometimes as a “0.” Avoid sendingvoltageintheundefinedrangeintoaTTLcomponents. Figure1:TTLInputVoltageLevels DIGITALLOGICGATES The flow of digital signals is controlled by transistors in various configurations depending on the logic family (see H&H 8.09 for details). For most purposes, we can imagine that the logic gates are composed of several ideal switches with just two states: OPEN and CLOSED. The state of a switch is controlled by a digital signal. The switch remains closed so long as a logical (1) signal is applied. A logical (0) control signal keeps it open. Logic signals interact by means of gates. The three fundamental gates, AND, OR, and NOT, are named after the three fundamental operations of logic that they carry out. The AND and OR gates each have two inputs and one output. The output state is determined by the states of the two inputs. The NOT gate has one input and one output. The function of each gate is defined by a truth table, which specifies the output state for every possible combination of input states. The output values of the truth tables can be understood in terms of two switches. If the switches are in series, you get the AND function. Parallel switches perform the OR operation. The most common gates are shown in Fig. 2. A small circle after a gate or at an input on the schematic symbol indicates negation (NOT). 2 Operation Switches A AND B Boolean circuitisclosed Notation (AANDBareclosed) A• B Series OR Conditionthat (AORBisclosed) A A + B Symbol TruthTable A B A .B A B A.B 0 0 0 1 1 0 1 1 A B 0 0 0 1 A+B A B A+B A _ A B Parallel Different 1meansopen NOT ( A) ≡ A (sameas invert) kindofswitch 0meansclosed CompoundGates NOR XOR Figure2:DigitalLogicgates 3 0 1 0 1 0 1 1 1 NOT NAND 0 0 1 1 A B A.B A B A+B A B A+B =AB+AB A _ A 0 1 1 0 MEMORYELEMENTSANDFLIP-FLOPS In sequential logic circuits, the output depends upon previous values of the input signals as well as their present-time values. Such circuits necessarily include memory elements that store the logic values of the earlier signals.ThefundamentalmemorycircuitistheRSmemoryelement.TheJKflip-flophasanRSflip-flopatitscore,but itaddscircuitrythatsynchronizesoutputtransitionstoaclocksignal.Timingcontrolbyaclockisessentialtomost complexsequentialcircuits RSMemoryCircuit ThetruthtablefortheRSmemoryelementshowshowthecircuitremembers.Supposethatitisoriginallyinastate withQ=0andR=S=0.ApositivepulseSattheinputsetsitintothestateQ=1,whereitremainsafterSreturnstozero. AlaterpulseRontheotherinputresetsthecircuittoQ=0,whereitremainsuntilthenextSpulse. RS MEMORY Signals Symbol Circuit R R Q = R+ P S Q SET RESET time P= S + Q S Truth Table R Q S Q S 0 1 0 1 R Q P= Q 0 Stays the same 0 0 1 1 1 0 0 P= Q 1 0 Disallowed Figure3:RSmemoryelement. JKFlip-Flop(TTL74107) TherearethreekindsofinputstotheJKflip-flop 1)datainputsJandK 2)theclockC 3)thedirectinputCLR(clear) Therearetwooutputs:Qanditscompliment. Figure4:JKFlip-Flop n counts the number of clock pulses since the start of the experiment.In the absence of a clock pulse, the output remainsunchangedatthepreviouslyacquiredvalue,Qn,whichisindependentofthepresent-timedatainputsJandK. Onlyonthearrivalofaclockpulse,C,cantheoutputchangetoanewvalue,Qn+1.ThevalueofQndependsontheJ andKinputsinthewayspecifiedinthetruthtable.Thechangeoccursatthefalling(trailing)edgeoftheclockpulse, indicatedbyadownwardarrowinthetruthtableinFig.4. Thedirectinput,CLR,overridestheclockanddatainputs.Duringnormaloperation,CLR=1.AtthemomentCLRgoes tozero,theoutputgoestozeroandremainsthereaslongasCLR=0. 4 555TimerandDigitalClock SeeFCsection11.14foradescriptionofthegutsofthe555timerchip.Figure9.7showsthecircuitforgeneratinga clockwiththe555andsummarizestheformulasrelatingtheresistorandcapacitorvaluestotheoutputlowtimeT1 andtheoutputhightimeT2 (a) Astable circuit (Digital Clock) +5V + 8 2 TRIG DIS 7 3 OUT THR 6 4 RST BYP 5 555 Output 1 GND RA RB (c) Limiting Values Max RA, RB 3.3 MΩ Min RA, RB 1 kΩ Min. C 500pf VC 0.1uf (b) Component values Output High (charge time): T2 = (RA+RB)C ln2 Output Low (discharge): T1 = RBC ln2 Period: T = T1 + T2 C 0V (d) Voltage outputs DC Volts V+ Pin 6 - Capacitor Voltage V c Supply Voltage (5V) .667 V+ Threshold Level .333 V+ Trigger Level time t2 DC Volts V+ t1 Pin 3 Output Voltage C charges through RA and RB in series C discharges through RB only Output is positive while C is charging Output is grounded while C is discharging time Figure 9.7 Astable circuit using 5 55 Timer chip 5 DIGITALLOGICCHIPPINOUTS Eachchiphasadotornotchtoindicatetheendwherepins1and14arelocated.Thepinnumbersincrease sequentially as you go counter-clockwise around the chip viewed from above. In 74xx family logic chips, pin 7 is alwaysgrounded(0V)andpin14isalwaysconnectedtothe+5Vsupply. 74107JKflip-flop 6 USEFULREADINGS 1. 2. FCChapter11(digitalelectronics) H&HChapter8.Everythinginthischapterisgoodtoknowaboutbutsections8.01,8.02,8.04,8.07-8.10, 8.12,8.16aremostrelevant.Alsohavealookatsection5.14onthe555timerchip. LABPREPACTIVITIES AnswerthefollowingquestionsusingMathematicaordothembyhandinyourlabbook. Question1 BasicDigitalLogic a. Readthelabthoroughlyandenterinyourlabbookthecircuitdiagramsandtruthtablesofall thecircuitsyouwilltest.TheseincludetheNAND,NOR,andINVERT/NOT. b. DesignacircuittoperformtheEXCLUSIVEOR(XOR)functionusingonlyNANDand/orNOR gates.SimplifythecircuitsothatyouusethesmallestpossiblenumberofNANDand/orNOR gates c. CheckthecircuitdoesperformtheEXLUSIVEORusingtruthtablesorBooleanalgebra. Question2 555Timer a. Designa4kHzclockusingthe555-timerchip.Makethelowlevel1/4oftheoutputperiod(a 75%dutycycle:25%low,75%high). b. Howlargeacapacitorwouldyouneedtosubstituteinordertomodifyyourclocktorunat1 Hz(e.g.forvisualobservationofLEDs),keepingallothercomponentsfixed? Question3 Question4 JKFlip-flop a. AJKflip-flopwithJ=K=1andCLR=1isdrivenattheclockinputby1kHzpulses.Drawthe waveformsfortheclockandtheQoutputvs.timeusingthesametimescale.Makesureto includeenoughperiodsoftheclocksignaltoseeallthebehavioroftheflip-flop’soutput. Labactivities a. Readthroughallofthelabstepsandidentifythestep(orsub-step)thatyouthinkwillbethe mostchallenging. b. Listatleastonequestionyouhaveaboutthelabactivity. TTLGATES Step1 7 TruthTables a. Checkyourpowersupplybeforeconnectingtothecircuitboard.TheTektronixPS280/3 hasafixed5Voutputthatyoushouldusetopowerdigitalcircuits.Thelogicchipswill burnoutataround6V.Ifthesupplyvoltagedropswhenyouconnecttothecircuit,donot increaseV. b. Inputlogicalvaluescanbesetbyconnectingwiresfromthegateinputstoeither0V (logical0)or5V(logical1).Useonelongrailonyourprototypingboardfor0Vandonefor 5V.Note:Disconnectinganinputfromthe5Vrailisnotthesameasconnectingitto0V. Ifitisdisconnected,theinputcanfloatupto5Vonitsown. c. Thelogicleveloftheoutputcanbeobservedusingalightemittingdiode(LED),whichis connectedfromtheoutputtoground.TheLEDlightsupwhentheoutputis+5Vandisoff whentheoutputis0V.Tolimittheamountofcurrentthoughthediode,placearesistor inserieswithit.Whatvalueofresistorshouldyouusetolimitthecurrentto20mA? Recordyourcalculation. d. Record the measured truth tables for the NAND (7400), NOR (7402), and INVERT (7404) gates,usingtheLEDindicatorsforyourmeasurements. Step2 Step3 Modifyingbasicgates a. ConnectaNANDgatesothatitperformstheINVERTfunction.DothisforaNORgatealso. Thistrickwillbeconvenientinsimplifyingcomplexcircuits. b. Recordyoucircuitandmeasuredtruthtable. ExclusiveOR a. VerifythetruthtablesforanEXCLUSIVEORchip(7486). b. NowbuildandtesttheXORcircuitofyourowndesignusingonlyNANDsandNORs. MEMORYCIRCIUTS Step4 RSmemorycircuit a. BuildanRSmemorycircuitfromtwoNORgates.Drawaschematicofyourcircuit. b. Demonstratethememorypropertybygoingthroughacompletememorycycle:Set(R=0, S=1),Store(0,0),Reset(1,0),Store(0,0),Set(0,1).Recordallinputsandoutputsfor eachcycle.Doesitagreewithpredictions? c. Examinetheeffectofthe“illegal”input(R=1,S=1),fordifferentinitialstatesoftheRS system.Describetheoutcomesoftheillegaloperation. TTLCLOCK Step5 DigitalClock a. Buildthe4kHzdigitalclockusinga555TimeraccordingtoyourdesigninQuestion2of the prelab. Measure the frequency, the pulse length (time the output is high), the duty cycle, and the nominal 5-volt amplitude. Do your measurements agree with your predictionsusingthemeasuredvaluesofyourcomponents? b. Checkthatasuitablelargecapacitorplacedinparallelwiththeexistingoneconvertsthe clockto1Hz. JKFLIP-FLOP Step6 a. b. c. 8 ConstructatruthtablefortheJKflip-flopfromyourobservationsusingtheLEDindicators. Sincetheoutputdependsuponthepreviousstate,Qn,youwillneedtotabulateQn+1for both possible previous states, Qn=0 and Qn=1. We suggest that you add an additional column,Qn+2,togetabetterfeelforthebehavioroftheflip-flop. SetCLR=1andJ=K=1.Nowdrivetheclockinputoftheflip-flopwith4kHzpulsesfrom your clock circuit as shown in Fig. 5. Use the oscilloscope to measure the clock input (positive pulses out of the NAND gate), and the output, Q, of the flip-flop. Record your measurements. WhathappenswhenJ=K=0? Figure5:JKFlip-floptestset-up APPENDIX:BOOLEANALGEBRA Fundamentallaws Weimaginealogicalvariable,A,thattakesonthevalues0or1.IfA=0thenĀ=1andifA=1thenĀ=0.Hereare someobviousidentitiesusingtheAND,ORandNOToperations.Lookingattheseidentitiesyoucanseewhythe‘plus’ symbolwaschosenforORand‘times’(•)forAND. OR AND NOT A + 0 = A A• 0 = 0 A +1 = 1 A•1 = A A + A =1 A • A = 0 A + A = A A• A = A A = A A + A =1 A • A = 0 Equality TwoBooleanexpressionsareequalifandonlyiftheirtruthtablesareidentical. AssociativeLaws ( A + B ) + C = A + ( B + C) (AB)C = A(BC) DistributiveLaws A(B + C ) = AB + AC Related identities : (A + AB) = A (A + A B )= A + B (A + B) • (A + C ) = (A + BC) 9 DeMorgan’sTheorems A • B •K = A + B + K A + B +K = A • B •K Example of Proof Each of the above equalities is a theorem that can be proved. Let’s do an example by directly comparing the truth tables for the left and right sides. We take on DeMorgan’s first theorem for two variables, AB = A + B A B AB AB A B A B A + B 0 0 0 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 0 0 0 The last columns of the truth tables are identical. Thus, the first theorem is proven for two variables. Example of Simplification Boolean algebra can be used to simplify logical expressions and reduce the number of gates required in a circuit. In Fig. 9.3 we show two ways to implement the expression, Y = A + ABC . A) DIRECT IMPLEMENTATION using NOT, NOR, and NAND A A BC B C B) SIMPLIFIED CIRCUIT ABC BC ABC Y = A+ABC A Y = A+ABC = A+BC (by identity #2) A = A+BC (by property of NOT) = A(BC) (by De Morgan's Law) Y = A+ABC B C Fig. 9.3. Boolean simplification 10 A+ABC