Download Low Voltage Power Distribution LVPD at Balloon-EUSO

HOUSEKEEPING
HK at Balloon-EUSO
10th JEM-EUSO meeting
from December 5th to 10th
at RIKEN, Tokyo
By G. Medina-Tanco*, A. Zamora, L. Santiago Cruz**,
F. Trillaud**, and H. Silva***.
*Institue of Nuclear Science, National Autonomous University of México.
**Institute of Engineering, National Autonomous University of México.
*** Ebizusaki Computational Astrophysics Laboratory, RIKEN.
December 7th, 2011.
24V
24V to 12V
DDCU
24V to 5V
DDCU
Housekeeping
design based on
LVPS Board at
EUSO-Balloon
24V to 5V
DDCU
24V
24V to 15V
DDCU
Conceptual drawing of HK in the case which the only
interfaces are PSB and CNES.
Power Supply Board
Signal Conditioning
& Command drivers
Auduino Mega
& Protocols
Conceptual drawing of HK for the most general scenario,
in which there are interfaces with PSB, HV, CCB and
CNES.
Single-board MCU
Arduino Mega 2560
The number of available analog and digital channels in Arduino
Board are more than enough to meet all TM&TC requirements.
But NOTE! That interfaces with HV, CCB and CNES are not fully
defined.
2
2
44
4
44
Finally, some important comments…
 The Arduino Mega 2560 option, could be delivered in early April
2012, whereas the baseline design would be completed around
mid August2012.
 The Arduino Mega 2560 does not use FPGA, in consequence it is
very likely that could not be used as final prototype for JEM-EUSO.
 Is necessary to define the subsystem requirements in order to
evaluate the feasibility of Arduino Mega 2560 option for HK at
EUSO-Balloon project.
Low Voltage Power Distribution System
(LVPDS) at Balloon-EUSO
PSB 1st prototype
10th JEM-EUSO meeting
from December 5th to 10th
at RIKEN, Tokyo
By H. Silva***, G. Medina-Tanco*, A. Zamora, L. Santiago
Cruz**, M. Casolino***, and K. Tsuno***.
*Institue of Nuclear Science, National Autonomous University of México.
**Institute of Engineering, National Autonomous University of México.
*** Ebizusaki Computational Astrophysics Laboratory, RIKEN.
December 7th, 2011.
As a first approach of PDMLVPS
 A Power Supply Board (PSB) has been developed in México.
 HVPS subsystem was based on EMCO regulator.
OUR
PROTOTYPE
PSB
5V
+12V
The interaction with PDMB requires
 The PDM board receives 5V and 12V from
PDMLVPS.
 5V is used to produce 1.5V, 3.0V and 3.3V.
Meanwhile 12V is needed for EMCO circuit
section.
 There are 9 regulators (final version)
 3V output regulator for ASIC (3)
 1.5V output regulator for ASIC (3)
 3.3V output regulator for FPGA
 1.5V output regulator for FPGA
 0-10V output regulator for HV chip
 If HVPS circuit is based on a EMCO module.
One EMCO per EC consumption is 0.5W
(9EC→4.5W).
 HV system current consumption is ~400mA.
 If HVPS circuit is based on CW the power
consumption from 28V (instead 12V) is 55mW
per EC (9EC→495mW). However, external
control consumption is missing.
 FPGA consumption is 1W~2W.
 PDMB Total power consumption is ~4W.
 Interface power connector used is 9pin Dsub.
Information provided by Aera
PDM board
From a
power
board
ASIC
PSB description
24V bus voltage
182mm X 95mm
V&I
monitoring
circuits
 UEI15-120-Q12P-C  12V/1.3A
 UEI15-050-Q12P-C  5V/3A
 MEV1S2405SC  5V/0.2A
 Is based on three
MURATA isolated DCDC converter.
 5V for PDM, 12V for
HV generation chips
and 5V HK monitor
circuits.
PSB Isolated DDCUs Specifications
Feature
Option/Output
Vin range [V]
Vin nom [V]
Vout [V]
Iout [A]
Power [W]
Efficiency [%]
UEI15-120-Q12P-C
A / Single
9-36
24
12
1.3
15.6
84.5
UEI15-050-Q12P-C
A / Single
9-36
24
5
3
15
87.3
MEV1S2405SC
A to B / Single
21.6-26.4
24
5
0.2
1
84
TMP-5/5-12/1-D24-C
B / Triple
18-36
24
Single +5V, dual ±12
5, ±1
35
85
110-150
70-125
12-20
75-10, 100-120
±0.05% / ±0.05%
±0.05% / ±0.075%
1.1% / 5%
±1% / ±1.5%, ±1.5% / ±8%
Under voltage shutdown [V]
8.4
8.5
---
None
Output Over Voltage Protec [V]
14.1
5.9
---
6.8, 15
Thermal protection shutdown [°C]
115
115
---
95
50
50
0.45
---
27.9x24.4x8.1
27.9x24.4x8.1
19.7x6.1x13.8
51.8x77.2x19
2000
(full magnetic and optical)
2000
(full magnetic and optical)
3000
1500
Fast blow at 4A
Fast blow at 4A
Fuse at 0.2A
Slow blow at 4A
Class B en55022
External caps recommended
Class B en55022
External caps recommended
No external components
required
CE - PI filter
340
350
85
125 ±10%
MTBF 2x106 [hours]
MTBF 2X106 [hours]
MTTF 7391 [khours]
---
-40 to 85
-40 to 85
-40 to 85
-40 to 70
10
6
10
6
2.8
7
170
10
UVLO
UV Shutdown
Start-up TH
Over Temp Shutd Output
current limit; Output Over
Volt Rev Cond Elimin
UVLO
UV Shutdown
Start-up TH
Over Temp Shutd Output current
limit; Output Over Volt Rev Cond
Elimin
Fully encapsulated with
toroidal magnetics; No
electrolytic or tantalum
caps
Current limit continuous and Over
Voltage Protection
Output Ripple/Noise [mVp-p]
Output Regulation max (line / load)
Start-up time
Vin to Vout regulated (max) [ms]
Dimensions [mm]
Isolation Input-Output [Vdc]
Input Fusing
EMI
Switching Freq [kHz]
Reliability issue
Operating Temp [°C]
Weight [g]
#Pin
Protections
(Input/Output)
PSB-HK TM/TC interface electrical specs
Monitored Output Voltage levels:
12V DC/DC MONITOR OUTPUT
5V DC/DC MONITOR OUTPUT
Vcc_12V [V]
*Vmon12V [V]
Vcc_5V [V]
*Vmon5V [V]
14
4
5.8
1.65
13.5
3.85
5.6
1.5
13
3.71
5.4
1.54
12.5
3.57
5.2
1.48
12
3.42
5
1.42
11.5
3.28
4.8
1.37
11
3.14
4.6
1.31
10.5
3
4.4
1.25
10
2.85
4.2
1.2
9
2.57
4
1.14
8
2.28
3
0.85
7
2
2
0.57
6
1.71
1
0.28
 A DB15 connector is proposed for
transmitting voltage signals
* Design calculations values
NOTE! Voltage levels measured on PCB TBC
PSB-HK TM/TC interface electrical specs
Monitored Output Current levels:
CURRENT MONITOR 12V OUTPUT
PIN_RET_12V
CURRENT MONITOR 5V OUTPUT
Icc_12V [A]
*Vmon12V [V]
Icc_5V [A]
*Vmon5V [V]
0.1
0.1
0.5
0.5
0.2
0.2
0.75
0.75
0.3
0.3
1
1
0.4
0.4
1.2
1.2
0.5
0.5
1.4
1.4
0.6
0.6
1.6
1.6
0.7
0.7
1.8
1.8
0.8
0.8
2
2
0.9
0.9
2.2
2.2
1
1
2.4
2.4
1.1
1.1
2.6
2.6
1.2
1.2
2.8
2.8
1.3
1.3
3
3
 A DB15 connector is proposed for
transmitting voltage signals
* Design calculations values
NOTE! Voltage levels measured on PCB TBC
RET_12V
PIN_RET_5V
RET_5V
PSB Bread board Model (BM) tests
Upper left, voltage converters. Upper right, current monitoring circuitry.
Lower left, combined view. Lower right, combined tests.
PSB Bread board Model (BM) tests
Setup for the HL_Cmd tests. A program is
uploaded on the chip of the Arduino Mega
which sends the appropriate commands.
LED lighted, a command has been
sent by the Arduino Mega.
PSB Bread board Model (BM) tests
Tests of the entire PSB on breadboard for passive load.
Picture of the active load setup.
PSB Bread board Model (BM) tests
Final printed circuit and tests of the PSB with passive and active loads.
PSB-PDM interface electrical specs
ELECTRICAL
Test voltage
600VAC (sea level)
150VAC (23.4km)
Current rating
2.5[A]
Contact resistance
8[mΩ] max at 3[A]
10[mΩ] max at 1[A]
Insulation resistance
5000[MΩ] min at 500VDC
Thermal Vacuum
Per NASA (space class only)
MECHANICAL
Operating Temp.
-55°C to 125°C
Sealing
Humidity
Mating life
500 cycles minimum
Vibration
20g’s MIL-STD-1344
Shock
50g’s MIL-STD-1344
Contact type
Pre-wired, solder and PCB
Number of pins
9
Contact functions
5VPins 1,2,3
12VPins 4,5
GNDPins 6,7,8,9
Approvals
MIL-STD-83513
 PSB – PDM Interface power
connector is based on a
9pin D-sub right angle.
 The proposal is a MDM
connector approved by MILDTL-83513.
PSB-CNES TM/TC interface electrical specs
HL_cmd 12V receiver electrical characteristics:
Circuit type:
2 Coil Latching Relay
(2 Form C)
Signals:
12VDC_Nom Pulse Set
12VDC_Nom Pulse Reset
Reference:
HL_cmd1_RET1 (HK board)
HL_cmd1_RET2 (HK board)
Max. applied voltage [V]
150% of Nom. Voltage
Coil Resistance [Ω]±10%
Set coil: 400
Reset coil: 400
Nominal operating power
[mW]
Set coil: 360
Reset coil: 360
Nominal operating current
[mA] ±10%
Set coil: 30
Reset coil: 30
Operate time [Set time]
Max. 10ms [10ms]
Release time [Reset time]
Max. 5ms [10ms]
Mechanical expected life
Min. 108 (at 600 cpm)
Electrical expected life
Min. 5x105 rated load (at
60 cpm)
Weight [g]
~4
PSB TM/TC interface proposal
 The PSB latching relay
receives two HL_cmd from
CNES.
 Voltage and current
monitoring circuits will provide
floating signals to HK board by
DB15 connector.
 Analog multiplexers and ADC
are used for reading voltage
digital value in programmable
device.
 A serial line driver is foreseen
in HK board for sending TM to
CNES.
 HK has relay turn-on capability
through open drain commands
and also acquisition CC (their
use is TBC).
 Temperature monitoring circuit
could be implemented
according to requirements.
PSB
Low Voltage Power Distribution System
(LVPDS) at Balloon-EUSO
Actual Status
10th JEM-EUSO meeting
from December 5th to 10th
at RIKEN, Tokyo
By H. Silva***, G. Medina-Tanco*, M. Casolino***,
and K. Tsuno***.
*Institue of Nuclear Science, National Autonomous University of México.
**Institute of Engineering, National Autonomous University of México.
*** Ebizusaki Computational Astrophysics Laboratory, RIKEN.
December 7th, 2011.
Functional Block Diagram of EUSO-Balloon Instrument
So far now LVPDS interacts with…
CNES: At the moment CNES (or someone) will provide
an On/Off command to a Latching Relay (LR)
and LVPD will replay with contact closure (CC)
signal.
PDM: This structure requires power supply lines for HVPS
board and PDMB internal circuitry.
DP: This structure requires power supply levels for at least
three subsystems: HK, CCB and CPU. Clock (CLK), Data
storage (DST) and IR camera (IR-CAM) blocks is TBC.
LVPDS Requirements
-The LVPS shall supply power to PDM and DP modules.
- The LVPS shall consist in two different power distribution modules, PDMLVPS and
DPLVPS.
-PDMLVPS and DPLVPS shall provide isolation interface between 28V bus PWP and all
subsystems.
- The isolation stage will comprise isolated DDCUs with efficiencies higher than 80%.
-The regulation stage shall be performed directly at load (as close as possible) for best
performance.
-The regulation stage will comprise isolated niPOL converters with efficiencies higher
than 90%.
-Propagation failures inside of LVPS modules should be controlled. If any failure event
occur cannot be propagated to PWP and subsystems.
-The LVPS modules shall provide ON/OFF functionality in order to be controlled from OBSIREN.
-The DDCUs shall provide low input voltage protection function to avoid malfunctions at
low input voltage.
-The DDCUs shall provide input circuit protection function in order to protect circuit at
secondary side when over current flows to input by some abnormalities.
- The DDCUs shall provide output over current protection function.
- Input and Output EMI filters should be consider in design LVPS modules.
- The LVPS subsystem reliability is TBD.
- The maximum PCB dimensions shall match with PDM size structure.
LVPDS Environmental Requirements
-The LVPS elements must endure environmental variability within industrial
temperature ranges (-40°C to 85°C).
- The LVPS elements must withstand shock acceleration levels of at least 15 G.
- The LVPS elements must endure humidity environment conditions of TBD.
LVPDS TM&TC Requirements
- The PDMLVPS and DPLVPS modules shall turned On/Off by two HLCMDS.
- The LVPDS modules shall provide On/Off status by CC signal.
-The LVPDS modules shall provide TM information about voltage and current
levels to HK system.
- TM & TC format information is TBD.
The interaction with CCB requires
 The CCB board needs 1.2V for FPGA core, 2.5V
as auxiliary voltage and 3.3V for I/O banks.
 The current baseline still in 1CCB to serve
8PDM’s.
 The estimated power consumption regarding
operations modes is:
MODE
CORE FPGA
AUXILIARY VOLTAGE
I/O BANKS
SUMA
Voltage [V] Current [A]1 Power [W] Voltage [V] Current [A]1 Power [W] Voltage [V] Current [A]1 Power [W] PTOT [W]
Standby2
1,2
0,9775
1,173
2,5
0,9545
2,38625
3,3
0,0046
0,01518
3.57
FPGA Configuration3
1,2
0,8625
1,035
2,5
0,575
1,4375
3,3
0,7475
2,46675
4.94
PDM Configuration4
1,2
2,07
2,484
2,5
1,73075 4,326875
3,3
0,0046
0,01518
6.82
Normal operation5
1,2
2,07
2,484
2,5
3,3
0,0046
0,01518
8.53
2,415
 Normal operation power consumption is 8.5W.
 Voltage levels absolute max ratings
1.2V(1.32V), 2.5V(3V) and 3.3V(3.75V).
 Voltage levels tolerance 1.2(±5%), 2.5(±5%) and
3.3(±5%).
6,0375
Note 1: plus 15% margin
Note 2: waiting for trigger
Note 3: typical values
Note 4: probably a bit lower
Note 5: processing trigger
Information provided by Jörg
The interaction with HK requires
 The HK board needs ±15V and 5V
voltage levels.
 ±15V is used for signal conditioning
circuit (MUX, ADC, Inst Amp and
HL_cmd driver).
 The 5V level is used for:
 Op-Amp for CC (contact closure)
signal.
 Buffer interface with PC port.
 Also ADC digital part.
 The Arduino Mega 2560 control board
power consumption is about 1.8W.
 The HK board total power
consumption expected is about 3W.
 In principle, HK will monitor current
and voltage levels from power LVPS.
 HK use a High efficiency buck
switching regulator to provide 5V
level.
Other interactions are:
 The power consumption expected
from CPU module is 12W, and 12V
voltage level.
 The power consumption of CLK is
about 1W at 5V.
 The IRCAM supply line is not defined
yet. In principle, there are three
options:
• CPU USB interface.
• PWP.
• LVPS board.
 Power interfaces ?.
The proposal for DPLVPS
 CPU in principle could be request 12V
voltage line at input with power
consumption of 12W.
 Meanwhile, CLK part will require 5V at the
input with 1W power consumption.
 Power supply for IRCAM is TBD.
Low Voltage Power Supply subsystem at B-EUSO
THANK YOU