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University of Victoria Department of Electrical and Computer Engineering Elec 499B – Group #7 Fixed Frequency Series-Parallel Resonant ZVT DC-DC Converter Final Project Report Submitted on: April 8, 2005 Group Members: Tim Gordon (0220973) Devin Krenz (0226341) Nouredine Mahdar (0228583) Rico Luc (0229785) Table of Contents List of Figures and Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv 1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0 DC-DC Converter Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 AC-DC Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 Driver Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Power Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.1 Power Circuit Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4.2 Winding of the Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 Test Procedure and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Testing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Final Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.0 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Appendix A (Block Diagram of Control IC) Appendix B (Pin Descriptions for Control IC) ii List of Figures Figure 1 - DC to DC Converter........................................................................................... 2 Figure 2 - AC to DC setup (transformers are not shown) ................................................... 3 Figure 3 - Schematic of Mosfet Bridge (part of power circuit) .......................................... 4 Figure 4 - Mosfet gate signal outputs from the control circuit ........................................... 4 Figure 5 - Error amplifier circuit (internal to control IC) ................................................... 6 Figure 6 - Schematic of the control circuit ......................................................................... 6 Figure 7 - Oscillator schematic and frequency behavioural graph ..................................... 7 Figure 8 - Control circuit .................................................................................................... 7 Figure 9 - Current Driver PCB............................................................................................ 8 Figure 10 - Power Circuit ................................................................................................... 9 Figure 11 - Voltage and Current at output of Mosfet Bridge ........................................... 14 Figure 12 - Gate signals Q1 and Q3 from the control circuit ........................................... 15 Figure 13 - Plot of Vout vs. Load for Vin = 27V and Vin = 56V .................................... 17 Figure 14 - Plot of Iout vs. Load for Vin = 27V and Vin = 56V ...................................... 18 Figure 15 - Plot of phase vs. Load for Vin = 27V and Vin = 56V ................................... 19 iii Summary Over the course of the term the project that was designed, built, and tested was a fixed frequency, DC to DC resonant converter. The goal of the design is to produce an extremely efficient, small, light weight, and cost effective DC to DC converter. These are some of the properties that are made possible by using a ZVT resonant type converter. The converter built in this project has 4 main stages: AC to DC conversion, control circuit, driver board and power board. When the project was completed and ready to be tested it was not able to operate at full power when the load was reduced from 100%. All the results were then collected at a low voltage, where the converter worked quite well. At high voltage when the load was reduced and the control circuit was adjusted to compensate the output voltage the circuit failed. At that point enough data had been collected to put together some detailed results showing that the system was generally operating as expected allowing a constant output voltage with varying load. 1 1.0 Introduction Resonant DC to DC converters are a very efficient way of converting DC voltages. By soft switching mosfet transistors and using Zero Voltage Transition (ZVT) techniques, it becomes possible to reduce or boost voltage with hardly any losses. DC to DC converters are used in many power applications including UPS (Uninterruptible Power Supply) systems. There are many different ways to implement a DC to DC converter, but this project focuses on the Fixed Frequency pulse width modulated series-parallel resonant LCC type Converter. To provide pulse width modulation we used the UC1875 IC to control the gating signals of the four power Mosfets (Bridge configuration). The converter also has a capacitive output filter. The goal for this project is to be able to supply a 120 volt output to a load with a maximum power of 500 watts. The input voltage is variable from 110Vdc to 130Vdc and by manually adjusting the phase delay of the mosfet gate signals it is possible to maintain the output voltage at a constant 120Vdc. Note that the IC used is capable of using feedback to keep the output signal constant with a certain amount of fluctuation in input voltage or load resistance, but due to time restraints this was not implemented in this project. The DC to DC converter has 4 main stages to its operation. These include AC to DC conversion, control circuit, driver circuit and power circuit. Each of these stages will be discussed in great detail in the following sections. A block diagram of the DC to DC converter is shown in figure 1. Figure 1 - DC to DC Converter 2 2.0 DC-DC Converter Stages 2.1 AC-DC Conversion The AC to DC conversion stage is the simplest part of the project. It consists of a large kVA step down transformer, a variac transformer (to vary input voltage during testing), a full-wave bridge rectifier, and a large filter capacitor. The input to the step down transformer is 208V three-phase supplied from the lab. The output is a 120V three phase signal that is put into the variac transformer so one is able to vary the voltage to the DC to DC converter from zero to 120Vac. The full wave rectifier consists of 3 sets of power diodes that rectify the three phase signal before it is input to the DC to DC converter across a large filter capacitor. There is also a circuit breaker placed between the filter capacitor and the converter for safety and an ammeter to monitor the input current. A picture of the setup is shown in figure 2. Figure 2 - AC to DC setup (transformers are not shown) The DC signal supplied by the AC to DC conversion stage is the input to the DC to DC power circuit across the four switching mosfets. This will be talked about in more detail in the power circuit section and is shown in the power schematic. 2.2 Control Circuit The purpose of the control circuit is to provide pulse width modulation by supplying a square wave pulses to the gates of the mosfets so that they are turned on and off in the correct sequence and at the correct frequency. Referring to the Mosfet Bridge shown in the schematic in figure 3 and the capture of the gate signals shown in figure 4, one can see that the gate signals on Q1 and Q3 are out of phase and the same goes for Q2 and Q4. There is also some delay between when Q1 goes low and Q3 goes high. This is to prevent both series mosfets from turning on at the same time and shorting the DC input. The delay is in the order of a few hundred nanoseconds (about 250ns in this case). There 3 is also a phase shift between the signals on Q1 and Q3 to Q2 and Q4. This phase shift needs to be adjustable in order to vary the output voltage of the DC to DC converter. Figure 3 - Schematic of Mosfet Bridge (part of power circuit) Figure 4 - Mosfet gate signal outputs from the control circuit The switching frequency of the gate signals is designed to be 100 kHz, but the frequency is adjustable in order to fine tune for resonance when connected to the power circuit. This frequency is also a critical piece of information in the design of the power circuit which will be discussed later. Figure 6 shows the schematic of the control circuit while figure 8 shows a picture of the PCB for the control circuit. By looking at the schematic in figure 6 and the block diagram of the IC given in appendix A, one can see that the control circuit is quite a complicated setup. For this project however all that is required is to calculate the values of the resistors and capacitors placed on the pins of the IC. These components set up the IC to output the gate signals to the mosfets with the correct frequency, phase, delay and to ensure that the IC is protected from noise spikes. In the schematic, C10, C7, C6, C11, C5, and C1 are all noise bypass capacitors. Most of them are selected to be 0.1uF or 0.01uF. The capacitance on the input voltage is selected to be larger for filtering the lower frequency variations. The delay pins (pin 7 and pin 15) also have resistances connected to them, R1 and R8. These 4 resistances set up the delay time for the transition between when Q1 goes low and Q3 goes high. The same goes for Q2 and Q4. They are calculated as follows. Typical Delay Time (from data sheets) = 250ns, which translates to a duty cycle of approximately 47.5%. Delay time = 62.5e-12/Idelay => Idelay = 0.25e-3 Idelay = Delay set voltage/ Rdelay, Delay set voltage typically = 2.4V =>Rdelay = 2.4/0.25e-3 = 9.6kΩ =>R1 = R8 = 9.6 kΩ In order to calculate the ramp capacitor (C14) and the slope resistor (R12) one must refer to the pin descriptions in the data sheets for the IC. The pin descriptions are included in Appendix B. The equation that is used for determining these values is shown below. dV/dT = Sense Voltage/(Rslope*Cramp) = (3.8V–1.3V)/10us The sense voltage is the difference between the typical ramp peak clamping level and the offset voltage to the input of the PWM comparator (inside IC). 10us is the period of the square wave that is trying to be obtained at the outputs. This design is intended to be for a 100 kHz switching frequency so the period of the waveform is simply the inverse of 100 kHz. The equation now becomes the following. Rslope*Cramp = 10us Rslope was selected to be 10kΩ and Cramp was selected to be 1nF to satisfy the above equation. Figure 5 shows a simplification of the error amplifier circuit and that it is the second input, along with the ramp capacitor, into the PWM comparator. Note that this can also be seen by looking at appendix A. In order for the PWM comparator to toggle, the input voltage to the non-inverting error amplifier input must exceed 1.3V. A voltage divider with a 10k potentiometer and 5k resistor were used to be able to vary the voltage input to the error amplifier. Using these values the input voltage can be varied from 0V to about 3.3V. When adjusting the pot the phase will change between the outputs A, B and outputs C, D. The switching frequency is set by a parallel capacitor and resistor being connected to the freqset pin (pin 16). Once again by using a potentiometer one is able to vary the switching frequency by adjusting the resistance. Referring again to figure 6 one can see that R9, P2, and C12 make up the configuration. 5 Figure 5 - Error amplifier circuit (internal to control IC) Figure 6 - Schematic of the control circuit In order to set the switching frequency of the gate signals one must refer to the data sheets of the IC to obtain values for the resister and capacitor that have to be placed in parallel and to the frequency set pin. Figure 7 shows a simplified oscillator schematic inside the IC and a graph that is used in determining the values for the RC circuit. 6 Figure 7 - Oscillator schematic and frequency behavioural graph The goal for this converter was to obtain a switching frequency of 100 kHz. The resistor and capacitor were then selected according to the above graph. Choosing a capacitor of 4700pF and a resistor of about 11kΩ will reveal the 100 kHz switching frequency. The potentiometer (P2) was then put in place to be able to vary the resistance from 5kΩ to 15kΩ. This allows the switching frequency to be adjusted from about 80 kHz to about 200 kHz in order to fine tune the circuit later when the power board is connected. Figure 8 - control circuit Figure 8 shows the layout of the control PCB including the switching frequency adjustment potentiometer and the gate signal phase adjustment potentiometer. Both of these adjustments are needed to fine tune the switching frequency when the power circuit is connected and to vary the phase between the gate signals on Q1, Q3 and Q2, Q4. When the input voltage to the power circuit is within the specified range of 110Vdc to 130Vdc the phase adjustment can be varied to adjust the output to remain constant at 120Vdc. This is the specification for the design; however in practice the potentiometer 7 used has enough range to keep the output constant when the input varies even more. This translates to the phase being adjusted from 0 to 180 degrees between mosfets Q1, Q3 and Q2, Q4. The phase is represented by the symbol, φ in figure 3. 2.3 Driver Circuit The driver circuit is simply a current amplification stage. The four output signals from the control circuit stage are not capable of supplying very much current (<1A). The power mosfets used on the power circuit have quite large gate-drain and gate-source capacitances. When switching these mosfets on and off at high frequencies such as 100 kHz they draw quite a large amount of ‘in rush’ current instantaneously. The current required to turn on one of these mosfets without delay is greater than 1 amp which is larger than the control circuit IC is capable of sourcing. The current driver board provides complete isolation between input (from the control circuit) and output (to the power circuit). A picture of the driver board is shown in figure 9. Note that this stage was provided by Dr. Bhat and therefore no design or building was required in the scope of this project. Figure 9 - Current Driver PCB The power to the board is supplied by two separate 15V power supplies (for isolation). The outputs are connected directly to the power mosfets from gate to source. 2.4 Power Circuit The power circuit is the final and most important stage of the project. It consists of the Mosfet Bridge, a series connected capacitor and inductor with parallel connected capacitor to transformer (hence LCC), a full wave bridge rectifier, and a capacitive output filter. By using the series-parallel configuration (or LCC resonant type) for the converter it is possible to operate at high frequency, with high efficiency reducing the size, weight, and cost. The transformer provides isolation to the output while the rectifier and output filter capacitor convert the square wave to a smooth DC output. Figure 10 shows the full schematic of the power circuit stage. 8 Figure 10 - Power Circuit As shown in figure 10, all the signals coming from the control circuit connect to the mosfets across the gate and source. The two zener diodes are placed across each connection to protect the mosfet junction from large voltage spikes. Vin is the input DC voltage supplied by the AC to DC converter. Ls, Cs, and Cp are the series-parallel resonant components to the converter. All the calculations for determining the values of the LCC resonant section and the output filter capacitor are discussed below. 2.4.1 Power Circuit Calculations A) Given data and Specifications: Vin: 110Vdc to 130Vdc Vout: 120Vdc Power: 500 Watts Frequency: 100 KHz Cs/Cp = 2 Q = 3, F = 1.1, δ = π The convention used in all the calculations presented are normalised using the base quantities shown below: VBase = Vs the minimum input voltage ZBase = RL’ the primary reflected load resistance IBase = Vs/RL 9 B) Design Calculations B-1) The Output Resistance RL = Pout/Vout^2 RL= 500/120^2= 28.8Ω This is done for the worst case operation conditions δ = π corresponding to minimum input voltage and maximum output current. B-2) The primary side reflected output voltage, turns ratio, and the primary reflected load resistance RL’ B2-1) By taking the minimum supply voltage, Vs =110Vdc, the primary side reflected output voltage is given by: Vout’ (pu) = sin(δ/2)*(D1^2+D2^2)^1/2 Where D1 and D2 are given by: D1 = 1 + (Cp/Cs)*(1-F^2) => D1 = 0.895 D2 = δ^2/8*Q*(F-1/F) => D2 = 0.7605 => Vout’ (pu) = 0.877 So the Vout’(Volts) is Vout’ = Vs*Vout’ (pu) = 110*0.877 = 96.466V B-2-2) The high frequency transformer turns ratio, n, is given by: n = Vout’/Vout n = 96.466/120 = 0.803 B-2-3) The primary reflected load resistance RL’ is given by: RL’ = RL*n^2 RL’ = 28.8*0.803^2 = 18.6Ω B-3) Leq, Cs and Cp calculations B-3-1) Leq Leq = Q*RL’/Wr Where Wr is given by: Wr = 2* π/F 10 For our design: Wr = 2*100kHz/1.1 = 571198.66 Leq = 3*18.6/571198.66 = 97.74μH Note that Leq = L + Lp + Ls’ Where Lp and Ls’ are the primary and primary referred secondary leakage inductances of the high frequency transformer. B-3-2) Cs and Cp Cs = 1/Wr^2*Leq So Cs = 1/(571198.66^2*97.74μH) = 0.0314μF Cp = Cs/2 Cp = 0.0157μF Now that all the values of all of the components have been obtained, one must calculate the voltages across them and current flowing through them for power rating purposes. B-4) Power rating for all components B-4-1) The peak current trough Cs and Leq The peak inverter current is the same as the switch peak current or inductor peak current and is given by the following: Ip (pu ) = [4*Sin(δ/2)]/( π*| Zpu|) (pu) Zpu = (B1/B3) + j(B2/B3) (pu) B1 = K*[(Q/F)*(Cs/Cp)]^2 B2 = Q*[F - (1/F)]*B3 - K^2*(Q/F)*(Cs/Cp) B3 = K^2 + [(Q/F)*(Cs/Cp)]^2 Where K is given by: K = 8/ δ^2 Using the design criteria outlined above we get: K = 8/ π^2 = 0.8105 B1 = 0.8105*[(3/1.1)*2]^2 = 24.116 B2 = 3*[1.1 - (1/1.1)]*30.409 - 0.8105^2*(3/1.1)*2 = 13.83 B3 = 0.8105^2*[(3/1.1)*2]^2 = 30.409 Zpu = (24.116/30.409) pu + j(13.83/30.409) pu = 0.79305 pu + j 0.4548 pu |Zpu| = (0.79305^2 + 0.4548^2)^(1/2) = 0.9142 pu Ip (pu) = 4/(π*0.9142) = 1.393 pu Ip = Ip(pu)*Iref Iref = Vb/Zb = Vs/RL’ Vb = Vs = 110V Zb = RL’ = 18.6 11 => Iref = 110/18.6 = 5.91A => Ip = 1.393*5.91A = 8.23A Note Ip is the current flowing through Leq B-4-2) The peak voltage across Cp The peak voltage across Cp is given by: VCp (pu) = Vout’(pu) = 0.877 So VCp = 0.877*110 = 96.466 volts B-4-3) The peak voltage across the capacitor Cs The peak voltage across the capacitor Cs is given by: VCs (pu) = Ip(pu)/XCs(pu) I (pu) = 1.393 (see calculations for the current through Leq) XCs (pu) = Q/F(pu) So XCs (pu) = 3/1.1 = 2.73 Then VCs (pu) = 1.393/2.73 = 0.51 (pu) The peak voltage across the Cs is then: VCs = 0.51*100 = 51 volts B-4-4) The current through Cp The current through Cp is given by: ICp (pu) = VCp(pu)/XCp(pu) VCp (pu) = 0.877 XCp (pu) = (Q/F)*(Cp/Cs) (pu) =>XCp (pu) = 2.73*2 = 5.454 (pu) So ICp (pu) = 0.877/5.454 = 0.1607 (pu) So ICp = ICp(pu)*Iref = 0.1607*5.91 = 0.950 Amps B-4-5) The peak voltage across Leq The peak voltage across Leq is given by: VLeq (peak) = ILeq*XLeq = ILeq*2*π*f*Leq = 8.23*(2*π*100kHz*97.7μH) => VLeq (peak) = 505.41 volts C) Summary for component values and their power rating Leq = 97.74μH Ipeak = 8.23A, Vpeak = 505.41V 12 Cs = 0.0314μF Ipeak = 8.23A, Vpeak = 417.79V Cp = 0.0157μF Ipeak = 0.950A, Vpeak = 96.466V RL = 28.8Ω Imax = 4.166A, Vmax = 120V 2.4.2 Winding of the Transformer and Inductor The high frequency transformer shown in the power circuit schematic (figure 10) had to be hand wound to meet precisely the turns ratio required for the design. The transformer was wound by using an EI-type core. The following calculations will demonstrate how the transformer was constructed. Equation relating voltage to flux: Erms = 4*N*f*Фmax Where Фmax = Bc*Ac Bc = 0.1T (The transformer core will saturate at Bc = 0.5T according to the data sheets, therefore 0.1T is chosen for a large safety margin) Ac is simply the cross sectional area of the core which is also given in the data sheets as 247mm². => N = Erms/(4*f*Bc*Ac) = 120/(4*100kHz*0.1*247e-6) = 12 turns Therefore the secondary of the transformer will have 12 turns and the primary of the transformer will have 10 turns. This meets the turns ratio calculated in the previous section of 0.8 to 1. The series inductor winding was wound around a circular plastic insert and measured using a Z meter to get the desired Induction as calculated in the power circuit design 3.0 Test Procedure and Results 3.1 Testing Procedure The testing of the converter required a great deal of instruments to monitor voltages and currents at many different locations in the circuit. There is a voltmeter and current meter at the input to the power circuit from the AC to DC stage and another voltmeter and current meter placed across the load at the output of the power circuit. There is also a Hall Effect ammeter that is placed across the output of the Mosfet Bridge before the LCC section inside the power circuit. This ammeter connects up to one channel of the oscilloscope to monitor the current being supplied to the resonant converter. The other channel of the oscilloscope connects up across the output of the Mosfet Bridge to monitor the voltage at that point. The voltage should be a perfect square wave and the current should be a sinusoidal waveform at full load current (28.8Ω load). Figure 11 shows a 13 screen shot of the oscilloscope with the current and voltage being displayed. The diagram shows that the voltage across the output of the mosfets is about 82Vp-p and the current is just short of 11Ap-p. The current is displayed directly because the Hall Effect current meter is normalized to one ohm. Also note that the reason the voltage is so low is because the testing was done at a reduced voltage from the specified voltage because the circuit behaves oddly at the specified voltage. The frequency is also shown at 90.5 kHz. The design was for 100 kHz, but when winding the inductor and transformer there was some slight variation in the values that were calculated. That means that the circuit will not be at the resonant frequency unless the switching frequency from the control circuit is adjusted accordingly. Figure 11 - Voltage and Current at output of Mosfet Bridge There was also a second oscilloscope connected to two of the gating signals from the control circuit so the phase between them could be observed and recorded. Figure 12 shows an oscilloscope screen capture of the gate signals on Q1 and Q2. One can notice that they are perfectly in phase. As the phase control is adjusted in the control circuit they will begin to go out of phase to a maximum of 180 degrees. The same thing is happening between Q3 and Q4 simultaneously as the phase is adjusted. By adjusting the phase the output voltage can be varied. 14 Figure 12 - Gate signals Q1 and Q3 from the control circuit By setting up all the ammeters, voltmeters, and oscilloscopes in this configuration it was possible to monitor all vital parts of the converter simultaneously while varying things like input voltage, load resistance, and gate signal phase. The next section will display all the results that were obtained from the testing but first one must understand the procedure that was taken to obtain them. Step 1: First the DC converter was turned on at a low voltage (Vin = 27Vdc) and the switching frequency was adjusted so the resonant converter was operating correctly, meaning a square wave was appearing at the output of the mosfet bridge. Note the converter is fixed frequency type so after the frequency was adjusted once, it was left alone for the rest of the testing. Step 2: The experiment began by starting with full load resistance which is 30 ohms and then measuring the output voltage and current. Also recorded was the voltage and current at the output of the Mosfet Bridge along with the phase between the gate signals Q1 and Q2. Step 3: After all the data is recorded at full load then the load is decreased from 30 ohms to 40 ohms and all the same measurements are recorded again. The load was decreased several times and all measurements were recorded every time until the load was decreased to 120 ohms. Step 4: After all the results were obtained at the low input voltage the input voltage was then increased to 56Vdc. Step 1, 2, and 3 were then repeated. The voltage was then stepped up to the lower portion of the specified value which was 110Vdc. Step 1, 2, and 3 were then repeated again. Finally the input voltage was stepped up to the upper end of the specified voltage of 130Vdc. 15 3.2 Final Results and Analysis The testing went well when operating the converter at lower voltages. The first two tests were completed successfully; however when the input voltage was brought up to the specified value of 110Vdc and 130Vdc, problems began to occur. The circuit worked fine when operating at full load. As the load was decreased the output voltage would increase, which is normal, but then as the phase was adjusted on the control circuit to compensate the voltage back down to 120 V a component failed preventing further testing. It is not known what exactly happened but it is thought that perhaps two series mosfets came on at the same time while adjusting the phase and shorted out the DC power supply. It could also be that the duty cycle was slightly too large for the gating signals, causing the short circuit. The control board did continue to work after the incident narrowing the problem to the power board. A mosfet is suspected to be the cause of the problem but due to time limitations not much time was spent troubleshooting the circuit as a lot of useable data had already been collected when testing at low voltage. The first test conducted was with an input voltage of 27Vdc. Table 1 shows the results for this experiment. Table 1 Test results with Vin = 27Vdc Test #1 Load (ohms) 30 40 48 60 80 120 Vin (V) 27.1 27.1 27.1 27.1 27.1 27.1 Frequency: 91 Khz Vout (V) 28.33 31.97 33.96 35.26 37.24 38.81 Iout (A) 1 0.9 0.6 0.6 0.5 0.4 Phase (deg) 0 1.6 2.04 2.2 2.36 2.6 VAB (rms) 12.8 12.8 13.3 13.3 13.64 14 Iout (rms) 0.00536 0.00536 0.00416 0.0036 0.002 0.0024 The second test conducted was with an input voltage of 56Vdc. Table 2 shows the results for this experiment. Table 2 Test results with Vin = 56Vdc Test #2 Load (ohms) 30 40 48 60 80 120 Vin (V) 55.9 55.9 55.9 55.9 55.9 55.9 Frequency: 91 Khz Vout (V) 58.33 65.94 69.07 73.36 78.3 81.2 Iout (A) 2 1.7 1.7 1.4 1 0.7 16 Phase (deg) 0 1.46 1.46 1.92 2.1 2.32 VAB (rms) 26 26.8 26.7 27.1 27.6 28 Iout (rms) 0.0108 0.0092 0.0092 0.00768 0.00656 0.00504 The last test did not last very long before the power circuit failed. Table 3 and table 4 show the results that were obtained in test 3 and 4 respectively. Table 3 Test results with Vin = 110Vdc Test #3 Load (ohms) 30 Vin (V) 110 Frequency 91 Khz Vout (V) 117 Iout (A) 4 Phase (deg) 0 VAB (rms) 51.2 Iout (rms) 0.022 Phase (deg) ? VAB (rms) ? Iout (rms) ? Table 4 Test results with Vin = 130Vdc Test #4 Load (ohms) 30 Vin (V) 130 Frequency 91 Khz Vout (V) 143.53 Iout (A) 5 Figure 13 shows a graph of output voltage verses load resistance for the two different values of input voltage that were able to be obtained. One can see that as the load is decreased the output voltage will rise while the input voltage remains constant. Note that no phase adjustment is taking place to the gates of the mosfets to compensate for the load change at this time. Output Voltage vs. Load Output Voltage (V) 100 80 60 Vin = 27Vdc 40 Vin = 56Vdc 20 0 0 50 100 150 Load (ohms) Figure 13 - Plot of Vout vs. Load for Vin = 27V and Vin = 56V Figure 14 shows a graph of output current verses load resistance for the same two input voltages. One can see that as the load is decreased the output current is also decreased. 17 The current plot takes a kind of inverse look to that of the voltage plot as expected. The current plot has a few values that lie outside the curve that is otherwise smooth, due to some sort of experimental error. Output Current (amps) Output Current vs. Load 2.5 2 1.5 Vin = 27Vdc 1 Vin = 56Vdc 0.5 0 0 50 100 150 Load (ohms) Figure 14 - Plot of Iout vs. Load for Vin = 27V and Vin = 56V The last plot that was obtained from the results is shown in figure 15. The plot shows the phase between gate signals Q1 and Q2 verses load resistance. As the load is decreased the output voltage increases as shown in figure 13. The phase then has to be adjusted on the gate signals to compensate for that load change and bring the output voltage back down to specified value. The experiment did not make it as far as testing at the specified values so the phase was adjusted until the output voltage equalled the input voltage. One can see that as the load is decreased from full load that the phase has to be adjusted quite a bit initially to compensate the output voltage but then as the load continues to decrease the phase does not have to be adjusted very much to compensate. The curve becomes quite flat after the load decreases beyond 50 ohms. 18 Phase Between Q1 & Q2 (deg) Phase vs. Load 30 25 20 Vin = 27Vdc 15 Vin = 56Vdc 10 5 0 0 50 100 150 Load (ohms) Figure 15 - Plot of phase vs. Load for Vin = 27V and Vin = 56V 4.0 Recommendations Due to the hard work put in by all the members of the group to be able to meet the deadlines outlined in the first progress report, it is difficult to come up with recommendations of how it would be done differently if it were to be done again. The only thing that could have been improved in the design process was allowing more time for testing at the end. Each stage of the converter was tested before connecting it to the next stage and tested at low voltage before running it at full power. For this reason it was not expected that something would go wrong when ramping the input voltage to full power when the circuit worked fine at low power. If there had been more time at the end of the term it might have been possible to fix the circuit failure and take more measurements at high voltage. Also a further recommendation would be to implement automatic feedback control so that the phase could be adjusted without user input. 5.0 Conclusions Overall the project was a success converting DC voltages as it was supposed to and a great learning experience. There were problems that occurred however when the power circuit was brought up to the full specified input voltage. Due to time restrictions there was not much troubleshooting that took place after the circuit was damaged so it was never determined why the circuit failed at full voltage. It is suspected though that when adjusting the phase on the control circuit that perhaps the phase delay was too small and the input voltage was shorted across the Mosfet Bridge. There was a loud noise and a spark that occurred on the power board when it failed. Also the circuit breaker that was connected in series with the input of the power board had tripped. Combining all the 19 evidence together definitely leads one to a belief that the input voltage was shorted which could only have occurred if two series mosfets had turned on at the same time. However the control circuit was tested before connecting to the power board and seemed to work properly. The delay between the ‘out of phase signals’ was set precisely to the typical value given in the data sheets of 250ns. The circuit did work long enough though to gather all the data required to put together a detailed results section to this report. The only difference is that the input voltage was not at the full specified value. The design approach taken in this project was done very well despite the power board failure in the end. By calculating all the values of the control circuit and bench testing it to begin with, gave the group a good understanding of how it worked and why it was required for the soft switching of the mosfets. By reviewing Dr. Bhat’s paper on fixed frequency DC to DC resonant converters, it then became possible to begin calculations for all the values of components in the design. The circuit was then built and connected to the control circuit to be tested. The testing proved to be quite successful at low voltages so the group went ahead and got all the results required at the low voltage before going ahead and running the circuit at full power. The group was able to stay on track with the outlook of events that were scheduled to take place in the first progress report. Everyone worked hard and without a doubt has increased their knowledge substantially on fixed frequency DC to DC resonant converters. 20 References [1] Dr. Ashoka K.S Bhat, IEEE fellow, and Xiaodong Li, “Analysis and Design of a Fixed-Frequency Series-Parallel Resonant Converter with Capacitive output filter” Department of Electrical and Computer Engineering at the University of Victoria. [2] Bill Andreycak, “PHASE SHIFTED, ZERO VOLTAGE TRANSITION DESIGN CONSIDERATIONS and the C3875 PWM CONTROLLER” [3] Michael j. Shutton, “Characteristics of load resonant converters operated in a high power factor mode” 21