Download Design of Low Voltage, Low Power, Wide Input Range Fully CMOS

Design of Low Voltage, Low Power, Wide Input Range
Fully CMOS Analog Multiplier
Ali Rezaeia,b
a
Mehdi JafariPanaha,c
Department of Electrical Eng., Tafresh University, Tehran Ave., Tafresh, IRAN
b
Corresponding author, Email: [email protected]
c
Email: [email protected]
Abstract ̶ In this paper, a four quadrant voltage mode analog multiplier, which is an important component in many
applications, using CMOS transistors biased in the triode and saturation region is presented. The major
improvements of the proposed multiplier are reducing the power consumption, increasing the input range and
increasing the frequency bandwidth. The fully CMOS design of the multiplier makes it compatible with digital
technology. Simulation results with Hspice for 0.18μm CMOS process show that this new multiplier structure has
very low power consumption, low THD and wide frequency range, which make it suitable for varieties of analog
applications.
Keywords: CMOS Multiplier, Low voltage circuits, Low power design, Analog IC design
Introduction
Analog multipliers are the major building blocks in the signal processing circuits. Multipliers are used in the
modulators, PLL’s, AGC’s, detectors, frequency multipliers, neural networks, adaptive filters, fuzzy systems and
other applications.
The function of analog multiplier is that two signals x and y is applied to the inputs, and the output is a linear
product of these signals, 𝑍 = 𝐴0 𝑋𝑌. A0 is a constant value and it is called the multiplier gain and the maximum
value of A0 is equal to 1/𝑋𝑚𝑎𝑥 or 1/𝑌𝑚𝑎𝑥 [1].
The first solid state multiplier was presented by Gilbert [1] and then a variety of multipliers with different
characteristics have been presented [2-7]. Due to advances in digital technology in modern electronics, analog
circuits are required to be implemented in the same standard CMOS process for low-cost fabrication.
The multipliers can be implemented in two modes, the voltage mode and the current mode. Each one of these modes
can be realized with CMOS transistors which are biased in the saturation, triode or sub-threshold region. In [4]
multipliers are divided into eight categories, depending on the signals application methods, CMOS transistor
operation region and the nonlinear cancelation method. In this division, according to the transistor operation region,
the input signals can be applied to drain, source, gate and substrate. Some of categories presented in this reference
are not practical and also some of them have poor linearity, high power consumption and low bandwidth, which
make them unsuitable for some applications. In [3] a current mode multiplier is obtained for high speed applications.
This structure needs a circuit to produce 2x which should be very precise and increases the number of transistors and
power consumption. So it is not suitable for low voltage and low power applications. In [5] a voltage mode
multiplier is offered for low voltage applications, in which a common voltage is required for biasing the transistors
for the input y. Furthermore, to convert the output current to the voltage, resistor is used which is not suitable for
fully CMOS implementation. In [6] a current mode multiplier is presented in which the transistors operate in weak
1
inversion region. It is proposed for low voltage and low power applications. This structure has very low bandwidth
about a few tens of KHz, which is not suitable for high frequency applications.
Achieving a lower level of nonlinear error in CMOS technology is difficult compared to BJT counterpart because of
the different (I-V) relationship of them. Hence, traditional BJT structures cannot be used easily for CMOS
multipliers. Therefore, various linearization techniques have been used to compensate for the nonlinearity of the
square-law device, such as floating gate[10], signal attenuator[11], variable Transconductance[12], using differential
pair[5] and using bipolar characteristic of the CMOS transistors[6]. Differential structure, because of common
signals cancellation property, is frequently used to cancel the nonlinear term in the multiplier circuits [1-7].
Multiplier Circuit Analysis
Fig. 1 shows the block diagram of the proposed four-quadrant multiplier, consisting of single-quadrant multiplier
blocks and square-law blocks. In [4], for multiplier implementation, only single-quadrant multiplier or square law
multiplier have been used, whereas Fig. 1 that consist of single-quadrant blocks and square law blocks
simultaneously.
According to the block diagram shown in Fig. 1, one can write the following relationships:
Z1  K (Y  X )2  2K  Y  X  .  Y   V1
(1)
Z 2  K (Y  X )2  2K Y  X  . Y   V2
(2)
Where K is a constant, X and Y are the input signals and V1, V2 are the offset terms which have the same values. The
differential output signal 𝑍𝑑 = 𝑍1 − 𝑍2 becomes:
Z d  8K . X .Y
(3)
Fig. 1 Block diagram of the multiplier
A. Basic circuit
Fig. 2 illustrates the basic structure of the purposed multiplier shown schematically in Fig. 1. For implementation of
2
2
a multiplier using CMOS transistors, it is possible to use 𝑉𝐺𝑆
in the saturation region and 𝑉𝐺𝑆 × 𝑉𝐷𝑆 or 𝑉𝐷𝑆
in the
triode region [4]. In the basic structure of Fig. 2, since CMOS transistors operate in both saturation and triode
2
regions, for multiplier implementation, the combination of 𝑉𝐺𝑆
and 𝑉𝐺𝑆 × 𝑉𝐷𝑆 terms have been used.
2
Fig.2 Multiplier basic sub-circuit
In this paper, capital letters with capital subscripts are used for DC bias values, and lower case letters with lower
subscripts for ac signals and capital letters with lower case subscripts for instantaneous values are used, respectively.
Having neglected the short channel effect and channel length modulation, the drain current of CMOS transistor in
the triode and saturation region are given with equations (4) and (5), respectively [9].
1
𝐼𝑑 = 𝐾𝑁/𝑃 (𝑉𝑔𝑠 − 𝑉𝑇𝑁/𝑃 )2
(4a)
2
𝑉𝑔𝑠 > 𝑉𝑇𝑁 , 𝑉𝑑𝑠 > 𝑉𝑔𝑠 − 𝑉𝑇𝑁 𝑜𝑟
𝑉𝑑𝑔 > −𝑉𝑇𝑁
(NMOS)
(4b)
𝑉𝑔𝑠 < 𝑉𝑇𝑃 , 𝑉𝑔𝑑 > 𝑉𝑇𝑃
𝑉𝑑𝑔 < |𝑉𝑇𝑃 |
(PMOS)
(4c)
𝑜𝑟
1
2
𝐼𝑑 = 𝐾𝑁/𝑃 [2(𝑉𝑔𝑠 − 𝑉𝑇𝑁/𝑃 )𝑉𝑑𝑠 − 𝑉𝑑𝑠
]
(5a)
2
𝑉𝑔𝑠 > 𝑉𝑇𝑁 , 𝑉𝑑𝑠 < 𝑉𝑔𝑠 − 𝑉𝑇𝑁 𝑜𝑟
𝑉𝑑𝑔 < −𝑉𝑇𝑁
(NMOS)
(5b)
𝑉𝑔𝑠 < 𝑉𝑇𝑃 , 𝑉𝑑𝑔 < 𝑉𝑇𝑃
𝑉𝑑𝑔 > |𝑉𝑇𝑃 |
(PMOS)
(5c)
𝑜𝑟
Where, 𝐾𝑁/𝑃 = 𝜇𝑁/𝑃 𝐶𝑜𝑥 𝑊/ 𝐿 is the transconductance parameter, W is transistor width, L is transistor length, 𝜇𝑛/𝑝 is
carrier mobility, 𝐶𝑜𝑥 is the gate capacitance per unit area, and 𝑉𝑇𝑁/𝑃 is the threshold voltage of the NMOS and
PMOS transistors, respectively.
In this circuit, when the input signals are zero, all transistors are in the triode region and when the non-zero inputs
are applied, transistors M1 and M4 are in the saturation region and transistor M2 and M3 are in the triode region or
wise versa. Assuming that transistors M1 and M4 are in the saturation region and transistor M2 and M3 are in the
triode region we have:
1
𝐼𝑑1 = 𝐾𝑃1 [(𝑦 + 𝑥 + 𝑉𝐺𝑆 − 𝑉𝑇𝑃 )2 ]
(6a)
2
1
𝐼𝑑2 = 𝐾𝑃2 [2(𝑦 − 𝑥 + 𝑉𝐺𝑆 − 𝑉𝑇𝑃 )(𝑦 − 𝑉2 ) − (𝑦 − 𝑉2 )2 ]
(6b)
2
1
𝐼𝑑3 = 𝐾𝑃3 [2(−𝑦 − 𝑥 + 𝑉𝐺𝑆 − 𝑉𝑇𝑃 )(−𝑦 − 𝑉1 ) − (−𝑦 − 𝑉1 )2 ]
2
1
𝐼𝑑4 = 𝐾𝑃4 [(−𝑦 + 𝑥 + 𝑉𝐺𝑆 − 𝑉𝑇𝑃 )2 ]
(6c)
(6d)
2
Where 𝑉𝐺𝑆 is the bias voltage due to the flow of the bias current 𝐼𝐵 /2 in each transistor, 𝑉𝑇𝑃 is threshold voltage, x
and y are input signals and 𝑉1 , 𝑉2 are constant DC voltages. In the Fig. 2, the output currents 𝐼𝑜1 and 𝐼𝑜2 can be
written as:
𝐼𝑜1 = 𝐼𝑑1 + 𝐼𝑑3
(7)
3
𝐼𝑜2 = 𝐼𝑑2 + 𝐼𝑑4
(8)
Currents 𝐼𝑜1 and 𝐼𝑜2 have the signal components, 𝑖𝑜 , and DC components, 𝐼𝐵 , i.e. (𝐼𝑜 = 𝑖𝑜 + 𝐼𝐵 ). The output current
is defined as the difference between 𝐼𝑜1 and 𝐼𝑜2 . Using equations (6), (7), (8) and assume equal KP, yields:
1
𝐼𝑜1 − 𝐼𝑜2 = 𝐾𝑃 [8𝑥𝑦 + 2𝑉𝑇𝑃 (𝑉1 − 𝑉2 ) + 2(𝑉22 − 𝑉12 ) + 2𝑥(𝑉1 − 𝑉2 )]
2
(9)
𝑉1 , 𝑉2 will be obtained in equations (10) and (11), respectively.
B. Analysis of the proposed multiplier circuit
The proposed multiplier circuit is shown in Fig. 3. In this circuit, the transistor M1 to M4 form the basic circuit of
Fig. 2, transistors M5 to M9 are current mirror source which provide the bias current IB, and M8, M9 are in the triode
region and transistors M10 to M13 are used as linear resistors which convert the output currents to the output voltages.
Considering equations (6) to (8) for the circuit of Fig. 3, the differential output current is the same as equation (9).
Fig. 3 Proposed multiplier circuit
According to the circuit of Fig. 3, we have:
𝑉1 = 𝑉𝐺𝑆12 = 𝑉𝐷𝐷 − 𝑉𝐺𝑆10
(10)
𝑉2 = 𝑉𝐺𝑆13 = 𝑉𝐷𝐷 − 𝑉𝐺𝑆11
(11)
Since the circuit is perfectly symmetrical and assuming transistor matching, then 𝑉𝐺𝑆10 = 𝑉𝐺𝑆11 and according to
equations (10) and (11), 𝑉1 = 𝑉2 . By substituting in equation (9), the DC values are removed and we have only the
signal values:
𝑖𝑜 = 𝐼𝑜1 − 𝐼𝑜2 = 4𝐾𝑃 . 𝑥. 𝑦
(12)
C. Differential active linear resistance
4
Using active resistors instead of passive resistors causes fully CMOS implementation of the circuit with lower area
occupation on the chip. In the circuit of Fig. 3, transistors M10 to M13 are used as linear resistors for converting the
output current to the voltage. For convenience, this part of the circuit is shown in Fig. 4.
Fig. 4 Differential active linear resistor Circuit
In the circuit shown in Fig. 4, all four transistors are in the saturation region. By writing KCL at the output node,
𝑉𝑜1 , we have:
𝐼𝑜1 + 𝐼𝐷10 − 𝐼𝐷12 = 0
(13)
Where:
1
𝐼𝐷10 = 𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑜1 − 𝑉𝑇𝑁10 )2
(14)
2
1
𝐼𝐷12 = 𝐾𝑁 (𝑉𝑜1 − 𝑉𝑇𝑁12 )2
(15)
2
By combining equations (13), (14) and (15), the output voltage, 𝑉𝑜1 , can be found in terms of the output current 𝐼𝑜1
(𝐼𝑜1 = 𝑖𝑜1 + 𝐼𝐵 ), as follows:
𝑉𝑜1 =
𝑖𝑜1 + 𝐼𝐵
𝑉𝐷𝐷 + 𝑉𝑇𝑁12 − 𝑉𝑇𝑁10
+
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁12 − 𝑉𝑇𝑁10 )
2
(16)
Similarly:
𝑉𝑜2 =
𝑖𝑜2 + 𝐼𝐵
𝑉𝐷𝐷 + 𝑉𝑇𝑁13 − 𝑉𝑇𝑁11
+
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁13 − 𝑉𝑇𝑁11 )
2
(17)
Considering equations (16) and (17) and since 𝑉𝑇𝑁10 = 𝑉𝑇𝑁11 and 𝑉𝑇𝑁12 = 𝑉𝑇𝑁13 , we have:
𝑉𝑜1 − 𝑉𝑜2 =
𝐼𝑜1 − 𝐼𝑜2
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁11 − 𝑉𝑇𝑁13 )
(18)
From equation (18), the differential output resistor can be obtained as follows:
𝑅𝑑𝑖𝑓𝑓 =
𝑉𝑜1 − 𝑉𝑜2
1
=
𝐼𝑜1 − 𝐼𝑜2
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁11 − 𝑉𝑇𝑁13 )
(19)
By substituting equation (12) into equation (18), the differential output voltage is:
𝑣𝑜 = 𝑉𝑜1 − 𝑉𝑜2 =
4. 𝐾𝑃 . 𝑥. 𝑦
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁11 − 𝑉𝑇𝑁13 )
(20)
5
D. Inspection of operation region of transistors
Since in the proposed multiplier, the wide input range with comparable linearity is obtained by using CMOS
transistors biased in the triode and saturation region complementary, careful inspection of operation region of
transistors are presented in detail.
a) Transistors M11-M13, M10 - M12
Operation of transistors M11-M13 is completely similar to transistors M10 - M12. For proper circuit functionality, all
four transistors, which are used as active load, must be in the saturation region. Equation (4b) gives the conditions
for NMOS transistors to be in the saturation regions.
According to Fig. 3, the gate-drain voltage of the active load transistors are zero and noticing that the threshold
voltage of an NMOS is positive, so equation 𝑉𝐷𝐺 > −𝑉𝑇𝑁 is always established and if equation 𝑉𝐺𝑆 > 𝑉𝑇𝑁 is
achieved the transistors will be in the saturated region.
Equations (21) to (24) can be written, by assumption that transistors M11-M13, M10- M12 operate in the saturation
region.
𝐼𝐷10 + 𝐼𝑜1 − 𝐼𝐷12 = 0
(21)
1
𝐼𝐷10 = 𝐾𝑁 (𝑉𝐺𝑆10 − 𝑉𝑇𝑁10 )2
(22)
2
1
𝐼𝐷12 = 𝐾𝑁 (𝑉𝐺𝑆12 − 𝑉𝑇𝑁12 )2
(23)
𝑉𝐺𝑆12 = 𝑉𝐷𝐷 − 𝑉𝐺𝑆10
(24)
2
Considering the DC values, 𝐼𝑜1 will be equal to 𝐼𝐵 and by combining equations (21) to (24) the gate-source voltages,
𝑉𝐺𝑆10 and 𝑉𝐺𝑆12 , are obtained as follows:
𝑉𝐺𝑆10 =
𝑉𝐷𝐷 + 𝑉𝑇𝑁10 − 𝑉𝑇𝑁12
𝐼𝐵
−
(𝑉
2
𝐾𝑁 𝐷𝐷 − 𝑉𝑇𝑁12 − 𝑉𝑇𝑁10 )
(25)
𝑉𝐺𝑆12 =
𝑉𝐷𝐷 + 𝑉𝑇𝑁12 − 𝑉𝑇𝑁10
𝐼𝐵
+
2
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁12 − 𝑉𝑇𝑁10 )
(26)
According to equations (25), (26), regarding to the values of the technology parameters and the bias current, IB, it
can be concluded that:
𝑉𝐺𝑆10 > 𝑉𝑇𝑁10
(27)
𝑉𝐺𝑆12 > 𝑉𝑇𝑁12
transistors M11-M13, M10- M12 are in the saturation region.
(28)
Hence,
b) Transistors M1, M2, M3 & M4
In circuit of Fig 3., when the input signals are zero, transistors M1, M2, M3 and M4 are in the triode region. Since the
circuit is symmetrical and assuming matching between transistors, when the non-zero inputs are applied, transistors
M1 and M4 are in the saturation region and M2 and M3 are in the triode region or wise versa. Hence, we just obtain
the operation region of M1 and M2 for non-zero inputs.
c) Condition of operating M1 in the triode region
In order to M1 to be in the triode region, equation (5c) must be satisfied. According to Fig. 3, the body effect are not
canceled in M1, M2, M3 and M4; 𝑉𝑆𝐵 ≠ 0, and 𝑉𝑇𝑃 can be obtained from equation (29)[8].
6
𝑉𝑇𝑃 = |𝑉𝑇𝑃0 + 𝛾 (√2|𝜙𝑓 | + |𝑉𝑠𝑏 | − √2|𝜙𝑓 | ) | , 𝑉𝑠𝑏 = |𝑦 − 𝑉𝐷𝐷 |
(29)
where 𝑉𝑇𝑃0 is the threshold voltage when 𝑉𝑆𝐵 = 0, 𝛾 is the body effect coefficient, and 𝜙𝑓 is the Fermi potential.
As it can be seen in equation (29), the input y signal affects 𝑉𝑇𝑃 and hence affects equation (5c).
Using equation (5c) we have:
𝑉𝐷 − 𝑉𝐺 > |𝑉𝑇𝑃 | ,
𝑉𝐺 = 𝑥,
𝑉𝐷 = 𝑉𝐺𝑆12
(30)
By combining equations (29) and (30) we obtaine:
𝑥 < 𝑉𝐺𝑆12 − |𝑉𝑇𝑃0 + 𝛾 (√2|𝜙𝑓 | + |𝑦 − 𝑉𝐷𝐷 | − √2|𝜙𝑓 | ) |
(31)
If y has its minimum value, then 𝑉𝑇𝑃 will be maximum and if the equation (31) is satisfied, then M1 would be in the
triode region. If y is has the maximum value, 𝑉𝑇𝑃 will be minimum and if the following equation (32) is satisfied,
then M1 will be in the saturation region.
𝑥 > 𝑉𝐺𝑆12 − |𝑉𝑇𝑃0 + 𝛾 (√2|𝜙𝑓 | + |𝑦 − 𝑉𝐷𝐷 | − √2|𝜙𝑓 | ) |
(32)
It should be noted that when the gate voltage of M1 has the maximum value, the gate voltage of M2 is minimum and
vice versa. Therefore, it can be concluded that when M1 operates in the saturation region, M2 is in the triode region
and when M1 operates in the triode region M2 is in the saturation region. There are the same conditions for M3 and
M4. Hence, according to the input signals, when M1 and M4 are in the triode region, M2 and M3 are in the saturation
region and vice versa. In all cases, equation (12) represents the multiplication of two signals.
E. Input Range
If x and y have their maximum values, according to the equation (32), M1 and M4 will be in the saturation region
and saturation of the transistors determines the maximum input range.
We have:
|𝑥𝑚𝑎𝑥 | + |𝑦𝑚𝑎𝑥 | + 𝑉𝐺𝑆 < 𝑉𝑇𝑃
(33)
According to equation (4a) VGS of the transistors M1, M2, M3 and M4 in saturation region can be obtained as
follows.
𝑉𝐺𝑆 = −√
𝐼𝐵
+ 𝑉𝑇𝑃
𝐾𝑃
(34)
Substituting equation (34) into equation (33) and assuming that both inputs x, y have equal swings, then we have:
𝐼𝐵
|𝑉𝑖,𝑚𝑎𝑥 | < 0.5√
𝐾𝑃
(35)
As it can be seen from equation (35), the maximum input range depends on IB and the technology parameters.
F. Power Consumption
Since PMOS transistors need lower drain current in comparison with NMOS transistors, they are good choices for
input stage operated in the saturation or triode regions in order to decrease the power consumption [2]. In [2, 5, 6, 7],
transistors biasing requires extra circuits which causes an increase in the power consumption, but in the proposed
multiplier circuit, for biasing, only the current source have been used that is one of major reasons to reduce the
power consumption.
7
The power consumption for the circuit of Fig. 3 is:
𝑃𝑇 = 𝑉𝐵 𝐼𝐵 + 𝑉𝐷𝐷 𝐼𝑇
(36)
Where, 𝑉𝐷𝐷 is supply voltage, 𝐼𝐵 is the value of the current source and 𝑉𝐵 is the voltage across this current
source, 𝐼𝑇 is the total current and can be obtained as follows:
𝐼𝑇 = 𝐼𝐷5 + 𝐼𝐷6 + 𝐼𝐷7 + 𝐼𝐷10 + 𝐼𝐷11
(37)
In the circuit of Fig. 3, we have:
𝐼𝐷5 = 𝐼𝐷6 = 𝐼𝐷7 = 𝐼𝐵 , 𝐼𝐷10 = 𝐼𝐷11
(38)
2
1
𝑉𝐷𝐷 + 𝑉𝑇𝑁10 − 𝑉𝑇𝑁12
𝐼𝐵
𝐼𝐷10 = 𝐾𝑁 (
−
– 𝑉𝑇𝑁10 )
2
2
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁12 − 𝑉𝑇𝑁10 )
𝑉𝐵 = 𝑉𝐷𝐷 − 𝑉𝑆𝐺5 = 𝑉𝐷𝐷 − √
2𝐼𝐵
− |𝑉𝑇𝑃5 |
𝐾𝑃
(39)
(40)
According to equations (36) to (40), the power consumption is obtained as follows:
2
𝑉𝐷𝐷 + 𝑉𝑇𝑁10 − 𝑉𝑇𝑁12
𝐼𝐵
𝑃𝑇 = (3𝐼𝐵 𝑉𝐷𝐷 + 𝑉𝐷𝐷 𝐾𝑁 (
−
− 𝑉𝑇𝑁10 )
2
𝐾𝑁 (𝑉𝐷𝐷 − 𝑉𝑇𝑁12 − 𝑉𝑇𝑁10 )
+ 𝐼𝐵 (𝑉𝐷𝐷 − √
2𝐼𝐵
− |𝑉𝑇𝑃5 |))
𝐾𝑃
(41)
It should be noted from equation (41) that increasing IB will increase the power consumption.
G. Frequency Response
Although the precise calculation of frequency responses is most often left to computer simulations, there is much
insight that can be obtained by finding the dominant frequency effects in integrated circuits [9]. In the presented
circuit of Fig. 3, because of the simple method of applying the input signals (the inputs are applied to the gate and
source directly) and considering short channel length for the transistors, the proposed multiplier has relatively high
cut of frequency. The active resistors used in Fig. 3 have the maximum effect on the frequency response
characteristic. For each one of the outputs, the dominant pole frequency can be
considered as follows:
𝜔𝑝1,2 =
1
𝑅𝑜1,2 . 𝐶𝑜1,2
(42)
For the output node, 𝑉𝑜1 , we have:
𝑅𝑜1 =
1
𝑔𝑚10 + 𝑔𝑚12
,
𝐶𝑜1 = 𝐶𝑔𝑠10 + 𝐶𝑔𝑠12
(43)
According to equations (42) and (43):
𝜔𝑝1 =
𝑔𝑚10 + 𝑔𝑚12
𝐶𝑔𝑠10 + 𝐶𝑔𝑠12
(44)
8
The dominant pole frequency of 𝑉𝑜2 is actually equal to that of 𝑉𝑜1 . Since small area transistors are used, the gatesource capacitors are small and hence according to (44) it is expected that the cut-off frequency will be large.
Simulation Results
The designed multiplier circuit of Fig. 3 was simulated using Hspice for 0.18µm CMOS process with main
parameters of 𝑉𝑇𝑁0 = 0.486𝑣, 𝑉𝑇𝑃0 = −0.46𝑣, IB=5µA and 𝑉𝐷𝐷 = 1.2𝑣.
Transistors sizes are shown in Tab. 1; these sizes are selected in order to optimize power consumption, input range
and bandwidth.
TAB. 1 TRANSISTORS DIMENSOIN
W(µm)
TRANSISTOR
M1,M2,M3,M4
L(µm)
0.3
0.6
M5,M6,M7,M8,M9
15
1
M10,M11,M12,M13
0. 22
1
In section 3, the analysis of the maximum input range has been done. According to (35), the maximum input range is
a function of the bias current, IB, and this current has selected regarding to the trade-offs between the maximum
input range, power consumption and bandwidth.
(Fig. 5a) shows simulated DC transfer characteristics of the proposed multiplier, when x was swept continuously
from -0.3v to 0.3v while y was varied from -0.3v to 0.3v with 0.1v step size. It can be seen that the maximum input
range is %50 of the power supply voltage and the multiplier is four quadrants. Since in the proposed multiplier
circuit of Fig. 3, 𝐼𝐵 = 5µ𝐴 and 𝑊𝑝/𝐿𝑝 = 0.3µ𝑚/0.6µ𝑚, simulation result validates the theoretical calculations
offered in (35). The derivative of the transfer characteristic is show in (Fig. 5b) which illustrates the error
performances of the DC transfer characteristic. In section 4, the analysis of the power consumption has been carried
out which resulted to equation (41). Simulation results shows a power consumption about 33µw, which is in
agreement with the theoretical calculations.
(a)
(b)
Fig. 5 (a) DC transfer characteristic (b) Error performances of the DC characteristic
9
In order to demonstrate the application of the proposed multiplier in a modulator circuit, transient response
simulation for the input signals 𝑦 = 0.3𝑣𝑝−𝑝 − 1𝐺𝐻𝑧, 𝑎𝑛𝑑 𝑥 = 0.3𝑣𝑝−𝑝 − 100𝑀𝐻𝑧 is shown in (Fig. 6a). To
illustrate the nonlinearity characteristics of the modulator circuit, the frequency spectrum of the output waveform is
shown in (Fig. 6b).
(a)
(b)
Fig. 6 (a) Output transient responses (b) Frequency spectrum of the waveform in Fig. 6
Frequency response simulation result of the proposed circuit is shown in Fig. 7 with the input signal 𝑥 = 0.3 𝑣. As it
can be seen, the circuit has high bandwidth of 3.7GHz which makes the circuit suitable for high frequency
applications.
By increasing the amplitude of the input signals, the non-linear effects of the CMOS transistors will be increased.
This causes an increase in the THD and non-linear effect in the DC characteristic. There is a direct relationship
between the THD and the multiplier circuit linearity, when 𝑥 = 0.3sin(2𝜋105 𝑡)𝑣 and 𝑦 = 0.3𝑣 are applied to the
inputs, the THD is equal to 0.69% and for inputs 𝑦 = 0.3sin(2𝜋105 𝑡)𝑣 and 𝑥 = 0.3𝑣, the THD of 0.74% is
achieved. Fig. 8 shows the THD values for various DC inputs x and y.
Fig. 7 Frequency response of the proposed multiplier
10
Fig. 8 THD as a function of the input signal x & y
Tab. 2, represents a performance comparison between the proposed circuit with references [2, 5,7]; which shows
that the proposed multiplier has better characteristics.
TAB. 2
COMPARISON OF THE PROPOSED CIRCUIT WITH [2,5,7]
𝑇ℎ𝑖𝑠 𝑤𝑜𝑟𝑘
[2]
[5]
[7]
𝑉𝐷𝐷
1.2
1.5
1.2
1.5
𝑃𝑜𝑤𝑒𝑟(𝜇𝑤)
33
32
113
290
0.74
---
1.1
---
3.7
1.98
1
0.1
± 0.3
±0.2
𝑇𝐻𝐷(%)
𝐵𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ(𝐺𝐻𝑍)
𝐼𝑛𝑝𝑢𝑡 𝑅𝑎𝑛𝑔𝑒
± 0.3 ±0.4
Conclusion
A four quadrant analog multiplier circuit using CMOS transistors biased in the triode and saturation region is
designed and simulated. The proposed multiplier offers reduced power consumption, increased input range and
increased bandwidth, which makes it suitable for high frequency, low power applications. The fully CMOS design
of the multiplier is an advantage for low cost implementation using standard digital CMOS technology. The
proposed circuit has been simulated with Hspice for 0.18μm CMOS process. The power supply voltage of circuit is
1.2v. The simulation results shown that the THD is less than 0.74% for input frequency of 100KHz, -3dB bandwidth
is 3.7GHz and the power consumption is about 33μw.
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