Download 1 Basic Digital Concepts

1 Basic Digital Concepts
By converting continuous analog signals into a finite number of discrete
states, a process called digitization, then to the extent that the states are
suffiently well separated so that noise does create errors, the resulting digital
signals allow the following (slightly idealized):
_ storage over arbitrary periods of time
_ flawless retrieval and reproduction of the stored information
_ flawless transmission of the information
Some information is intrinsically digital, so it is natural to process and
manipulate it using purely digital techniques. Examples are numbers and
words. The drawback to digitization is that a single analog signal (e.g. a
voltage which is a function of time, like a stereo signal) needs many discrete
states, or bits, in order to give a satisfactory reproduction. For example, it
requires a minimum of 10 bits to determine a voltage at any given time to an
accuracy of _ 0:1%. For transmission, one now requires 10 lines instead of
the one original analog line. The explosion in digital techniques and
technology has been made possible by the incredible increase in the density
of digital circuitry, its robust performance, its relatively low cost, and its
speed. The requirement of using many bits in reproduction is no longer an
issue:
The more the better. This circuitry is based upon the transistor, which can be
operated as a switch with two states. Hence, the digital information is
intrinsically binary. So in practice, the terms digital and binary are used
interchangeably. In the following sections we summarize some conventions
for defining the binary states and for doing binary arithmetic.
ANALOGUE vs. DIGITAL
To make some sense of the 'analogue vs. digital' debate, let's firstly establish
what the two terms mean. In the case of digital electronics, we're talking
about two different methods of sending an electronic signal from A to B.
ANALOGUE signals are continuous, and can take any value.
DIGITAL signals encode values into binary numbers. As a binary number is
made up entirely from 0's and 1's, it may be transmitted in the form of
electronic on/off pulses (on =1, off =0). When these pulses are recieved, they
are processed. A digital signal is made up of discretely variable physical
quanitities.While these two types of signal both transmit information in
electrical voltages, they each have their advantages and disadvantages. One
of the most heated analogue/digital arguments takes place within the audio
and recording industry. Here, (putting it a little simplistically), analogue
systems are useful, because they can give a faithful electronic representation
of a complex waveform. However, because of the need for amplification of
the electronic signal, 'noise' can be added along the signal path (figure 1).
This noise is due to unavoidable electron activity in the circuitry.
Unfortunately though, there is no easy way of differentiating this unwanted
noise from the original signal. Consequently, the noise (audible as a 'hiss') is
added to the signal with each stage of transmission.
Figure 1: Analogue signal path in a hi-fi system
____________
____________
____________
|
|
|
|
|
|
| SOURCE |------->| AMPLIFIER |------->| SPEAKERS |
|____________| ^ |____________|
|____________|
^
voltage
A digital equivalent to this system would sample the sound wave at selected
intervals and transmit the values that correspond to the sound wave in binary
code. The digital representation of the sound wave could then be moved
around or processed within the system without picking up any additional
noise. Although the electron (noise) activity is still taking place, whenever
the digital signal is repeated, during each stage of the transmission, the noise
can be discarded.
Figure 2: Signal path in a digital/analogue hi-fi system
____________
____________
_____________
|
|
|
|
|
|
|
|------->| ANALOGUE |------->| DIGITAL |
| MIC |
| TO DIGITAL |
| (NOISELESS) |
|
|
| CONVERTER |
| HI-FI |
|____________|
|____________|
|_____________|
|
______v_______
|
|
| DIGITAL TO |
| ANALOGUE |
| CONVERTER |
|______________|
|
______v_______
|
|
| AMPLIFIER |
|______________|
|
______V_______
|
|
| SPEAKERS |
|______________|
The main disadvantage of the above system (apart from its complexity) is
that it cannot deal with a continuous series of values. As the soundwave is
only examined or sampled at given points in time, a true representaion of the
wave cannot be given digitally.
Here, then, is a summary of the advantages and disadvantages of the two
systems:
ANALOGUE
DIGITAL
Potential for more
Can be very immune to
'faithful' reproduction
noise
Noise and distortion
Output subject to
problems
quantity errors from sampling
Usually simple
Very long distances possible
Can be complex
1.1 Binary Logic States
The following table attempts to make correspondences between conventions
for defining binary logic states. In the case of the TTL logic gates we will be
using in the lab, the Low voltage state is roughly 0{1 Volt and the High state
is roughly 2:5{5 Volts. See page 475 of the text for the exact conventions
for TTL as well as other hardware gate technologies.
Boolean Logic Boolean Algebra Voltage State Voltage State
(positive true) (negative true )
True (T) 1 High (H) Low (L)
False (F) 0 L H
The convention for naming these states is illustrated in Fig. 1. The \positive
true" case is illustrated. The relationship between the logic state and label (in
this case \switch open") at some point in the circuit can be summarized with
the following:
The labelled voltage is High (Low) when the label's stated function is True
(False). In the _gure, the stated function is certainly true (switch open), and
this does correspond to a high voltage at the labelled point. (Recall that with
the switch open, Ohm's Law implies that with zero current, the voltage
di_erence across the \pull up" resistor is zero, so that the labelled point is at
+5 Volts. With a closed switch, the labelled point is connected to ground,
with a 5 Volt drop across the resistor and a current of I = V=R = 5 mA
through it.)
Figure 1: Illustration for labelling logic states (\positive true").With the
convention known as \negative true", the label would be changed to \switch
closed" with a bar over it: switch closed. Our statement becomes:The
labelled voltage is Low (High) when the label's stated function is True
(False).So in the _gure, the stated function (switch closed) is true when the
voltage is low. The bar is meant to envoke the boolean inversion operation:
_T = F, _F = T, __T = T, and so forth.
1.2 Binary Arithmetic
Each digit in binary is a 0 or a 1 and is called a bit, which is an abbreviation
of binary digit.
There are several common conventions for representation of numbers in
binary.
The most familiar is unsigned binary. An example of a 8-bit number in this
case is
010011112 = 0_27 + 1_26 +_ _ _+ 1_20 = 64 + 8 + 4 + 2 + 1 = 7910
(Generally the subscripts will be omitted, since it will be clear from the
context.) To convert from base 10 to binary, one can use a decomposition
like above, or use the following algorithm illustrated by 79: 79=2 = 39,
remainder 1, then 39=2 = 19 r 1, and so forth. Then assemble all the
remainders in reverse order.
The largest number which can be represented by n bits is 2n - 1. For
example, with 4 bits the largest number is 11112 = 15.
The most significant bit (MSB) is the bit representing the highest power of
2, and the LSB represents the lowest power of 2.
Arithmetic with unsigned binary is analogous to decimal. For example 1-bit
addition and multiplication are as follows: 0 + 0 = 0, 0 + 1 = 1, 1 + 1 = 0, 0
_0 = 0, 0_1 = 0, and 1 _ 1 = 1. Note that this is different from Boolean
algebra, as we shall see shortly, where 1 + 1 = 1.
Another convention is called BCD (\binary coded decimal"). In this case
each decimal digit is separately converted to binary. Therefore, since 7 =
01112 and 9 = 10012, then 79 = 01111001 (BCD). Note that this is different
than our previous result. We will use BCD quite often in this course. It is
quite convenient, for example, when decimal numerical displays are used.
1.2.1 Representation of Negative Numbers
There are two commonly used conventions for representing negative
numbers.
With sign magnitude, the MSB is used to flag a negative number. So for
example with 4-bit numbers we would have 0011 = 3 and 1011 = -3. This is
simple to see, but is not good for doing arithmetic. With 2's complement,
negative numbers are designed so that the sum of a number and its 2's
complement is zero. Using the 4-bit example again, we have 0101 = 5 and
its 2's complement -5 = 1011. Adding (remember to carry) gives 10000 = 0.
(The 5th bit doesn't count!) Both addition and multiplication work as you
would expect using 2's complement. There are two methods for forming the
2's complement:
1. Make the transformation 0 ! 1 and 1!0, then add 1.
2. Add some number to -2MSB to get the number you want. For 4-bit
numbers an
example of finding the 2's complement of 5 is -5 = -8 + 3 = 1000 + 0011 =
1011.
1.2.2 Hexadecimal Representation
It is very often quite useful to represent blocks of 4 bits by a single digit.
Thus in base
16 there is a convention for using one digit for the numbers 0,1,2,: : :,15
which is called
hexadecimal. It follows decimal for 0{9, then uses letters A{F.
Decimal Binary Hex
2 Logic Gates and Combinational Logic
2.1 Gate Types and Truth Tables
The basic logic gates are AND, OR, NAND, NOR, XOR, INV, and BUF.
The last two are not standard terms; they stand for \inverter" and \bu_er",
respectively. The symbols for these gates and their corresponding Boolean
expressions are given in Table 8.2 of the text which,for convenience, is
reproduced (in part) in Fig. 2.
All of the logical gate functions, as well as the Boolean relations discussed
in the next section, follow from the truth tables for the AND and OR gates.
Wereproduce these below.
We also show the XOR truth table, because it comes up quite often,
although, as we shall see, it is not elemental.
2.2 Boolean Algebra and DeMorgan's Theorems
Boolean algebra can be used to formalize the combinations of binary logic
states. The
fundamental relations are given in Table 8.3 of the text. In these relations, A
and B are
binary quantities, that is, they can be either logical true (T or 1) or logical
false (F or 0).
Most of these relations are obvious. Here are a few of them:
AA = A ; A + A = A ; A + A = 1; AA = 0; A = A
Recall that the text sometimes uses an apostrophe for inversion (A0). We use
the standard over bar notation (A).We can use algebraic expressions to
complete our definitions of the basic logic gates we began above. Note that
the Boolean operations of \multiplication" and \addition" are defined by the
truth tables for the AND and OR gates given above in Figs. 3 and 4. Using
these definitions, we can define all of the logic gates algebraically. The truth
tables can also
be constructed from these relations, if necessary. See Fig. 2 for the gate
symbols.
_ AND: Q = AB (see Fig. 3)
_ OR: Q = A + B (see Fig. 4)
_ NAND: Q = AB
_ NOR: Q = A + B
_ XOR: Q = A _ B (defined by truth table Fig. 5)
_ INV: Q = A
_ BUF: Q = A
2.2.1 Example: Combining Gates
Let's re-express the XOR operation in terms of standard Boolean operations.
The following
truth table evaluates the expression Q = AB + AB.
We see that this truth table is identical to the one for the XOR operation.
Therefore, we
can write
A _ B = AB + AB (1)
A schematic of this expression in terms of gates is given in Fig. 6 (as well as
Fig. 8.25 of
the text). Recall that the open circles at the output or input of a gate
represent inversion.
2.2.2 Gate Interchangeability
In an example from the homework, we can make an INV gate from a 2-input
NOR gate.
Simply connect the two inputs of the NOR gate together. Algebraically, if
the two original NOR gate inputs are labeled B and C, and they are
combined to form A, then we have=B+C =A+A=A, which is the INV
operation.
Note that an INV gate can not be made from OR or AND gates. For this
reason the OR and AND gates are not universal. So for example, no
combination of AND gates can be combined to substitute for a NOR gate.
However, the NAND and NOR gates are universal.
2.2.3 DeMorgan
Perhaps the most interesting of the Boolean identities are the two known as
DeMorgan's
Theorems:
A + B = _ A _ B (or; A+B = _A_B) (2)
AB = A + B (or; AB =A+B) (3)
These expressions turn out to be quite useful, and we shall use them often.
An example of algebraic logic manipulation follows. It is the one mentioned
at the end
of Lab 1. One is to show that an XOR gate can be composed of 4 NAND
gates. From the
section above we know A _ B = AB + AB. Since AA = 0 and BB = 0, we can
add these,
rearrange, and apply the two DeMorgan relations to give
A _ B = A(A + B) +B(A+B) = A(AB) +B(AB) = _A(AB)__B(AB)_
2.3 Symbolic Logic
The two DeMorgan expressions above can be envoked using gate symbols
by following this
prescription: Change gate shape (AND$OR) and invert all inputs and
outputs.
By examining the two rightmost columns of Fig. 2, one sees that the
transformation
between 3rd and 4th columns for the gates involving AND/OR gates works
exactly in this
way. For example, the DeMorgan expression AB = A+B is represented
symbolically by the
equivalence between the 3rd and 4th columns of the 2nd row (\NAND") of
Fig. 2. We will
go over how this works, and some more examples, in class.
Notes
Digital Electronics
(MCA 103)
Lesson 6
Binary codes:
Digital systems represent and manipulate not only binary numbers, but also many
other discrete elements of information. Any discrete element of information distinct
among a group of quantities can be represented by a binary code.
Minimum number of bits required to code 2n distinct quantities is n. There is no
maximum number of bits that may be used for a binary code.
BCD Codes:
The BCD(Binary Coded Decimal) is a code which assigns the decimal equivalent
of each and every digit of the decimal number. The weights in the BCD code are 8,4,2,1.
The bit assignment 0110, for example, can be interpreted as
0 X 8 + 1 X 4 + 1 X 2 + 0 X 1=6
Error Detection Codes:
Binary information, be it pulse modulated signals or digital computer input or
output, may be transmitted through some form of communication medium such as wires
or radio waves. Any external noise introduced into a physical communication medium
changes bit values from 0 to 1 or vice versa.
An error-detection code can be used to detect errors during transmission. The
detected error cannot be corrected, but its presence is indicated.
A parity bit is an extra bit included with a message to make the total number of
1’s either odd or even. Parity bit P is chosen so that the sum of all 1’s is odd (odd parity)
or it is chosen so that the sum of all 1’s is even (even parity). This parity bit can be used
to detect the single bit errors in the transmission.
Alphanumeric codes:
Many applications of digital computers require the handling of data that consist
not only of numbers but also of letters. An alphanumeric code is a binary code of a group
of elements consisting of the ten decimal digits, the 26 letters of the alphabet and a
certain number of special symbols such as $, =, (, ) etc. The need to represent more than
64 characters gave rise to seven and eight bit alphanumeric codes.
ASCII codes:
ASCII stands for American Standard Code for Information Interchange. It is a
seven bit alphanumeric code but is, for all practical purposes, an eight bit code because
an eighth bit is invariably added for parity.
EBCDIC codes:
Extended Binary Coded Decimal Interchange Code. This is also an eight bit alpha
numeric code.
Lesson 7 & Lesson 8
Simplification of Boolean Functions using Karnaugh Map
Karnaugh Maps:
1. Karnaugh maps provide an alternative technique for representing Boolean
functions.
2. The Karnaugh map comprises a box for every line in the truth table.
3. Unlike a truth table, in which the input values typically follow a standard binary
sequence (00, 01, 10, 11), the Karnaugh map's input values must be ordered such
that the values for adjacent columns vary by only a single bit, for example, 00, 01,
11, and 10. This ordering is known as a gray code, and it is a key factor in the way
in which Karnaugh maps work.
4. The Karnaugh map provides a simple and straight-forward method of minimising
boolean expressions. With the Karnaugh map Boolean expressions having up to
four and even six variables can be simplified.
5. The diagram below illustrates the correspondence between the Karnaugh map and
the truth table for the general case of a two variable problem.
The values inside the squares are copied from the output column of the truth table,
therefore there is one square in the map for every row in the truth table.
M0
m1
m3
m2
M4
m5
m7
m6
Three variable Karnaugh Map
A’B’
A’B
AB
AB’
C’D’
C’D
CD
CD’
The Karnaugh map uses the following rules for the simplification of expressions by
grouping together adjacent cells containing ones :

Groups may not include any cell containing a zero

Groups may be horizontal or vertical, but not diagonal.

Groups must contain 1, 2, 4, 8, or in general 2n cells.
That is if n = 1, a group will contain two 1's since 21 = 2.
If n = 2, a group will contain four 1's since 22 = 4.

Each group should be as large as possible.

Each cell containing a one must be in at least one group.

Groups may overlap.

Groups may wrap around the table. The leftmost cell in a row may be grouped
with the rightmost cell and the top cell in a column may be grouped with the
bottom cell.

There should be as few groups as possible, as long as this does not contradict any
of the previous rules.
Don't-care conditions
Two reasons for don't-care:



It does not matter whether the output is 0 or 1;
The corresponding combinations of inputs are impossible, therefore they never
occurs.
These are represented in the Karnaugh map using X symbol.
After covering all the 1’s the simplified expression is written by taking the common
term.
Lesson 9
Multiplexers
A digital multiplexer is a combinational circuit that selects binary
information from one to many input lines and directs it to a single output
line.
Normally there are 2n input lines and n selection lines whose bit
combination determines which input is selected.
Chip 74150 is a 16 lines to 1 line multiplexer. Connection diagram of
74150 is as follows:
Lesson 10
Demultiplexers
Demultiplexing means one into many. A demultiplexer is a logic
circuit with one input and many outputs. By applying control signals, we
can steer the input signal to one of the output lines.
So there are
o
o
o
1 input signal
n control signals
and 2n output signals
74154 is a decoder/demultiplexer.
Pin diagram for 74154
Lesson 12
Adders
Combinational circuits:
A combinational circuit consists of logic gates whose outputs at
any time are determined directly from the present combination of inputs
without regard to the previous inputs.
Sequential circuits:
Sequential circuits are one where the outputs are a function of
the inputs and the state of memory elements. The state of memory elements,
in turn is a function of previous inputs.
Adder:
-
adder is a combinational circuit.
Is used for adding binary digits.
There are two adder circuits
One is half adder and another is full adder.
Half adder performs the addition of two bits.
Full adder performs the addition of three bits(2 significant bits & a
carry).
- Two half adders can be employed to implement a full adder.
Half adder:
Half adder is a combinational circuit which performs the
addition of two bits.
Truth table:
a
B
Sum (S)
Carry (C)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Logic diagram:
Full Adder:
A full adder is a combinational circuit that forms the arithmetic
sum of three input bits. It consists of three inputs and two outputs. Two of
the input variables represent the two significant bits to be added. The third
input represents the carry from the previous lower significant position.
Truth table:
Carry
Sum
(in)
0
0
Carry
(out)
0
a
b
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Logic diagram:
Full adder can be constructed using two half adders.
Lesson 13
BCD Arithmetic
BCD Addition
BCD, or binary-coded decimal, represents the 10 decimal digits in
terms of binary numbers. It is possible to build digital hardware that
manipulates BCD directly, and such hardware could be found in early
computers and many hand-held calculators. The BCD system was chosen for
the internal number system in these machines because it is easy to convert it
to alphanumeric representations for printouts and displays. The compelling
advantages of BCD have waned over time, and these digits are supported by
more modern hardware simply to provide backward compatibility with
earlier generations of machines. In this section, we briefly examine the
approaches for constructing BCD arithmetic -elements.
For example, let's consider the addition of the two BCD digits 5 and 3:
Now consider the sum of 5 and 8:
The sum is 1101 = 13, but this result should be correctly represented as 0001
0011 in BCD notation. There is a simple way to find the correct result. We
add 6 (0110) to the digit sum if it exceeds 9. Let's examine the following
cases:
In both cases, by adding six we obtain the correct answer in BCD.
BCD adder:
A BCD adder is a circuit that adds two BCD digits in parallel
and produces a sum digit also in BCD. A BCD adder must include the
correction logic in its internal construction. To add 0110 to the binary sum,
we use a second 4 bit binary adder to produce the binary sum. When the
output carry is equal to zero, nothing is added to the binary sum. When it is
equal to one binary 0110 is added to the binary sum through another 4 bit
binary adder.
Block diagram of a BCD adder
Lesson 14
Comparator
Magnitude comparator:
A magnitude comparator is a combinational circuit that compares two
numbers, A and B, and determines their relative magnitudes.
The outcome of the comparison is specified by three binary variables that
indicate whether A>B, A=B or A<B.
Algorithm Procedure for Circuit design:
The circuit for comparing two n-bit numbers has 22n entries in the truth
table and becomes too cumbersome even with n=3. So the circuit can be designed
using algorithmic procedure. An algorithm is a procedure that specifies a finite set
of steps which, if followed, give the solution to a problem.
Designing comparator circuit:
The algorithm is a direct application of the procedure a person uses
to compare the relative magnitude of two numbers.
Consider two numbers, A and B with four digits each.
A = A 3 A2 A 1 A0
B = B3B2B1B0
1. The two pairs are equal if all pairs of significant digits are equal.
A3=B3, A2=B2, A1=B1, A0=B0
Since in binary the digits are either 1 or 0 , so the equality relation of each pair of
bits can be expressed logically with an equivalence function:
Xi = AiBi + Ai’Bi’
for i=0,1,2,3
2. To determine if A is greater than or less than B, we inspect the relative
magnitudes of pairs of significant digits starting from the most significant position.
If the two digits are equal, we compare the next lower significant pair of digits.
This comparison continues until a pair of unequal digits is reached. If the
corresponding digit of A is 1 and that of B is 0, we conclude that A>B. if the
corresponding digit of A is 0 and that of B is 1, we have that A<B.
The sequential comparison can be expressed logically by the following two
Boolean functions:
(A>B)=A3B3’+x3A2B2’+x3x2A1B1’+x3x2x1A0B0’
(A<B)= A3’B3+x3A2’B2+x3x2A1’B1+x3x2x1A0’B0
7485:
7485 is a 4 bit magnitude comparator
Lesson 15
Parity Generators/Checkers
Parity bit:
Parity bit is an additional non-information bit appended to a group of
bits to make the number of "1s" in the group of bits either an odd or even number.
Parity Bit in error detection:
A parity bit is a scheme for detecting errors during transmission of
binary information. Parity bit is included with a binary message to make the
number of 1’s either odd or even. The message, including the parity bit, is
transmitted and then checked at the receiving end for errors.
An error is detected if the checked parity does not correspond to the
one transmitted.
Parity Generator:
Parity generator is a circuit that generates the parity bit in the
transmitter.
Parity Checker:
Parity checker is a circuit that checks the parity in the receiver.
Three bit parity generator:
As an example consider a three-bit message to be transmitted with
an odd-paritybit. The truth table for odd parity generation is shown below:
x
y
z
P
0
0
0
1
0
0
1
0
0
1
0
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
0
x,y,z constitute the message and are the inputs to the circuit. The parity bit P is the
output. For odd parity, the bit P is generated so as to make the total number of
ones is odd (including P). From the truth table, we see that p=1 when the number
of ones in x,y and z is even.
At the receiver the parity is recalculated using either an exclusive-or adder or a Finite
State Machine (FSM). An implementation using XOR gates is shown below.
Lesson 16
Code Converters
Code Converter:
Code converter is a circuit that is used for converting one code to
another code thus making the two systems using different codes compatible.
Need for code converters:
The availability of a large variety of codes for the same discrete
elements of information results in the use of different codes by different digital
systems. It is sometimes necessary to use the output of one system as the input to
another. A conversion circuit must be inserted between the two systems if each
uses different codes for the same information.
BCD to Excess – 3 code:
For example consider the conversion of BCD numbers to Excess – 3
code.
Truth table for code conversion is given below:
Input (BCD)
Output(Excess 3)
A
B
C
D
w
x
y
z
0
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
Simplifying the Boolean function using K-maps we get:
w=A + BC+BD=A+B(C+D)
x=B’C+B’D+BC’D’=B’(C+D)+B(C+D)’
y=CD+C’D’=CD+(C+D)’
z=D’
Lesson 17
Encoders
Encoder:
An encoder is a combinational circuit that produces a reverse operation
from that of a decoder.
An encoder has 2n (or less) input lines and n output lines. The output
lines generate the binary code for the 2n input variables.
Octal to Binary Encoder:
The octal to binary encoder consists of eight inputs, one for each of the
eight digits, and three outputs that generate the corresponding binary number.
The truth table for Octal to binary encoder is given below:
X7
1
0
0
0
0
0
0
0
X6
0
1
0
0
0
0
0
0
X5
0
0
1
0
0
0
0
0
X4
0
0
0
1
0
0
0
0
Inputs
X3
0
0
0
0
1
0
0
0
X2
0
0
0
0
0
1
0
0
X1
0
0
0
0
0
0
1
0
X0
0
0
0
0
0
0
0
1
Outputs
A2 A1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
A0
0
1
0
1
0
1
0
1
Design Issues:
There are two ambiguities associated with the design of encoders:
1. only one input can be active at any given time. If two inputs are
active simultaneously, the output produces undefined combination.
2. an output with all zeroes can be generated when all the inputs are
zeroes or I0 is 1.
Priority Encoder:
1. Solves the ambiguities present in the encoders.
2. Multiple high inputs are allowed.
3. These encoders establish an input priority to ensure that only the
highest priority input line is encoded.
4. The operation of the priority encoder is such that if two or more
inputs are equal to 1 at the same time, then the input in the highest
numbered position will take precedence.
*********
LESSON 18
SR FLIP FLOP
Sequential Logic Circuit:
 Sequential logic is a type of logic circuit whose output depends not only on
the present input but also on the previous output of the circuit ie output of
the sequential circuit is a function of current inputs and previous output.
 Sequential logic has storage or memory elements.
 It consists of a combinational circuit to which memory elements are
connected to form a feedback path.
Synchronous / Asynchronous Sequential Circuits:
 There are two main types of sequential circuits
 Synchronous
 Asynchronous
 A Synchronous sequential circuit
 is a system whose behavior can be defined from the
knowledge of its signals at discrete instants of time.
 Synchronization is achieved by a timing device called a
master clock generator.
 The clock pulses are distributed throughout the system in
such a way that memory elements are affected only with the
arrival of the synchronization pulse.
 Synchronous sequential circuits that use clock pulses in the
inputs of memory elements are called clocked sequential
circuits.
 The memory elements used in clocked sequential circuits are
usually clocked flip flops.
 An asynchronous sequential circuit
 is a sequential circuit whose behavior depends only on the
order in which its input signals change and can be affected at
any instant of time.
 Memory elements are either latches or time delay elements.
 Difficult to design and verify or test.
 May be regarded as a combinational circuit with a feed back.
Flip-Flops:
 A flip flop is a bistable electronic circuit that has two stable states – that is
output is either 0 or +5v dc.
 the flip-flop or bistable multivibrator is a digital circuit capable of serving as a
one-bit memory.
 A flip-flop typically includes zero, one, or two input signals; a clock signal;
and an output signal.
 The major differences among various types of flip-flops are in the number of
inputs they possess and in the manner in which the inputs affect the binary
state.
 The different types of flip flops are RS flip flop, D flip flop, JK flip flop, T flip
flop.
SR flip flop using NOR gate:
To create an S-R latch, we can wire two NOR gates in such a way that the
output of one feeds back to the input of another, and vice versa, like this:
1. The first input condition in the truth table is R=0, S=0. Since a 0 at the
input of a NOR gate has no effect on its output, the flip flop simply remains
in its present state that is Q remains unchanged
2. The second input condition S=0 and R=1 forces the output of the first NOR
gate to low and hence Q is 0. Now both the inputs to the second NOR gate
are zero so the output at second NOR gate is 1.
3. Third input condition S=1 and R=0 forces the output of the second NOR
gate to low and hence Q’ is low. Both the inputs to the first NOR gate are
zero so the output at first NOR gate Q is 1.
SR Flip flop using NAND gate:
***********
Lesson 19
D flip flop and JK flip flop
Clocked RS flip flop:
The clocked RS flip flop consists of a basic NOR flip-flop and two
AND gates. The outputs of two AND gates remain at 0 as long as the clock pulse
is 0, regardless of the S & R input values. When the clock pulse goes to 1,
information from the S and R inputs is allowed to reach the basic flip flop. The set
state is reached with S=1, R=0 and CP=1. To change to the clear state inputs must
be S=0, R=1 and CP=1.
D flip flop:
- It has only one input designated as D.
- The D input goes directly to the S input, and its complement, is applied
to the R input.
- The D input is sampled during the occurrence of a clock pulse. If it is 1,
the flip flop switches to set state. If it is 0, the flip flop switches to reset
state.
- The D flip flop receives the designation from its ability to transfer data
into a flip-flop.
- It is basically an RS flip-flop with an inverter in the R input. This
reduces the number of inputs from two to one.
JK Flip Flop:
-
JK flip flop is a refinement of the RS flip flop in that the indeterminate
state of the RS type is defined in the JK type.
In a JK flip flop, J and K inputs behave like S and R to set and clear the
flip flop.
When inputs are applied to both J and K simultaneously, flip flop
switches to its complement state.
(a) Logic diagram
(b) Graphic symbol
(c) Transition table
Lesson 21 & 22
Registers
Register:
- a group of flip flops used to store a binary number is called a register.
- Can be used to accept input data from an alphanumeric keyboard and
then present this data at the input of a microprocessor chip.
- A register forms the basis for some very important arithmetic operation.
Types of Registers:
A register is used to store a binary number. There must be one flip flop for
each bit in the binary number. The flip flops must be connected in such a way that
the binary number can be entered into the register and possibly shifted out. A
group of flip flops connected to provide either or both of these functions is called a
shift register.
Shift Register:
Shift registers are a type of sequential logic circuit, mainly used for storage
of digital data. They are a group of flip-flops connected in a chain so that the
output from one flip-flop becomes the input of the next flip-flop. Most of the
registers possess no characteristic internal sequence of states. All the flip-flops are
driven by a common clock, and all are set or reset simultaneously.
The basic types of shift registers are
1. Serial In - Serial Out
2. Serial In - Parallel Out
3. Parallel In - Serial Out
4. Parallel In - Parallel Out
1. Serial In – Serial Out shift register:
A basic three-bit shift register can be constructed using three D flip-flops,
as shown below. The operation of the circuit is as follows. The register is first
cleared, forcing all four outputs to zero. The input data is then applied
sequentially to the D input of the first flip-flop on the left (FF0). During each
clock pulse, one bit is transmitted from left to right. Assume a data word to be
100. The least significant bit of the data has to be shifted through the register from
FF0 to FF2
Three D Flip-Flops are cascaded Q to D and the clocks paralleled to form a three
stage shift register above.
JK FFs cascaded Q to J, Q' to K with clocks in parallel to yield an alternate
form of the shift register above.
A serial-in/serial-out shift register has a clock input, a data input, and a data
output from the last stage. In general, the other stage outputs are not available
Otherwise, it would be a serial-in, parallel-out shift register..
The waveforms above are applicable to either one of the preceding two
versions of the serial-in, serial-out shift register. The three pairs of arrows show
that a three stage shift register temporarily stores 3-bits of data and delays it by
three clock periods from input to output.
2. Serial In Parallel Output:
For this kind of register, data bits are entered serially in the same manner as
discussed in the last section. The difference is the way in which the data bits are
taken out of the register. Once the data are stored, each bit appears on its
respective output line, and all bits are available simultaneously. The construction
of a four-bit serial in - parallel out register is shown below.
3. Parallel in Serial out shift register:
Below we take a close look at the internal details of a 3-stage parallel-in/ serial-out
shift register. A stage consists of a type D Flip-Flop for storage, and an AND-OR
selector to determine whether data will load in parallel, or shift stored data to the
right. In general, these elements will be replicated for the number of stages
required. We show three stages due to space limitations. Four, eight or sixteen bits
is normal for real parts.
Above we show the parallel load path when SHIFT/LD' is logic low. The upper
AND gates serving DA DB DC are enabled, passing data to the D inputs of type D
Flip-Flops QA QB DC respectively. At the next positive going clock edge, the data
will be clocked from D to Q of the three FFs. Three bits of data will load into QA
QB DC at the same time.
The type of parallel load just described, where the data loads on a clock pulse is
known as synchronous load because the loading of data is synchronized to the
clock. This needs to be differentiated from asynchronous load where loading is
controlled by the preset and clear pins of the Flip-Flops which does not require the
clock. Only one of these load methods is used within an individual device, the
synchronous load being more common in newer devices.
The shift path is shown above when SHIFT/LD' is logic high. The lower AND
gates of the pairs feeding the OR gate are enabled giving us a shift register
connection of SI to DA , QA to DB , QB to DC , QC to SO. Clock pulses will cause
data to be right shifted out to SO on successive pulses.
The waveforms below show both parallel loading of three bits of data and serial
shifting of this data. Parallel data at DA DB DC is converted to serial data at SO.
What we previously described with words for parallel loading and shifting is now
set down as waveforms above. As an example we present 101 to the parallel inputs
DAA DBB DCC. Next, the SHIFT/LD' goes low enabling loading of data as opposed
to shifting of data. It needs to be low a short time before and after the clock pulse
due to setup and hold requirements. It is considerably wider than it has to be.
Though, with synchronous logic it is convenient to make it wide. We could have
made the active low SHIFT/LD' almost two clocks wide, low almost a clock
before t1 and back high just before t3. The important factor is that it needs to be
low around clock time t1 to enable parallel loading of the data by the clock.
Note that at t1 the data 101 at DA DB DC is clocked from D to Q of the Flip-Flops
as shown at QA QB QC at time t1. This is the parallel loading of the data
synchronous with the clock.
4. Parallel in Parallel out register:
In this type of registers both input and output can be parallel.
Shown below is a four bit parallel in parallel out register. This type of registers are
also called as data registers.
Lesson 23 & 24
Counters
Counter:
A sequential circuit that goes through a prescribed sequence of states upon
the application of input pulses is called a counter.
Ripple Counter:
The ripple counter is one in which each flip flop is triggered by the
previous flip-flop, and thus the counter has a cumulative settling time. Counters
such as these are also called serial, or asynchronous.
A binary ripple counter can be constructed using clocked JK flip flops.
A two-bit asynchronous counter is
shown on the left. The external clock
is connected to the clock input of the
first flip-flop (FF0) only. So, FF0
changes state at the falling edge of
each clock pulse, but FF1 changes only
when triggered by the falling edge of
the Q output of FF0. Because of the
inherent propagation delay through a
flip-flop, the transition of the input
clock pulse and a transition of the Q
output of FF0 can never occur at
exactly the same time. Therefore, the
flip-flops cannot be triggered
simultaneously, producing an
asynchronous operation.
Synchronous counters
The counters shown previously have been ``asynchronous counters''; so
called because the flip flops do not all change state at the same time, but change as
a result of a previous output. The output of one flip flop is the input to the next;
the state changes consequently ``ripple through'' the flip flops, requiring a time
proportional to the length of the counter. It is possible to design synchronous
counters, using JK flip flops, where all flip flops change state at the same time;
i.e., the clock pulse is presented to each JK flip flop at the same time. This can be
easily done by noting that, for a binary counter, any given digit changes its value
(from 1 to 0 or from 0 to 1) whenever all the previous digits have a value of 1. A
count down timer can be made by connecting the Q’output to the J and K, through
the AND gates. Preset and clear could also be provided, and the counter could be
made ``programmable'' as in the previous case.
Clear
Lesson 25
SEQUENTIAL CIRCUIT DESIGN
State transition diagram:
The state transition diagram is a graph with nodes and directed arcs.
Each node represents a unique state of the circuit. A directed arc connects two
nodes representing the present state and the next state. If the circuit is in the state
at the tail of the arc, it will advance to the state at the head of the arc at the next
clock pulse.
The binary number inside each node identifies the state the node
represents. The directed lines are labeled with two binary numbers separated by a
slash (/). The input value that causes the state transition is labeled first. The
number after the slash symbol / gives the value of the output.
State Table
The state table representation of a sequential circuit consists of three
sections labeled present state, next state and output. The present state designates
the state of flip-flops before the occurrence of a clock pulse. The next state shows
the states of flip-flops after the clock pulse, and the output section lists the value of
the output variables during the present state.
Excitation table:
The excitation table tells the designer the minimum inputs that are
necessary to generate a particular next state when the current state is known.
For an S-R flip flop to make a 0 → 0 transition :
S=0, R=0
S=0, R=1
holds the 0 state or
resets the flip flop to 0
Therefore the minimum controls are S=0, R=don’t care.
Steps for the design of sequential circuits:
List of consecutive steps in sequential circuit design:
 The word description of the problem is stated.
 From the given information obtain the state diagram and state
table
 Reduce the number of states by state reduction methods.
 Assign binary values to each state if the state table contains
letters
 Determine the number of flip flops needed.
 Choose the type of flip flop to be used.
 From the state table, derive the circuit excitation and output
tables.
 Using the map or any other simplification method, derive the
circuit output function and the flip flop input functions.
 Draw the logic diagram.
**********
LESSON 26
TIMING CIRCUITS
Most digital systems require some kind of a timing waveform. In
digital systems, rectangular waveform is most desirable unlike analog systems
where sinusoidal signals are often used.
Multivibrators:
A multivibrator is an electronic circuit which is used for generating
rectangular waveforms.
There are three types multivibrators. These are:
1. Astable (or free running) multivibrator
2. Monostable (or one shot) multivibrator
3. Bistable multivibrator.
Astable Multivibrator:
 An astable multivibrator is nothing but an oscillator which generates
rectangular waveform.
 Astable Multivibrator is a two stage switching circuit in which the output of
the first stage is fed to the input of the second stage and vice versa.
 This free running multivibrator generates square wave without any external
triggering pulse.
 The circuit has two stable states and switches back and forth from one state to
another, remaining in each state for a time depending upon the discharging of
the capacitive circuit.
Monostable multivibrator:
 A monostable multivibrator has one stable state. i.e. under the steady state
condition its output is fixed and it is either low or high.
 When the circuit is triggered with an externally applied pulse it goes into
other state.
 The circuit remains in this state for a time duration depending upon the
values of the elements used in the circuits.
 It recovers back to the stable state without any external triggering pulse.
 This circuit is also referred to as a one shot multivibrator because one
trigger pulse produces only one pulse but of different width.
 It is also called as pulse stretcher because it can generate long pulse from a
narrow pulse.
Bistable multivibrator:
 A multivibrator circuit in which both the states are stable is referred to
as a bistable multivibrator or flip flop.
 This circuit makes transitions from one stable state to another only when
a triggering pulse is applied.
 These are used as memory elements.
 Flip flops are the bistable multivibrators.
Lesson - 27
SCHMITT TRIGGERS:
A Schmitt trigger is an electronic circuit that is used to detect whether a
voltage has crossed over a given reference level. It has two stable states and is
very useful as a signal conditioning device.
Given a sinusoidal waveform, a triangular wave, or any other periodic
waveform, the Schmitt trigger will produce a rectangular output that has sharp
leading and trailing edges.
Digital signals are generally considered to be one of two logic states called
by various names: On / Off, High / Low, One / Zero, 1 / 0 and Vcc / Gnd. These
are called logic signals because they are unambiguous "either / or" values.
In the real world, the voltage levels that represent logic states are not
precisely Vcc and Gnd. When these fuzzy real voltage levels are applied to digital
inverter inputs, they are compared to an internal voltage threshold and the
difference between the applied input voltage and the threshold is amplified
(multiplied) by a factor of about 100. These real voltage levels representing 1 and
0 must be in a range of values, sufficiently above and below the actual switching
threshold so that despite their fuzzyness (noise) they always generate logic 1 or 0
levels at the output of the circuit.
OPERATIONAL AMPLIFIERS:




An operational amplifier (or op-amp for short) is a differential amplifier
with an extremely high voltage gain (AV = 200,000 or more). Its name hails
from its original use in analog computer circuitry (performing mathematical
operations).
Op-amps typically have very high input impedances and fairly low output
impedances.
Sometimes op-amps are used as signal comparators, operating in full cutoff
or saturation mode depending on which input (inverting or noninverting)
has the greatest voltage. Comparators are useful in detecting "greater-than"
signal conditions (comparing one to the other).
One comparator application is called the pulse-width modulator, and is
made by comparing a sine-wave AC signal against a DC reference voltage.
As the DC reference voltage is adjusted, the square-wave output of the
comparator changes its duty cycle (positive versus negative times). Thus,
the DC reference voltage controls, or modulates the pulse width of the
output voltage.
Working Principles of Operational Amplifier:
BLOCK DIAGRAM OF AN OP AMP
An op amp has two inputs labelled – and +, and are referred to as inverting
and non-inverting inputs, respectively. The input Input1 is applied between the
inverting input terminal and ground, and input Input2 is applied between the noninverting input terminal and ground. The ground terminal is not there in this circuit
but is the ground terminal of the supplies +Vsupply and –Vsupply.
The following table shows the various input combinations and the
corresponding output for an amplifier with a voltage gain of 4:
An increasingly positive voltage on the (+) input tends to drive the output
voltage more positive, and an increasingly positive voltage on the (-) input tends to
drive the output voltage more negative. Likewise, an increasingly negative voltage
on the (+) input tends to drive the output negative as well, and an increasingly
negative voltage on the (-) input does just the opposite. Because of this
relationship between inputs and polarities, the (-) input is commonly referred to as
the inverting input and the (+) as the noninverting input.
OP AMP as comparator:
 OP AMP can be used as an analog comparator to compare two analog
signals.
 The analog signals to be compared are applied at the two inputs and
polarity of the output voltage indicates the comparison.
 The principle of the comparator is based on the equation Voutput = Av.
(Vinput(+) – Vinput(-))
 Since the gain Av of an op amp is very large any difference will be
magnified to the power supply rails rails +/-Vcc.
 If Vinput(+) is greater than Vinput(-) then the difference will be positive
and the result will be amplified to +Vcc.
 If Vinput(-) is greater, then difference is negative and the result will be
amplified to –Vcc.
 Finally if the two voltages are exactly equal, then the difference will be
zero and the output will also be zero.
Figure: Operational amplifier as a comparator
LESSON – 28
A/D & D/A CONVERTERS
Analog to digital converter:
Fundamentals of analog to digital conversion:
 The process of converting an analog voltage into an equivalent digital
signal is known as Analog to Digital conversion.
 The continuous analog signal is subdivided into a series of discrete time
segments by a device known as analog to digital converter.
 Over some period of time within each of the analog data segments, the
signal is sampled by the ADC and related circuits.
 Either simultaneously with or immediately following sampling, the ADC
utilizes microelectronic logic circuits to convert the sampled signal into a
binary number that is proportional to the signal.
 This number, in turn is passed along to either a readout device or data
storage device as a digital representation of the analog signal over the entire
duration of the segment.
The ADC Process
(a) Analog signal varies continuously with time.
(b) ADC subdivides analog signal into discrete time segments over which it samples the data (S), converts
the sample into a number (C), and waits (W) for the next conversion cycle to begin.
(c) Digital signal as transmitted to readout device or computer.
A/D converter – Simultaneous conversion:
There are a number of different methods to convert analog signal to digital.
The simplest of these methods is the simultaneous method.
1. The simultaneous method of A/D conversion is based on the use of a number
of comparator circuits.
2. The analog signal to be digitized serves as one of the inputs to each
comparator.
3. The second input is a standard reference voltage.
4. If the analog input signal exceeds the reference voltage to any comparator, that
comparator turns on.
5.This type of converter is frequently called a flash converter because it is very
fast.
A/D Conversion by Flash/Parallel Technique
2 – bit simultaneous A/D converter:
A two bit simultaneous A/D converter uses four different voltage ranges
and 3 comparators.
1. The reference voltages used are +V/4, +V/2, +3V/4. The system is then
capable of accepting an analog input voltage between 0 and +V.
2. Now if all the comparators are off, the analog input signal must be between
0 and V/4.
3. If all comparator outputs are high, the input signal must be between +3V/4
and +V
4. The three comparator outputs are then fed into a coding network to provide
2 bits which are equivalent to the input analog voltage.
5. the bits of the coding network can then be entered into a flip-flop register
for storage.
6. 2n – 1 comparators are required to convert a analog signal to a digital signal
that has n bits.
7. As the number of bits in the desired digital number increases, the number of
comparators increases very rapidly and soon becomes unmanageable.
A/D Converter – Counter method:
A higher resolution A/D converter using only one comparator could be
constructed if a variable reference voltage is used. This reference voltage could
then be applied to the comparator, and when it became equal to the input analog
voltage, the conversion would be complete.
 First the counter is reset to all 0s.
 When a convert signal is given, the counter advances through its normal
binary count sequence and the staircase waveform is generated at the output
of the ladder.
 This waveform is applied to one side of the comparator.
 The analog signal is applied to the other side.
 When the reference voltage equals (Or exceeds) the input analog voltage,
the counter stops and the conversion is complete.
 The number stored in the counter is the digital equivalent of the analog
input voltage.
 This converter is composed of a
o D/A converter
o One comparator
o A clock
o Gate and control circuitry
 Since the counter always begins at zero and counts through its normal
binary sequence, as many as 2n counts may be necessary before conversion
is complete.
 The average conversion time is 2n/2 or 2 n-1 counts.
 The counter advances one count for each cycle of the clock therefore the
clock determines the conversion rate.
CONTINUOUS A/D CONVERTER:
 This method is similar to counter method.
 For speeding up the conversion, resetting the counter each time a
conversion is made is eliminated.
 The counter would not begin at zero each time, but instead would begin
at the value of the last converted point.
 In this method up down counter is used.
 There is a need for additional logic circuitry to decide whether to count
up or down by examining the output of the comparator.
 The comparator has two outputs. When the analog voltage is more
positive than the reference voltage then the up output of the comparator
is high. When the analog voltage is more negative than the ladder
output, the down output is high.