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Department of Electrical and Electronics Engineering
Reg. No. :
MANIPAL INSTITUTE OF TECHNOLOGY, MANIPAL
(A Constituent Institute of Manipal University, Manipal)
THIRD SEMESTER B.E. DEGREE END SEMESTER EXAMINATION
(REVISED CREDIT SYSTEM)
11 December 2010
ANALOG ELECTRONIC CIRCUITS (ELE 209)
Time: 3 hours
Note
Max. Marks: 50
: Answer any FIVE full questions. Refer Table-1 for h-parameters.
1A.
1B.
1C.
Determine V0 for the circuit shown in Fig 1(A).
Define Transition time, storage time and reverse recovery time with respect to a PN junction diode
Plot the waveform by determining V0 for the circuit shown in Fig 1(C).
(02)
(03)
(05)
2A.
2B.
Determine the transistor quiescent voltages and currents of the amplifier shown in Fig 2(A). Assume VBE=0.7V.
From the fundamental derive an expression for S(ICBO), for voltage divider biasing circuit with emitter
resistance RE.
Draw the small signal h- parameter model of a Darlington pair transistor connection. Hence list out its merits
and demerits.
(03)
2C.
3A.
3B.
4A.
Design a voltage divider biasing circuit to meet the following specifications, V cc=25V, VCE=4V,
100 , S 5 and RE=100Ω. Hence draw the circuit.
IC=10mA,
For the cascaded amplifier shown in Fig 3(B) determine AV, AVS = v0/vS, and Ri using approximate h-parameter
transistor model.
An NMOS has V t
0 . 5V and
W
10 ,
L
n
C ox
200
4C.
5A.
amplifier
shown
in
the
2,
(05)
(02)
, Vt=1V, r0=40K. Determine all the quiescent
current and voltages and hence determine the output voltage when sinusoidal vi=0.8mv is applied at the input
of the amplifier.
Derive an expression for current gain, the input resistance and output resistance of a single common gate
MOSFET amplifier
the
(05)
2
The MOSFET shown in Fig. 4(B) has
In
(03)
A / v . Determine
i. The value of the VGS to operate in saturation region with a dc current IDC=100mA.
ii. Value of the VGS required to cause the device to operate 1000 resistor for very small ac, vDS signal.
4B.
(04)
circuit
Fig.
5(A),
both
the
MOSFETs
aspect ratio of MOSFET M1=
are
having
(04)
(04)
VT=0.7V,
and the drain current of
MOSFET M2 =ID2=2mA. Determine
i.
5B.
6A.
6B.
6C.
The quiescent VGS and VDS of both the MOSFETs and aspect ratio
of M2
ii.
Draw the small signal equivalent circuit and hence find small signal voltage gain from v s to vo.
iii.
Maximum sinusoidal input that can be applied before the output begin to clip.
For a transformer coupled class A power amplifier, derive an expression for efficiency and hence obtain
maximum efficiency. Also list any two disadvantages of the same.
Determine the lower and upper cut off frequency of the CE amplifier shown in Fig 6(A). Hence find the band
width. Assume the R0=50K, C1=1µF, C2=4µF, C0=1nf and CE=10µF.
Determine the output voltage V0, VCE and currents through all the resistance in the circuit shown in Fig. 6(B),
where VBE = 0.7 V
Design a 7805 variable voltage regulator to get an Output voltage range 6V to 16V. Take R1 = 1K, Iadj=4.3mA.
Draw the circuit.
Vi
2K
C =100 s
D1
(06)
(04)
(04)
(04)
(02)
2K
2K
20V
Vi
D3
10V
20ms
100K
10ms
Vi
V0
4K
Vi
6V
D2
6V
4K
t
-30V
Vo
4V
F ig 1 ( A )
F ig 1 ( C )
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Department of Electrical and Electronics Engineering
+12V
1.4K
F
22K
V0
10
F
710
C4
20K
80
10
R s = 1 .1 K C
1
C2
Q2
Q1
=45
Vi
V0
6 .2 K
3K
C3
2K
120K
470
Vs
C5
VEE= 10V
+
F ig 3 (B )
F ig 2 ( A )
+10V
+1 0 V
ID2= 2 m A
2K
1m A
3K
M2
1M
V0
C2
v0
1M
C2
M1
C1
50K
CG
C1
vi
2K
vs
F ig 4 ( B)
F ig 5 ( A )
24 V
100 k
2.2 k
C 2= 4 F
Vo
22 k
1.5 k
Vs
C E= 10
F
100
C o =1nF
C 1= 1 F
10 k
Fig 6(A)
V CE1
4 .7 K
Q1
1 .5 K
+
3K
100
Q2
2 .2 K
V i =2 2 V
5 .6 V
Vo
h-parameters
hi
hr
hf
h0
Table-1
CE
CB
1.1K
1.1K
-4
2.5×10
1
50
-51
CC
21.6 ohms
2.9×10-4
-0.98
24µmho
0.49µmho
25µmho
F i g . Q 66(B)
B
Fig.
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