Download Implementing a receiver in a fast data transfer system - A feasibility study

Examensarbete
LITH-ITN-ED-EX--03/017--SE
Implementing a receiver in
a fast data transfer system
A feasibility study
Filip Hall
Pär Håkansson
2003-10-17
Department of Science and Technology
Linköpings Universitet
SE-601 74 Norrköping, Sweden
Institutionen för teknik och naturvetenskap
Linköpings Universitet
601 74 Norrköping
LITH-ITN-ED-EX--03/017--SE
Implementing a receiver in
a fast data transfer system
A feasibility study
Examensarbete utfört i Elektronikdesign
vid Linköpings Tekniska Högskola, Campus
Norrköping
Filip Hall
Pär Håkansson
Handledare: Adriana Serban
Examinator: Shaofang Gong
Norrköping 2003-10-17
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Titel
Title
Implementing a receiver in a fast data transfer system -A feasibility study
Författare
Author
Filip Hall
Pär Håkansson
Sammanfattning
Abstract
This report is an outcome of a master degree project at Linköpings University in co-operation with Micronic Laser Systems AB.
The purpose with this master degree project was to investigate how to implement a receiver in a data transfer system. The system consists of
several data channels, where every channel consists of three parts: driver, transmission lines and receiver. The driver send low amplitude
differential signals via the transmission lines to the receiver that amplifies and converts it to a single-ended signal. The receiver has to be fast and
be able to feed an output signal with high voltage swing. It is also needed for the receivers to have low power consumption since they are close to
the load, which is sensitive to heat.
Different amplifier architectures were investigated to find a suitable circuit for the given prerequisites. In this report the advantages and
disadvantages of voltage and current feedback are discussed.
The conclusions of this work are that in a system with an amplifier as a receiver with differential transmission lines, a single operational amplifier
cannot be used. An input stage is needed to isolate the feedback net from the inputs of the operational amplifier. When fast rise time and large
output swing are wanted the best amplifier architecture is current feedback amplifiers. A current feedback amplifier in CMOS with the required
high voltages and slew rate is hard to realize without very high power consumption.
Nyckelord
Keyword
Current feedback operational amplifier, voltage feedback operational amplifier, instrumentation amplifier, receiver, transmission line, differential
to single converter
ABSTRACT
Abstract
This report is an outcome of a master degree project at Linköpings University in cooperation with Micronic Laser Systems AB.
The purpose with this master degree project was to investigate how to implement a
receiver in a data transfer system. The system consists of several data channels, where
every channel consists of three parts: driver, transmission lines and receiver. The
driver sends low amplitude differential signals via the transmission lines to the
receiver that amplifies and converts it to a single-ended signal. The receiver has to be
fast and be able to feed an output signal with high voltage swing. It is also needed for
the receiver to have low power consumption since they are close to the load, which is
sensitive to heat.
Different amplifier architectures were investigated to find a suitable circuit for the
given prerequisites. In this report the advantages and disadvantages of voltage and
current feedback are discussed.
The conclusions of this work are that in a system with an amplifier as a receiver with
differential transmission lines, a single operational amplifier cannot be used. An input
stage is needed to isolate the feedback net from the inputs of the operational amplifier.
When fast rise time and large output swing are wanted the best amplifier architecture
is current feedback amplifiers. A current feedback amplifier in CMOS with the
required high voltages and slew rate is hard to realize without very high power
consumption.
PREFACE
Preface
This is a report of a Master degree project within the program Electronic Design. The
task of the Master degree project was given by Micronic Laser Systems AB and
performed at ITN, campus Norrköping, Linköpings Universitet. The work was
financially supported by Micronic Laser Systems AB
Micronic Laser Systems is a world-leading manufacturer of high-end laser pattern
generators for production of photomasks. Since semiconductor devices become more
complex, high data rates are needed in future laser pattern generators. In this report a
model for very high-speed data transmission is investigated.
We would like to thank our supervisor Adriana Serban at ITN for support and
assistance. We are also grateful to our examiner Shaofang Gong at the University of
Linköping, Campus Norrköping for support and technical ideas. We would also like
to thank Leif Odselius at Micronic Laser Systems AB.
TABLE OF CONTENTS
Table of contents
1
INTRODUCTION...............................................................................................11
1.1
1.2
1.3
1.4
1.5
2
BACKGROUND .................................................................................................11
TASK ...............................................................................................................12
PURPOSE ..........................................................................................................12
METHOD ..........................................................................................................12
REPORT OUTLINE ............................................................................................13
SYSTEM OVERVIEW AND PROBLEM DESCRIPTION ...........................15
2.1 SYSTEM OVERVIEW..........................................................................................15
2.1.1 Input and Output Signals..............................................................................16
2.2 AMPLIFIER REQUIREMENTS .............................................................................18
2.2.1 Bandwidth.....................................................................................................18
2.2.2 Slew Rate ......................................................................................................18
2.2.3 Common Mode Rejection .............................................................................19
2.2.4 Power Consumption .....................................................................................20
2.2.5 Amplifier Specifications ...............................................................................20
3
AMPLIFIER ARCHITECTURES ....................................................................21
3.1 OPERATIONAL TRANSCONDUCTANCE AMPLIFIER ............................................21
3.2 VOLTAGE-FEEDBACK AND CURRENT-FEEDBACK OP-AMP ..............................25
3.2.1 Voltage-Feedback Vs Current-Feedback Op-amps .....................................25
3.2.2 The Current Feedback Op-amp....................................................................27
3.2.3 A CMOS Current Feedback Amplifier .........................................................29
3.3 DIFFERENTIAL AMPLIFIERS .............................................................................33
3.3.1 Op-amp in a Difference Amplifier Configuration ........................................33
3.3.2 Instrumentation Amplifiers...........................................................................34
3.3.3 Op-amp with Differential to Single Input Stage...........................................37
3.4 CHARGE TRANSFER AMPLIFIER .......................................................................40
3.4.1 NMOS CTA...................................................................................................40
3.4.2 Other CTA Architectures..............................................................................42
4
SIMULATIONS ..................................................................................................45
4.1 TRANSMISSION LINES ......................................................................................45
4.2 A BIPOLAR CURRENT FEEDBACK AMPLIFIER: THS3001.................................48
4.2.1 Difference Amplifier using THS3001 ...........................................................48
4.2.2 Difference Amplifier using THS3001 with Transmission Lines ...................52
4.2.3 Triple-Op-amp Instrumentation Amplifier ...................................................54
4.2.4 Dual-Op-amp Instrumentation Amplifier.....................................................56
4.3 AMPLIFIERS IN CMOS.....................................................................................59
4.3.1 Current Feedback Amplifier.........................................................................59
4.3.2 Differential to Single Converter...................................................................62
4.3.3 Differential Amplifier in CMOS ...................................................................63
5
DISCUSSIONS ....................................................................................................65
6
CONCLUSIONS..................................................................................................67
TABLE OF CONTENTS
7
REFERENCES ....................................................................................................69
APPENDIX A .............................................................................................................71
APPENDIX B .............................................................................................................72
APPENDIX C .............................................................................................................74
APPENDIX D .............................................................................................................76
APPENDIX E .............................................................................................................80
APPENDIX F .............................................................................................................84
TABLE OF CONTENTS
List of Figures
Fig. 2.1 A data transmission channel with transmission line and receiver ..................15
Fig. 2.2 The differential input signals to the receiver ..................................................16
Fig. 2.3 The output signal of the receiver ....................................................................17
Fig. 3.1 Schematic of a folded-cascode OTA ..............................................................22
Fig. 3.2 CFA in a non-inverting feedback configuration.............................................26
Fig. 3.3 VFA in a non-inverting feedback configuration.............................................26
Fig. 3.4 Simplified schematic of a CFA ......................................................................27
Fig. 3.5 Input stage to a VFA.......................................................................................28
Fig. 3.6 Compound transistor in CMOS ......................................................................29
Fig. 3.7 Source follower with increased transconductance..........................................30
Fig. 3.8 Voltage follower with compound transistors..................................................31
Fig. 3.9 CFA in CMOS ................................................................................................32
Fig. 3.10 Op-amp in a difference amplifier configuration...........................................33
Fig. 3.11 Triple-OP IA configuration ..........................................................................34
Fig. 3.12 Dual-OP IA configuration ............................................................................35
Fig. 3.13 Block schematic of a CCII............................................................................37
Fig. 3.14 Differential to single converter based on CCII.............................................37
Fig. 3.15 Differential amplifier using CCII and Op-amp ............................................38
Fig. 3.16 CCII in CMOS..............................................................................................39
Fig. 3.17 NMOS CTA and its three timing phases ......................................................40
Fig. 3.18 Simplified schematic of CMOS CTA...........................................................42
Fig. 4.1 Transmission line with terminations...............................................................45
Fig. 4.2 Signals at near- and far-end of the transmission, (Γ=0) .................................46
Fig. 4.3 Signals at near- and far-end of the transmission, (Γ=-0.2) .............................46
Fig. 4.4 Signals at near- and far-end of the transmission line with different lengths ..47
Fig. 4.5 THS3001 in difference amplifier configuration without transmission lines ..48
Fig. 4.6 Output and positive input signals of the difference amplifier with different
feedback resistors ..................................................................................................49
Fig. 4.7 Zoomed version of Fig. 4.6 ............................................................................49
Fig. 4.8 Full swing power consumption of the difference amplifier ...........................50
Fig. 4.9 Steady state power consumption of the difference amplifier .........................50
Fig. 4.10 Output signal of the difference amplifier with different load resistances ....51
Fig. 4.11 Output signal of the difference amplifier with different capacitive loads ....51
Fig. 4.12 Difference amplifier in the data transmission channel .................................52
Fig. 4.13 The full swing output signal of the difference amplifier in the data
transmission channel .............................................................................................52
Fig. 4.14 The current flowing trough Rg1 (dashed line) and Rg2 in the difference
amplifier in the data transmission channel............................................................53
Fig. 4.15 The input voltages to the difference amplifier in the data transmission
channel ..................................................................................................................53
Fig. 4.16 Triple-Op-amp IA using THS3001...............................................................54
Fig. 4.17 Full swing output voltage of the triple-Op-amp IA ......................................54
Fig. 4.18 The power consumption the triple-Op-amp at full swing.............................55
Fig. 4.19 The steady state power consumption of the triple-Op-amp IA ....................55
Fig. 4.20 Dual-Op-amp IA using THS3001.................................................................56
Fig. 4.21 Input and output signals of the dual-Op-amp IA..........................................56
Fig. 4.22 The input delay between the inputs of Op2 in the dual-Op-amp IA .............57
Fig. 4.23 The CMRR versus the frequency of the dual-Op-amp IA............................57
Fig. 4.24 The dynamic power consumption of the dual-Op-amp IA...........................58
Fig. 4.25 The steady state power consumption of the dual-Op-amp IA ......................58
Fig. 4.26 The CMOS CFA in a non-inverting configuration.......................................59
Fig. 4.27 The input and output voltage of the CMOS CFA.........................................60
Fig. 4.28 The steady state power consumption of the CMOS CFA ............................60
Fig. 4.29 The dynamic power consumption of the CMOS CFA at full swing ............61
Fig. 4.30 A differential to single converter based on CCII..........................................62
Fig. 4.31 The differential input and the single-ended output signals of the differential
to single converter .................................................................................................62
Fig. 4.32 Differential amplifier with CCII and CFA ...................................................63
Fig. 4.33 The output signal and the differential input signals of the differential
amplifier ................................................................................................................63
ABBREVIATION
Abbreviation
ASIC
Application Specific Integrated Circuits
BJT
Bipolar Junction Transistor
BiCMOS
Bipolar CMOS
CCII
Second generation Current Conveyor
CFA
Current Feedback Amplifier
CM
Common Mode
CMOS
Complementary MOS
CMRR
Common Mode Rejection Ratio
CTA
Charge Transfer Amplifier
DAC
Digital to Analog Converter
FC-OTA
Folded Cascode Operational Transconductance Amplifier
IA
Instrumentation Amplifier
IC
Integrated Circuit
KVL
Kirschoff´s Voltage Law
KCL
Kirschoff´s Current Law
MCM
Multi Chip Module
MOS
Metal-oxide Semiconductor
NMOS
N-channel MOS
Op-amp
Operational Amplifier
OTA
Operational Transconductance Amplifier
PMOS
P-channel MOS
RF
Radio Frequency
SOC
System On Chip
SR
Slew Rate
VFA
Voltage Feedback Amplifier
INTRODUCTION
1 Introduction
1.1 Background
In data transmission systems where large amounts of data are transmitted at high rate,
fast and accurate electronic systems are needed. High rate of data flow raises demands
not only on electrical circuits but also on the transmission systems. To overcome
limitations of electrical circuits new components are used with, e.g., high-speed, high
accuracy and low power consumption. State-of-the-art circuits can be realized by
using new IC technologies as well as new circuit techniques.
Mainstream IC technologies continue to be CMOS and BiCMOS because of their low
cost and high level of integration and low power dissipation. Another advantage is the
possibility for digital and analog circuits to coexist on the same chip, i.e., mixed
signal design. These advantages motivate the extensive work of developing highspeed CMOS designs and new circuit techniques, despite many difficulties and
limitations designers are confronted with.
To push the frequency towards RF-limits implies another set of problems, i.e., how to
model and simulate the system or circuit interconnects using the transmission line
concept and how to simulate the system including the packaging model.
Micronic Laser Systems is a world-leading manufacturer of high-end laser pattern
generators for production of photomasks. Since semiconductor devices become more
complex, high data rates are needed in future laser pattern generators. In this report a
model for very high speed data transmission is investigated. The task of the work was
given by Micronic Laser Systems AB and performed at ITN, campus Norrköping,
Linköpings Universitet. This work is financially supported by Micronic Laser
Systems AB.
11
INTRODUCTION
1.2 Task
The task of this master degree project is to make a study of how to design and use an
amplifier as a receiver in a data transfer system. The high speed data transmission
system investigated is proposed by Micronics Laser Systems AB. The transmission
system consists of several channels, where every channel can be divided into three
parts: driver, transmission lines and receiver. The driver sends a signal via the
transmission lines to the receiver that feeds the load with an amplified signal. The
receiver has to be fast and be able to feed the load with a high voltage swing. It is also
required to use a receiver with low power consumption.
The task is to present a study containing solutions both with commercial amplifiers
and designs in CMOS. Despite the main task to design an amplifier with the required
driving capabilities it should also be compatible with the transmission system. Thus,
other design problems must also be dealt with.
1.3 Purpose
The purpose of this work is to present the possibilities and limitations of using
amplifiers in a very high speed transmission system. The main purpose is not to
achieve a final solution of the receiver problem but to point out different methods to
solve it. The master degree project shall also present details to consider when
investigating solutions for similar problems.
1.4 Method
Parts of this project have been contributed to study available amplifier architectures.
Different architectures have been evaluated to find an amplifier to meet our
requirements. The amplifiers simulated can be divided into two groups, designs in
CMOS and analyzes of commercial amplifiers. The CMOS schematics were designed
and simulated in a 0.6µm process, XC06 from XFAB Semiconductor Foundries AG.
Medium-voltage transistors from the XC06 process were used in the simulations. In
terms of commercial amplifiers THS3001 from Texas Instrument Inc. was found to be
the fastest operational amplifier on the market, so THS3001 was used in this project.
Our simulations were done in Hspice and the results viewed in Mentor Graphics
Awaves. The schematics were done in Mentor Graphics’ Led.
12
INTRODUCTION
1.5 Report Outline
This chapter consists of a background of the work. The task, purpose and method are
also presented here. Chapter 2 contains a more detailed presentation of the task and its
difficulties. First, one data channel is introduced to give a general picture of the task,
and second the requirements of the receiver are presented. In Chapter 3 theory of the
amplifier architectures investigated is introduced. This chapter also contains
descriptions of the feasibility of using various amplifiers in the data transmission
channel. In chapter 4 simulations of different amplifier circuits from chapter 3 are
presented. Simulations on both amplifiers alone and amplifiers as receivers in the data
channel are shown. The results from chapter 3 and 4 are discussed in chapter 5.
Chapter 6 contains the conclusions of the discussion in chapter 5. The best solution
found and a suggestion for further work is also presented here. Appendixes are
implemented at the end of the report to enhance understanding of the technical parts.
13
14
SYSTEM OVERVIEW AND PROBLEM DESCRIPTION
2 System Overview and Problem Description
In a high speed data transmission system, cross talk, signal skew and switching noise
may cause problems to signal integrity. To overcome these problems it is known that
differential data transmission provides less cross talk, less signal skew and less
switching noise than single-ended data transmission techniques [1].
As a starting point for our study, a low-swing, differential analog data transmission
technique with an amplifier array close to the load has been proposed [1]. The data
transmission technique has high demands on the amplifier array in terms of speed and
power consumption.
2.1 System overview
A block schematic of one data transmission channel with differential driver, near-end
terminations, transmission lines, far-end terminations and amplifier is shown in Fig.
2.1, where Vdiff is the differential input signal, Vcm is the common mode signal, Rterm
are the terminating resistors and Vb is the termination voltage. Because of demands on
signal rise time, bandwidth and cable length, it has been concluded that transmission
lines with controlled impedance must be used in the system [1]. Hence, the impedance
of the cable, connector and line driver must be matched. The low-swing differential
data transmission channel requires an amplifier close to the load to amplify and
convert the differential signal to a single-ended signal.
Vb
RTerm
Line driver
Transmission Line
Amplifier
Vout
Vdiff
Vcm
Cload
RTerm
Vb
Fig. 2.1 A data transmission channel with transmission line and receiver
15
SYSTEM OVERVIEW AND PROBLEM DESCRIPTION
2.1.1 Input and Output Signals
The differential analog input signal of the amplifier is shown in Fig. 2.2. The voltage
at the center of differential signals is called the common-mode (CM) level The CM
voltage at the input is 0.25V. Vin+ and Vin- have a voltage swing of 0.5V and the
differential signal at the input is equal to Vindif=Vin+-Vin-. The differential input signal
ranges from –0.5 to 0.5V and thus the peak-to-peak swing of the input voltage is 1V.
Vin+,Vin(V)
0.5
Vin+
CM level of the input signal
Vin-t
Fig. 2.2 The differential input signals to the receiver
For this study it is supposed that the input signal comes from a 10-bit digital-toanalog converter (DAC) with a sampling frequency of 40MHz. Since the input signal
consists of 10 bits there are 210 =1024 discrete values for the amplifier to distinguish.
The voltage magnitude of one step at the input is
Vin , step =
Vinpp
2
10
=
1
≈ 1mV
1024
(eq. 2.1)
where Vin,step is the smallest step of the input voltage. Since the sampling frequency of
the DAC is 40MHz, the input signal holds a constant value for 1/40MHz = 25ns.
16
SYSTEM OVERVIEW AND PROBLEM DESCRIPTION
The maximum magnitude of the output signal is 12V. Since the input peak-to-peak
voltage is 1.0V the amplifier needs a gain of 12. The common mode of the output
signal is 6V, Fig. 2.3 shows the output voltage. The smallest output voltage amplitude
step at the amplifier is
Vout , step =
Voutpp
2
10
=
12
≈ 12mV
1024
(eq. 2.2)
where Vout,pp is the output peak-to-peak voltage swing.
Vout
(V)
12
Vo
CM level of the output signal
6
t
Fig. 2.3 The output signal of the receiver
The rise/fall time of a signal is usually defined as the time taken to go from 10% to
90% of the final value. The sampling period is 25ns and the rise and fall time must be
less than 5ns [1]. The slew rate (SR) needed for a 5ns rise time and a 12V output
swing is given by
SR =
dV
9.6
=
= 1.9 kV µs
dt 5 ⋅ 10 −9
17
(eq.2.3)
SYSTEM OVERVIEW AND PROBLEM DESCRIPTION
2.2 Amplifier Requirements
As previously stated the main objective of this work is to study the amplifier used as a
receiver in the system. The most critical requirements of the amplifier are the broad
bandwidth, high slew rate and low power consumption.
2.2.1 Bandwidth
The pulse rise time for a circuit with single-pole transfer function is related to the
bandwidth according to
tR =
0.35
f −3dB
(eq. 2.4)
where tR is the rise time and f-3dB is the frequency where the system gain has
decreased with 3 dB (Appendix A). For circuits with multiple-pole transfer functions
the rise time can often be estimated with eq. 2.4 because the dominant pole normally
determines the -3dB frequency. The information given by the rise time might not be
sufficient because problems may arise after the signal reached its peak. Circuits with a
transfer function containing complex poles can generate a high frequency peak in the
frequency response that makes the pulse response to exhibit overshoots and damped
sinusoidal oscillation. Thus, it is important to not only look at the rise time but also
the settling time to get the information of the maximum speed of a circuit.
In eq. 2.4 it is assumed that the signals are small i.e., the amplifier acts in the linear
area. If the input pulse is large enough to cause nonlinear operation the pulse response
may get a different appearance than predicted by a small signal analysis.
The amplifier needed in the data channel has a rise time of 5ns, which gives a
minimum -3dB frequency of 70 MHz when using eq. 2.4.
2.2.2 Slew Rate
Since the rise time in eq. 2.4 is only applicable for small signals other methods are
used to determine the large signal bandwidth. For large output signals, the amplitudes
can be close to the power supply, the operation speed is limited by the ability of the
amplifier to provide sufficient current to charge the capacitive load. The rate of
voltage change when the load is charged at its maximum rate is called the slew rate
and is given by
SR =
I
dV
= out
dt C load
where Iout is the output current and Cload is the capacitive load.
18
(eq. 2.5)
SYSTEM OVERVIEW AND PROBLEM DESCRIPTION
The rise time for an amplifier at a slew rate limited operation is given by
tR =
0.8H
SR
(eq. 2.6)
where H is the height of a voltage step and 0.8 originates from the definition of the
rise time (10 to 90%).
From eq. 2.3 the slew rate of the amplifier must be 1.9kV/µs and the load is modeled
as a capacitor of 10pF. Putting these values into eq. 2.5
I out = SR ⋅ C load = 1.9 ⋅ 10 9 ⋅ 10 ⋅ 10 −12 = 19 ⋅ 10 −3 = 19mA
(eq. 2.7)
Thus, we need an output current equal to 19mA during 5ns to have the desired slew
rate.
2.2.3 Common Mode Rejection
The common mode voltage is defined as the average input voltage, i.e., (vin++vin-)/2.
Since the input signals are differential the common mode voltage is always supposed
to be the same. Variation in the common mode voltage can arise due to noise and it is
thus important for the amplifier to suppress any such variation since it should not
affect the output signal.
The common mode rejection ratio (CMRR) is given by
⎛A
CMRR = 20 log⎜⎜ DM
⎝ ACM
⎞
⎟⎟
⎠
(eq. 2.8)
where ADM is the differential mode gain and ACM is the common mode gain. Assume
a common mode rejection of 60dB,
ADM
12
= 1000 ⇒ ACM =
= 12 ⋅ 10 −3
ACM
1000
(eq. 2.9)
If we want a common mode noise to be less than 10% of the smallest signal (1.2mV)
at the output the maximum common mode signal at the input is
Vin ,CM max =
Vout ,max
ACM
1.2 ⋅ 10 −3
=
= 0.1V
12 ⋅ 10 −3
(eq. 2.10)
With a CMRR of 60dB we can allow a common mode noise of 0.1V without getting a
distortion larger than 10% of the minimum output signal.
19
SYSTEM OVERVIEW AND PROBLEM DESCRIPTION
2.2.4 Power Consumption
The current in an amplifier flows mainly through the output and supply pins. The
power dissipated in the amplifier can be divided into two parts, internal and external
power dissipations. The internal power consumption arises from transistor biasing.
The external power consumption is made up of the current flowing out from the
circuit, i.e., the output current.
It was mentioned earlier that a great number of amplifiers will be used in the entire
system on a finite area. Many amplifiers active on a small area lead to a high heat
radiation. In this project the area around the amplifiers is sensitive to heat and it is
thus important that the amplifiers have as low power consumption as possible. In fact,
low power consumption is one of the key characteristics of the amplifiers
2.2.5 Amplifier Specifications
A short summery of the amplifier specification is listed below.
•
•
•
•
•
•
•
•
•
•
Differential input, Vin,diff =0-1V, Vin,cm=0.25V
Single-ended output, Vout=0-12V
Gain(closed loop) 12 times
Voltage resolution 12mV at the output
40 Msamples/s
Rise time <5ns
Bandwidth 70MHz
Worst case slew rate 1.9 kV/µs
Cload=10pF
Low power consumption
20
AMPLIFIER ARCHITECTURES
3 Amplifier Architectures
In this chapter theory of the investigated amplifier architectures is presented. Also
presented are the advantages and disadvantages of the different architectures and the
feasibly to use them in the transmission system. Architectures investigated in this
work are current feedback, voltage feedback and charge transfer amplifiers. Theory
about differential amplifiers is also presented.
3.1 Operational Transconductance Amplifier
Today a lot of high-speed Op-amps realized in CMOS are designed to drive purely
capacitive loads. Since the system described in chapter 2 has a purely capacitive load
it is possible to design faster amplifiers with higher output swing than those designed
for driving resistive loads. The high speed is obtained by only having one highimpedance node, i.e., the output node, and all internal nodes have low-impedance.
Examples of amplifiers using these features are the folded-cascode amplifier and the
current mirror amplifier [2]. These amplifiers are often referred to as Operational
Transconductance Amplifiers (OTAs).
The OTA is basically a conventional Op-amp without an output buffer. An op-amp
designed to drive capacitive loads does not need a buffer to obtain low output
impedance and hence can the OTA be useful.
21
AMPLIFIER ARCHITECTURES
The circuit in Fig. 3.1 is referred to as a Folded-Cascode OTA (FC-OTA) [2]. It is
called folded-cascode since the differential input pair (appendix B) is folded down
from the active load (Mp0-Mp3). The basic idea with folded-cascode is to use
transistors of opposite type in the active load and in the differential input pair. The
opposite transistor type arrangement makes it possible for the output to be taken at the
same bias-voltage levels as the input signals [2]. The only high impedance node in
Fig. 3.1 is the output node. The open loop gain of the amplifier is determined by the
product of the input transconductance and the output impedance. Since the output
impedance is high due to the cascode technique a high gain is obtained. The
differential to single conversion in the circuit is realized with a wide swing current
mirror (Mn4-Mn7).
VDD
Vbias1
Mp3
Vbias2
Vinp
Mp2
Mp0
Mp1
Mn0
Vout
Mn1
Vinn
Vbias3
Vbias4
Mn2
Mn6
Mn4
Mn3
Mn7
Mn5
VSS
Fig. 3.1 Schematic of a folded-cascode OTA
22
AMPLIFIER ARCHITECTURES
SMALL SIGNAL ANALYSIS
If the high-frequency poles and zeros are ignored the small signal transfer function of
the FC-OTA is given by
Av =
Vout ( s)
= g m ,in Z L ( s )
Vin ( s)
(eq. 3.1)
where gm,in is the transconductance of each transistor in the differential input pair and
ZL(s) is the impedance at the output node [2]. ZL(s) consists of the output load
capacitance, the impedance of the stabilizing network and the output impedance of the
FC-OTA. When the amplifier is stabilized by the output capacitance, the small signal
transfer function is
Av =
g m,in rout
1 + srout C L
(eq. 3.2)
where rout is the output impedance. When operated at high frequencies the load
capacitance dominates and the transfer function is thus
Av =
g m,in
sC L
(eq. 3.3)
and the unity-gain frequency is then
ωt =
g m ,in
CL
(eq. 3.4)
To maximize the unity-gain frequency, the transconductance of the input transistors
must be maximized. The transconductance of a transistor is raised by increasing its
width or drain-source current or both. Eq. 3.4 shows the relationship between the
unity gain frequency and the capacitive load.
23
AMPLIFIER ARCHITECTURES
SLEW RATE
The slew rate available in a FC-OTA is derived from internal currents of the
amplifier. When a large input signal is applied to the input Mn1 is turned on hard and
Mn0 is turned off. This means that all the biasing current in the transistor Mp1 is
flowing through Mp3. Since Mn0 is turned off all the current from the current source
(Mn2 and Mn3) is flowing through Mn1. The current flowing in the current source must
be larger than IDp0. Therefore, the current available for charging CL is IDp2, which is
half of the total biasing current. A similar reasoning is valid for discharging the load.
Hence, the maximum available slew rate in the FC-OTA in Fig. 3.1 is given by
SR =
I Mp 2
CL
=
I tot
2 ⋅ CL
(eq. 3.5)
If we were supposed to design a FC-OTA for the slew rate of 1.9kV/µs, the current
flowing in MTp2 and MTp4 has to be
I Mp 0 = I Mp 2 = SR ⋅ C L = 1.9 ⋅ 10 9 ⋅ 10 −11 = 19mA
If the supply voltage is assumed to be 14V and the power dissipated in the biasing
network is ignored, the power dissipated is
P diss = (Vdd − Vss ) ⋅ ( I Tp 2 + I Tp 4 ) = 14 * 0.038 = 538mW
The slew rate of a current mirror amplifier can be larger than a FC-OTA for a given
biasing current. However, it is still the biasing current that charges/discharges the
load.
To increase the driving capabilities of the OTA an output buffer can be added. An
OTA with output buffer is a conventional voltage feedback Op-amp [3].
24
AMPLIFIER ARCHITECTURES
3.2 Voltage-Feedback and Current-Feedback Op-amp
In the previous chapter it was shown that the slew rate of an OTA is derived from the
internal currents (i.e., biasing currents) and the load capacitance. The large slew rate
and capacitive load given in chapter 2 (i.e., 1.9kV/µs and 10pF) leads to high power
consumption of the OTA. Therefore, conventional Op-amps are investigated in the
following chapter.
When high slew-rate, large-signal and wide bandwidth is of interest, as in our project,
the current-feedback operational amplifier (CFA) is the first choice to analyze. CFAs
have gained popularity during the last years since modern process technologies make
it possible to make use of the advantages of the CFA. Large signal CFAs are usually
designed in bipolar technologies due to the availability of high-speed complementary
bipolar transistors. Slew rates of CFAs can normally reach 500V/µs to 2500V/µs
compared to maximum slew rates of about 100V/µs for voltage feedback operational
amplifier (VFA) with comparable quiescent currents.
3.2.1 Voltage-Feedback Vs Current-Feedback Op-amps
Main differences between CFAs and VFAs as well as a presentation of a classical
CFA architecture and its basic function are presented below.
ƒ
The slew rate of VFAs is inherent limited by the fixed tail current in the input
stage and the compensation capacitance.
ƒ
The large slew rate of CFAs is obtained as a result of using current as a
feedback error signal. In other words, the input stage current is not fixed.
ƒ
In closed-loop configuration the gain-bandwidth product of VFA is constant,
i.e., the closed-loop gain is dependent on the bandwidth.
ƒ
In CFA the product of bandwidth and gain is not constant.
ƒ
A VFA has high impedance at both the non-inverting and inverting inputs.
ƒ
CFA inputs are asymmetrical, the non-inverting input has high impedance but
the inverting input has low impedance.
25
AMPLIFIER ARCHITECTURES
The closed loop gain of the CFA in Fig. 3.2 is given in eq. 3.6 and is very similar to
the closed loop gain of the VFA in Fig. 3.3 (eq.3.8). However, eq. 3.7 has some
interesting features compared to the voltage feedback gain bandwidth product (eq.
3.9). The VFA closed loop bandwidth decreases with increased loop gain. In contrast,
the closed loop bandwidth of the CFA is independent of the closed loop gain.
Moreover, eq. 3.7 implies that the CFA requires specific values of Rf and Cc
(compensating capacitor) to be properly compensated. To increase the stability of the
amplifier the value of the Rf or Cc can be increased. A derivation of the closed loop
gain and bandwidth is given in appendix C.
V in
Ierr
A=
Vo
z t I err
Rf
Vout
= 1+
Vin
Rg
eq .(3.6)
1
2πR f C c
eq.(3.7)
BW =
Rg
Rf
Fig. 3.2 CFA in a non-inverting feedback configuration
V in
V err
aV err
Vo
A=
Vout
R
=1+ 2
Vin
R1
GBP = A ⋅ BW = f t
R2
R1
Fig. 3.3 VFA in a non-inverting feedback configuration
26
eq .(3.8)
eq. (3.9)
AMPLIFIER ARCHITECTURES
3.2.2 The Current Feedback Op-amp
The CFA usually consists of an input stage, current mirrors, a high impedance node
and an output buffer. Fig. 3.4 shows a simplified schematic of a CFA in a noninverting feedback configuration [2].
The input stage (Q1-4) forces the inverting and non-inverting inputs to have the same
potential. If there is a difference in potential between the inverting and non-inverting
input a current start flowing out from or into the inverting input to counteract the
voltage difference. This current (If) is the difference between the collector currents of
Q2 and Q4 in Fig. 3.4. These collector currents are mirrored, using current mirrors
(CM1 and CM2), to the high impedance node denoted as Cc and Ro in Fig. 3.4. This
results in a high voltage swing at the high impedance node. Hence, the actual
amplification is done at this node. The last stage is a unity gain buffer that buffers the
voltage at the high impedance node to the output.
Ir
CM1
Q1
Q2
Buffer
Vin-
Vin+
Cc
Q3
Q4
Ro
x1
If
CM2
IR
Fig. 3.4 Simplified schematic of a CFA
27
Rf
Rg
AMPLIFIER ARCHITECTURES
In Fig. 3.4 a class-AB input stage is used to force the inverting input to follow the
non-inverting input. In contrast, Fig. 3.5 shows an input stage that is typical for a
conventional VFA. This type of configuration is called a differential pair. The
differential pair is in many ways different from the input stage in a CFA. Both of the
inputs in a VFA (differential pair) have high impedance, resulting in essentially no
current flowing into the nodes.
Q1
Q2
Vin+
Vbias
Vin-
Q3
Fig. 3.5 Input stage to a VFA
The slew rate at the high impedance node in the VFA is usually limited by the current
flowing in the biasing transistor (Q3 in Fig. 3.5). However, the slew rate of the CFA is
not limited by the biasing current since the current flowing into or out from the
inverting input also affects the slew rate. The current flowing through the inverting
input helps charging/discharging the high impedance node. This gives the CFA a
much higher slew rate compared to the VFA with the same quiescent currents and
bandwidth.
In applications the CFA can be configured similar to the VFA but with one exception,
a capacitance can never be connected between the output and the input of the
amplifier. The open loop inverting input with low impedance causes much concern
among designers and is often viewed as making a CFA unsuitable as a difference
amplifier. However, a CFA can be used as a difference amplifier with the same
configuration as the VFA [4].
The VFA has better DC-performance characteristics than the CFA. The VFA also has
better CMRR. Even though a VFA has better DC-characteristics, a CFA is needed in
this project due to the need of wide bandwidth, high slew rate and low power
consumption.
28
AMPLIFIER ARCHITECTURES
3.2.3 A CMOS Current Feedback Amplifier
A disadvantage when using CMOS transistors in analog amplifiers is their relative
low transconductance (gm) compared to bipolar transistors. The gm of a MOS
transistor in the saturated region is proportional to √ID, eq. 3.10, whereas it is
proportional to IC for a BJT. Increasing ID to get higher gm also increases the power
dissipation. To double gm of a MOS transistor the drain current has be increased four
times. Another way to get higher gm is to increase the width of the transistor, but large
transistors generates more parasitic capacitance and the frequency response gets
reduced (appendix D).
g m = 2 µ n C ox
W
ID
L
(eq 3.10)
A method used to generate higher gm, without increasing the current or dimensions, is
to combine two or more transistors. A circuit designed for this purpose is referred to
as a compound transistor.
COMPOUND TRANSISTOR
A compound circuit with increased transconductance is shown in Fig. 3.6 [5]. The
circuit consists of two source followers and one current mirror. One of the source
followers is made with an NMOS-transistor and the other with a PMOS-transistor.
The current mirror feeds Mn1 with a bias current. The bias current is fed back with a
ratio of α to 1.
The circuit is equivalent to a PMOS transistor where the compound gate is the gate of
Mn1 and the source of Mp1 is the compound source. The compound drain terminal can
be achieved by duplicating the drain current in Mp1 using an extra output from the
current mirror. The compound transistor transconductance is calculated through a
small signal analysis. The small signal analysis gives a Gm of (gmn1gmp1)/(gmn1- αgmp1)
from the gate of Mn1 to the source of Mp1. The current mirror transfer ratio should be
set to α=gmn1/gmp1 for a maximized transconductance.
Ibias
gate
source
Mn1
Mp1
α:1
Fig. 3.6 Compound transistor in CMOS
29
AMPLIFIER ARCHITECTURES
SOURCE FOLLOWER WITH INCREASED TRANSCONDUCTANCE
There are two drawbacks with the simple source follower when it is used as an output
buffer. The first is that there is a DC level shift between the input and output voltage,
Vout=Vin-Vgs. The second is that it has high output impedance. The output impedance
of a source follower is inversely proportional to the transconductance, eq. 3.11. A
method to achieve lower output impedance is thus to increase the transistor
transconductance which can be realized by using compound transistors.
1
gm
Z out =
(eq. 3.11)
A source follower implemented with an n- and p-type current mirror is shown in Fig.
3.7 [5]. The source follower is a realization of the p-compound device in Fig. 3.6.
Since the compound circuit is a source follower it is meant to have equal output and
input voltage. To achieve a linear transfer function the gate-source voltage of
transistor Mn1 and Mp1 must be the same. The n- and p-type current mirror made by
Mn2 and Mp2 acts as a gate-source voltage matching circuit for Mn1 and Mp1.
Assuming that Mp1 and Mp2 have the same size and equal drain current the gate source
voltage has to be identical. The same reasoning is valid for Mn1 and Mn2. Since Mn2
and Mp2 have the same gate source voltages, Mn1 and Mp1 have to have identical gate
source voltages. The matching circuit removes the gate-source voltage differences
between Mn1 and Mp1, thus the output-offset voltage problem removed and the output
voltage follows the input voltage. Even though it is supposed to be matched, inputoutput matching problems can arise due to body effects in the transistors. Using a
twin-well process can reduce the body effect and generate better DC-accuracy [5].
Ibias
gate
source
Mn1
Mp1
Mn2
Mp2
Fig. 3.7 Source follower with increased transconductance
30
AMPLIFIER ARCHITECTURES
BUFFER WITH COMPOUND TRANSISTORS
An output voltage buffer is often used in Op-amp to isolate the load from the high
impedance node. In high-speed amplifiers it is important to have a fast voltage buffer
that can feed large output currents. A voltage follower used in high-speed Op-amps
should have high input impedance, very low input capacitance, very low output
impedance, gain near unity, high linearity, wide frequency response and the ability to
drive large capacitive loads without oscillation. The voltage follower in Fig. 3.8 is
designed to meet these requirements better than the conventional voltage follower [5].
vdd1
Mn4
Mp4
Mn3
Mp3
vdd2
Vin+
Vout
vss2
Mn1
Mp1
Mn2
Mp2
vss1
Fig. 3.8 Voltage follower with compound transistors
The voltage follower in Fig. 3.8 is implemented with two compound transistors, one
p-type and one n-type. The p-type is realized with Mn1, Mp1 and a current mirror
implement by Mn2 and Mp2. The n-type is realized with Mn3, Mp3 and a current mirror
implement by Mn4 and Mp4. The compound transistors are connected in a push-pull
configuration. Since the compound transistors have high gm the output impedance is
low.
31
AMPLIFIER ARCHITECTURES
CURRENT FEEDBACK OP-AMP IMPLEMENTATION
A CFA designed for high frequency is shown in Fig. 3.9 [5]. The CFA consists of two
voltage followers of the technique presented above. The voltage followers are used as
input and output buffers. The circuit in Fig. 3.9 has the typical current feedback
features, a high impedance non-inverting input, a low impedance inverting input, a
high impedance gain node and a unity voltage gain output buffer.
The input stage (Mn1-Mn4 and Mp1-Mp4) forces the inverting and non-inverting inputs
to have the same potential. When the amplifier is in a non-inverting feedback
configuration (Fig. 3.2) and there is a difference in potential between the inverting and
non-inverting input a current start flowing out from or into the inverting input to
counteract the voltage difference. This current is the difference between the source
currents of Mn5 and Mp3. These source currents are mirrored, using Mn5 and Mp5, to
the high impedance node (H). The last stage is a unity gain buffer that buffers the
voltage at the high impedance node to the output.
Vdd1
Mn4
Mn10
Mp5
Mp4
Mp10
Mn3
Mn9
Mp6
Mp3
Vin+
Vss2
Vdd2
Vin-
Vbias1
Mp9
Vss3
(H)
Vdd3
CC
Mn1
Mn7
Mn6
Vbias2
Mp1
Mn2
Vout
Mn5
Mp7
Mn8
Mp2
Mp8
Vss1
Fig. 3.9 CFA in CMOS
32
AMPLIFIER ARCHITECTURES
3.3 Differential Amplifiers
Differential amplifiers can be realized using one or more Op-amps in different
configurations. A differential-to-single input stage together with an Op-amp can also
be used as a differential amplifier.
3.3.1 Op-amp in a Difference Amplifier Configuration
An Op-amp in a difference amplifier configuration is shown in Fig. 3.10. To have true
differential amplification, eq. 3.12 must be satisfied.
Rf1
R g1
=
Rf 2
(eq. 3.12)
Rg 2
When eq. 3.12 is true, the amplified voltage is given by
Vamp=
Rf1
R g1
(eq. 3.13)
(Vdiff )
The output voltage is given by Vo=Vamp+Vref
Rf1
Rg1
_
Vo
RL
Vdiff
+
Vcm
CL
Rg2
Rf2
Vref
Fig. 3.10 Op-amp in a difference amplifier configuration.
33
AMPLIFIER ARCHITECTURES
3.3.2 Instrumentation Amplifiers
The classic difference amplifier configuration can be unsuitable in some applications.
A configuration involving more than one Op-amp can be used to achieve a better
differential amplifier and is referred to as an instrumentation amplifier (IA). An IA
should meet following specifications: very high common-mode and differential-mode
input impedance, low output impedance, accurate and stable gain, and extremely high
CMRR [6]. IAs are often used in test and measurement instruments and hence their
name.
TRIPLE-OP-AMP IA
The IA in Fig. 3.11 consists of two stages, the input or first and the output or second
stage [6]. The first stage consists of two Op-amps, Op1 and Op2. The second stage
consists of Op3 in a difference amplifier configuration.
Ri
Vin1
Rf
Op1
R3
Rg
Vout
Op3
R3
Vin2
Op2
Ri
Rf
Vref
Fig. 3.11 Triple-OP IA configuration
The voltage across Rg is given by the difference of the input voltages, vin1-vin2, since
the inverting and the non-inverting input of an Op-amp have the same voltage. The
same current flows through R3 and Rg since no current flows through the inputs of
Op-amps. The output voltage of the first stage is given by
⎛ 2R ⎞
vout1 − vout 2 = ⎜1 + 3 ⎟(vin1 − vin 2 )
⎜
R g ⎟⎠
⎝
(eq. 3.14)
The second stage is a Op-amp in a difference amplifier configuration, and thus
vout =
Rf
Ri
(vout 2 − vout1 )
34
(eq. 3.15)
AMPLIFIER ARCHITECTURES
Combining eq. 3.14 and eq. 3.15 gives
vout = A(vin 2 − vin1 )
(eq. 3.16)
where A is the total gain. The total gain is given by
⎛ 2R ⎞ ⎛ R f
A = AΙ × AΙΙ = ⎜1 + 3 ⎟ × ⎜⎜
⎜
R g ⎟⎠ ⎝ Ri
⎝
⎞
⎟⎟
⎠
(eq. 3.17)
where the total gain A is the product of the first- and second-stage gains AI and AII.
Since the input Op-amps are connected in a non-inverting configuration their input
impedance becomes extremely high. Likewise the output impedance of Op3 is low.
Hence the circuit in Fig. 3.11 meets all the requisites for an IA given above.
DUAL-OP-AMP IA
It can be advantageous to use as few Op-amps as possible in an IA. An IA with two
Op-amps is shown in Fig. 3.12 [6]. The configuration in Fig. 3.12 is referred to as a
Dual-OP IA.
R4
R3
R1
R2
Vref
Vout
Op1
Op2
Vin1
Vin2
Fig. 3.12 Dual-OP IA configuration
Since Op1 is a non-inverting amplifier its output voltage is
⎛
R ⎞
vout1 = ⎜⎜1 + 3 ⎟⎟vin1
R4 ⎠
⎝
(eq. 3.18)
The output voltage of the circuit, vout, is given by
⎛R ⎞
⎛ R ⎞
v out = −⎜⎜ 2 vout1 + ⎜⎜1 + 2 vin 2
R1 ⎠
⎝ R1 ⎠
⎝
35
(eq. 3.19)
AMPLIFIER ARCHITECTURES
Combining eq. 3.18 and eq. 3.19 gives following expression of Vout
⎛
⎞
1 + R3 / R4
R ⎞⎛
vout = ⎜⎜1 + 2 ⎜⎜ vin 2 −
vin1
1 + R1 / R2
⎝ R1 ⎠ ⎝
⎠
(eq. 3.20)
For true differential operation the resistances must have the relationship of
R3 R1
=
R4 R2
(eq. 3.21)
When eq. 3.21 is true the output voltage is given by
⎛ R ⎞
v out = ⎜⎜1 + 2 (vin 2 − vin1 )
⎝ R1 ⎠
(eq. 3.22)
The circuit in Fig. 3.12 has high input impedance and low output impedance. The
obvious advantages with a dual-op-IA compared to the more common used triple-opIA is the fewer Op-amps and resistors that makes the circuit cheaper, smaller and
more power effective. A drawback of the circuit is that the input signals are treated
asymmetrically because vin1 first has to propagate through Op1 before it catches up
with vin2. The delay in Op1 makes a deterioration of the common-mode component
cancellation in the two input signals when the frequency arises. Thus a degradation of
the CMRR with respect to the frequency is the trade off for using fewer Op-amps.
In the equations of both the triple-Op and dual-Op IA the reference voltage is
assumed to be at ground potential. The reference voltage determines the CM-level of
the output voltage, which in this case is 0V.
36
AMPLIFIER ARCHITECTURES
3.3.3 Op-amp with Differential to Single Input Stage
Instead of using multiple Op-amps in an IA, a differential amplifier can be realized
using a differential to single converter and one Op-amp.
DIFFERENTIAL TO SINGLE CONVERTER
To handle a differential input and convert it to a single-ended signal a differential-tosingle converter has to be designed. One idea is to use two second generation current
conveyors (CCII) to design a differential-to-single converter.
A CCII is a three port device that operates as a voltage follower between port X and
Y, and a current follower between port X and Z [7]. The definition of a CCII is shown
in eq. 3.23 – eq. 3.25. Key features of CCII are low gain error, low DC error, high
linearity and a wide bandwidth.
Iy
Vy
Vx
Ix
Y
Z
X
Iz
Vz
Iy = 0
(eq. 3.23)
Vx = V y
(eq. 3.24)
Iz = Ix
(eq. 3.25)
Fig. 3.13 Block schematic of a CCII
A differential-to-single converter using two CCII is shown in Fig. 3.14. Eq. 3.23
implies that no current is flowing into or out from the Y port of the differential to
single converter.
Vin+
Ie
Y
CCII Z
Ie
X
R1
Vout
R2
X
CCII
Vin-
Y
Vref
Fig. 3.14 Differential to single converter based on CCII
It is concluded from eq. 3.24 that the voltage across R1 is equal to Vin+-Vin-. The
voltage across R1 produces a current equal to
Ie =
Vin + − Vin −
R1
37
(eq. 3.26)
AMPLIFIER ARCHITECTURES
The current (Ie) is flowing out from one of the CCII and into the other CCII. From eq
3.25 we know that Ix = Iz. Hence, the same current is flowing in both R1 and R2. The
voltage across R2 has to be equal to
Vout − Vref = I e ⋅ R2
(eq. 3.27)
Combing eq. 3.26 and eq. 3.27 gives
Vout =
R2
(⋅ Vin+ − Vin − ) + Vref
R1
(eq. 3.28)
Hence, the differential signal is converted to a single-ended signal.
A DIFFERENTIAL TO SINGLE AMPLIFIER
The circuit in Fig. 3.15 consists of two stages. The first stage is the differential-tosingle converter presented above and the second stage is Op-amp in a non-inverting
configuration. The gain of the amplifier is given by
G=
R2
R1
⎛ R3 ⎞
⎜1 +
⎜ R4
⎝
⎠
(eq. 3.29)
Ie
Vin+
CCII
Ie
+
Op-amp
R1
Vout
-
CCII
VinR2
R4
R3
Vref
Fig. 3.15 Differential amplifier using CCII and Op-amp
38
AMPLIFIER ARCHITECTURES
A SECOND GENERATION CURRENT CONVEYOR IN CMOS
Fig. 3.16 shows an implementation of a current conveyor in CMOS [7]. With properly
matched transistors Mn5 and Mp5 have the same gate- source voltage and same drain
current (Ibias). Since, Mn5 and Mp5 have the same drain current Iy is ideally equal to
0A.
The translinear cell, Mn5, Mn6 and Mp5, Mp6, is designed to have equal gate-source
voltages. A KVL (Kirschoffs voltage law) in the translinear cell gives the relationship
Vx = Vy.
The drain current of Mn6 and Mp6 are equal at the quiescent point. A current flowing
out from or into node X is mirrored to node Z (Ix = Iz). This implies that all the
conditions of a CCII are satisfied.
Mp2
Mp1
Mp3
Mn5
Ibias
Mn6
Y
X
Mp5
Mn1
Mp4
Z
Mp6
Mn2
Mn3
Fig. 3.16 CCII in CMOS
39
Mn4
AMPLIFIER ARCHITECTURES
3.4 Charge Transfer Amplifier
The last architecture investigated in this work is the charge transfer amplifier (CTA),
which is very different from the OTA and Op-amp. The advantage with CTA is
mainly their potentially low power consumption. The CTA consumes little or no
power during static operation.
The charge transfer amplifier (CTA) operates by transferring a charge to or from the
capacitor CT to the load capacitor. The quantity of charge transferred to or from the
load capacitor is proportional to the input voltage (transconveyance).
3.4.1 NMOS CTA
A simplified schematic of the NMOS CTA amplifier core is shown in Fig. 3.17 [8].
The NMOS CTA requires three different timing phases, shown in Fig. 3.17. The
phases are called Reset-, Precharge- and Amplify-phase. The dynamic behavior of a
CTA is difficult to characterize, a complete description of the dynamic behavior is
carried out in [8]. In the following relationships all second order effect are ignored.
Vss
Vin
VpreC
Res
S1
S2
S1
Cload
Amp
Res
S1
VB
CT
Pre
S2
Vo
Time
Fig. 3.17 NMOS CTA and its three timing phases
Reset phase
In the reset phase, CT is connected to Vss and discharged. The output node is
connected to the precharge voltage VPreC and Cload is charged. Thus, the voltages at the
end of the reset phase are
V B = VSS
(eq. 3.30)
VO = VPr eC
(eq. 3.31)
40
AMPLIFIER ARCHITECTURES
Precharge phase
CT is connected to the source of the NMOS transistor during the precharge phase. At
beginning of this phase VB = Vss and Vo = VPreC. Current flows from output node to CT
until the transistor reaches the cutoff region. At the end of the precharge phase we
have
V B = V IN − VTN
(eq. 3.32)
VO = VPr eC
(eq. 3.33)
Amplification phase
A change in VIN (∆VIN) will result in the same change at the source of the NMOS
transistor (node B).
V B = VIN + ∆V IN − VTN
(eq. 3.34)
The change in Vin produces a current flowing from the output node to the node B
(From Cload to CT). The change in charge at the CT is equal to
∆Q = ∆VIN ⋅ CT
(eq. 3.35)
Since the current is conveyed from Cload through the NMOS transistor to CT the
following relationship is valid at the output
∆Q = ∆V ⋅ C load
o
(eq. 3.36)
Combining eq. 3.35 and 3.36 gives
∆VO =
CT
∆VIN
C load
(eq. 3.37)
To conclude, at the and of the amplification phase
V B = VIN + ∆V IN − VTN
(eq. 3.38)
CT
∆V IN
C load
(eq. 3.39)
VO = VPr eC −
The idea with a charge transfer amplifier is that when the device reaches cutoff region
no current should flow from the drain to the source. However, the subthreshold
current is too large to ignore and causes a relatively large voltage drop, especially
when the voltage between the source and drain is large. Moreover, the NMOS CTA
41
AMPLIFIER ARCHITECTURES
can only amplify positive input signals. This makes the NMOS CTA not feasible to
our application.
3.4.2 Other CTA Architectures
A solution to the problem incorporated with the NMOS CTA is to add a PMOS CTA
in parallel with NMOS counterpart (Fig. 3.18) [9]. The main idea of the CMOS CTA
is that the non-idealities such as subthreshold current should cancel each other out.
Vdd
CT
S1
VpreC
VA
Vdd
S1
S2
Vout
Vin=Vpre+∆Vin
Vss
Cload
S1
VB
S1
CT
Vss
Fig. 3.18 Simplified schematic of CMOS CTA
The CMOS CTA is reset in a similar way as the NMOS CTA, the capacitors are
discharged. At the end of the precharge phase the output has the potential of
VOut = VPr eC
(eq. 3.40)
and the sources of the transistors (gate precharged to VPreC)
V A, B = VPr eC ± VTN
(eq. 3.41)
The drain-source voltage is equal to |VTN|, an increase in Vin (positive or negative)
leads to a charge transfer trough the transistor with the corresponding voltage drop.
However, the maximum output voltage possible before both of the devices reaches the
cutoff region (VDS=0) is
VO = VPr eC ± VTH
(eq. 3.42)
Another CTA topology is the differential CMOS CTA, which further reduces the
offset voltages [8]. The main idea is to use two CMOS CTAs in parallel to get a fully
differential amplifier. AMIS has proposed an improved differential CTA, which does
not require a precharge voltage and input capacitance [10]. AMIS claims that they
42
AMPLIFIER ARCHITECTURES
have overcome some of the problems with the differential CTA. However, to the
authors’ knowledge the limited output voltage range still remains.
An application of the CTA is to use it as a preamplifier followed by a track and latch
stage in A/D converters [9]. The gain in the CTA is normally 4 to 10 times and the
output voltage of the preamplifier is normally in the order of a few tens of mV.
43
44
SIMULATIONS
4 Simulations
In this chapter simulations are presented. The simulations in this report are delimited
to transmission lines, current feedback operational amplifiers and instrumentation
amplifiers. The simulations were done in Hspice and the results viewed in Mentor
Graphics Awaves. The schematics were done in Mentor Graphics’ Led.
4.1 Transmission Lines
Signals in the data channel are transmitted in transmission lines. A schematic of
differential transmission lines with termination resistors is shown in Fig. 4.1.
Driver
Line
Zs=50 Ω
ZT1=50 Ω
Z0=50 Ω
l=0.5 m
VT1
Vdiff
VT2
Vcm
Zs=50 Ω
ZT2=50 Ω
Fig. 4.1 Transmission line with terminations
Hspice allows the user to create cable models based upon measured data. Using data
from [1] a model for a 50Ω cable was created. The parameters of the transmission
lines used in our simulations are
vrel=0.67
Attenuation –2dB at 250 MHz
Z0=50Ω
where vrel is the speed of the signal relative to the speed of light (3·108 m/s) and Z0 is
the characteristic impedance of the transmission line.
45
SIMULATIONS
Fig. 4.2 shows the positive signal at near-end (solid line) and far-end (dashed line)
with perfect match (Γ=0) (appendix F). The wire model used in this simulation is lossless and has the length of 0.5m. The total delay time for the pulse from the source to
the output of the transmission lines is given by
l Tline
0.5
=
= 2.5ns
v cable 2.0 ⋅ 10 8
where lTline is the length and vcable is the speed of the transmission lines.
t=
(eq. 4.1)
Fig. 4.2 Signals at near- and far-end of the transmission, (Γ=0)
To illustrate the consequence of termination mismatch at the near- and far-end a
simulation with ZT = 75Ω was performed. The simulation with transmission lines
without attenuation is shown in Fig. 4.3. The simulation shows a reflection of 20% of
the incident wave, which was expected (Γ=-0.2).
Fig. 4.3 Signals at near- and far-end of the transmission, (Γ=-0.2)
46
SIMULATIONS
The delay and attenuation of the signal changes with wire length. Fig. 4.4 shows the
signals with wire lengths of 0.5m, 1m and 1.5m, respectively. The delay is
consequently 2.5ns, 5ns and 7.5ns. Compared to Fig. 4.2, the signal degradation
owing to cable loss is apparent.
Fig. 4.4 Signals at near- and far-end of the transmission line with different lengths
47
SIMULATIONS
4.2 A Bipolar Current Feedback Amplifier: THS3001
There are many general purpose amplifiers available on the market. In a research, the
most suitable amplifier was the current feedback amplifier Op-amp THS3001 from
Texas Instrument Inc. As the majority of the available CFAs it is designed in a bipolar
technology. The THS3001 is manufactured in a complementary, high speed and high
voltage bipolar process.
According to the specification of THS3001, it has a unity gain frequency of 420MHz
and a maximum slew rate of 6500 V/µs (25% to 75% of the output voltage at 30V
power supply) [11]. When driving a capacitive load larger than 10pF a series resistor
of at least 20Ω must be used to ensure stabile operation [12].
4.2.1 Difference Amplifier using THS3001
To determine if THS3001 could handle the requirement given, it was simulated in a
difference amplifier configuration, Fig. 4.5. Since there is a relationship between the
feedback resistor and the bandwidth of a CFA, the configuration in Fig. 4.5 was
simulated with feedback resistors (RF) of 900, 1000, 1200, 1500 and 1700Ω. The gain
of the amplifier had a constant value of 12.
Rf1
Rg1
RL=20 Ω
-
Vdiff
Vo
+
Vcm
CL=10 pF
Rg2
Rf2
Vref=6 V
Fig. 4.5 THS3001 in difference amplifier configuration without transmission lines
48
SIMULATIONS
Fig. 4.6 shows the full swing input and output signals of the setup in Fig. 4.5 with
different values of the feedback resistor, 0.9-1.7kΩ. The rise times and overshoots
differ with different feedback resistors. The highest slew rate, but also the largest
overshoot (6%), is achieved with the smallest feedback resistor (0.9kΩ). The rise time
with a 0.9kΩ resistor is 1.6ns and with a 1.7kΩ resistor the rise time has increased to
4.7ns.
Fig. 4.6 Output and positive input signals of the difference amplifier with different
feedback resistors
Fig. 4.7 zooms in the output signal in Fig. 4.6 to estimate the settling time (note the
first overshot in Fig. 4.6 is excluded in Fig. 4.7). The output signal, when RF=1.2kΩ,
settles within 0.1% of the output swing at 62ns. Since the signal start rising at 50ns
the settling times becomes 12ns. The settling time is 10 and 18ns for values of RF of
0.9 and 1.7k, respectively.
Fig. 4.7 Zoomed version of Fig. 4.6
49
SIMULATIONS
POWER CONSUMPTION
The power consumption, when the output swings between 0 and 12V every 25ns, is
shown in Fig. 4.8. The average power consumption at full output swing is given in
Table 4.1.
Table 4.1 Average power
consumption of Fig 4.8
(CL=10pF, RL=20Ω)
Rf
Power
240mW
0.9kΩ
225mW
1.0kΩ
210mW
1.2kΩ
190mW
1.5kΩ
180mW
1.7kΩ
Fig. 4.8 Full swing power consumption of the difference amplifier
Fig. 4.9 shows the steady state power consumption. The input voltage is ramping from
0 to 1V during 200ns. The average steady state power consumption is given in Table
4.2.
Table 4.2 Average power
consumption of Fig 4.9
(CL=10pF, RL=20Ω)
Rf
Power
170mW
0.9kΩ
160mW
1.0kΩ
145mW
1.2kΩ
135mW
1.5kΩ
128mW
1.7kΩ
Fig. 4.9 Steady state power consumption of the difference amplifier
50
SIMULATIONS
RISE AND FALL TIME WITH DIFFERENT LOADING
To investigate how different load resistances affect the rise time of the amplifier,
simulations with different load resistors were done. The different load resistors (RL)
used in the simulation was 0Ω, 20Ω, 50Ω, 100Ω and 500Ω. The power consumption
is independent of the load resistance. RF used in the simulation is 1.5kΩ.
Fig. 4.10 Output signal of the difference amplifier with different load resistances
If the load resistance becomes too large the amplifier cannot meet the speed
requirement. The crucial load resistance is between 50 and 100Ω. It is also interesting
to be aware of the influence of the capacitive load. Simulation with different load
capacitances is shown in Fig. 4.11. The rise time becomes faster when CL decreases
but with the payoff of large overshoots. The power consumption becomes higher due
to larger CL, Table 4.2.
Table 4.2 Average power
consumption with
different load capacitance
(CL=10pF, RL=20Ω,
Rf=1.5kΩ)
CL
Power
5pF
180mW
10pF
190mW
20pF
235mW
50pF
535mW
Fig. 4.11 Output signal of the difference amplifier with different capacitive loads
51
SIMULATIONS
4.2.2 Difference Amplifier using THS3001 with Transmission Lines
Fig. 4.12 shows THS3001 in a difference amplifier configuration connected to
transmission lines. The transmission lines used are presented in chapter 4.1.
Driver
Line
RT1=50 Ω
Rs=50 Ω
Z0=50 Ω
l=0.5 m
Vb=0 V
THS3001
Rf1=1.5 kΩ
Rg1=125Ω
_
RL=20 Ω
Vout
Vdiff
+
Rg2=125Ω
Rs=50 Ω
Vcm
CL=10 pF
Rf2=1.5kΩ
RT2=50Ω
Vb=0 V
Vb=0 V
Vref=6V
Fig. 4.12 Difference amplifier in the data transmission channel
Even though the ratio of the feedback resistors (Rf/Rg) is 12 (i.e., the gain) and the
differential input toggles between 0 and 1V the output voltage of the amplifier does
not have a swing of 0-12V, Fig. 4.13. The gain of the system is reduced due to
currents flowing in the feedback resistors.
Fig. 4.13 The full swing output signal of the difference amplifier in the data
transmission channel
52
SIMULATIONS
The currents flowing through RF1 and RF2 is illustrated in Fig 4.14, where the current
fed back from the output is the solid line and the current from the reference voltage is
the dashed line. The currents are not symmetrical since different voltages are across
the feedback resistors. The voltage across RF1 is determined by Vout-Vin and the
voltage across RF2 is equal to Vref-Vin, where Vin is the input voltage at the noninverting port of the Op-amp.
Fig. 4.14 The current flowing trough Rg1 (dashed line) and Rg2 in the difference
amplifier in the data transmission channel
A current fed back may not be crucial to the application, but the non-symmetry will
causes problems for the differential input signal. Fig. 4.15 shows the differential input
signals to the amplifier and it can be seen they are not each other’s inverse. The nonsymmetry of the input voltage is due to the non-symmetry in the currents flowing in
the terminating resistors (RT).
Fig. 4.15 The input voltages to the difference amplifier in the data transmission
channel
53
SIMULATIONS
4.2.3 Triple-Op-amp Instrumentation Amplifier
It was shown in the previous chapter that a single Op-amp in a difference amplifier
configuration cannot be used in the data transmission system. The input signals get
corrupted due to currents flowing through the feedback resistors. Hence, an input
stage is needed to isolate the feedback net from the transmission lines. In an IA the
inputs are isolated from the feedback net.
The triple-Op-amp IA in Fig. 4.16 consists of three THS3001 Op-amps. The IA has a
total gain of 12. The gain is divided into the first and second stage where the first
stage has a gain of 3 and the second of 4. The amplifier was simulated with the inputs
connected to the transmission line presented in chapter 4.1.
Ri
Vin+
Rf
Op1
R3
Rg
Rload
Cload
R3
Vin-
Op2
Ri
Vout
Op3
Rf
Vref
Fig. 4.16 Triple-Op-amp IA using THS3001
The rise time of the triple-Op-amp IA configuration in Fig 4.17 is 3.8ns and the fall
time is 4.2ns and is shown in Fig 4.17. Changing the size of the feedback resistors
alter the slew rate. The IA has a –3dB frequency of 83MHz.
Fig. 4.17 Full swing output voltage of the triple-Op-amp IA
54
SIMULATIONS
The power consumption at full swing is shown in Fig. 4.18 and the average
consumption is 300mW.
Fig. 4.18 The power consumption the triple-Op-amp at full swing
The steady state power consumption of the triple-Op-amp IA varies between 230 and
260mW and is shown in Fig. 4.19.
Fig. 4.19 The steady state power consumption of the triple-Op-amp IA
55
SIMULATIONS
4.2.4 Dual-Op-amp Instrumentation Amplifier
A dual-Op-amp IA is shown in Fig. 4.20. The setup was simulated using two
THS3001 Op-amps and its inputs connected to the transmission line in chapter 4.1.
R4=11kΩ
R3=1kΩ
R1=136Ω
R2=1.5kΩ
Vref=6V
RLoad=20Ω
Op1
Op2
Vout
Cload=10pF
Vin+
Vin-
Fig. 4.20 Dual-Op-amp IA using THS3001
With the setup in Fig 4.20 the rise and fall time are both 4.3ns. The –3dB frequency of
the configuration is 90MHz. The input and output signals of the dual-Op-amp IA are
shown in Fig. 4.21.
Fig. 4.21 Input and output signals of the dual-Op-amp IA
56
SIMULATIONS
The non-inverting (dashed) and inverting (solid) input voltages of Op2 in Fig. 4.20 are
shown in Fig. 4.22. The inverting input is delayed 2.5ns due to the propagation delay
in Op1.
Fig. 4.22 The delay between the inputs of Op2 in the dual-Op-amp IA
The CMRR versus the frequency is shown in Fig. 4.23. The CMRR is poor for high
frequencies due to the delay in Fig. 4.22
Fig. 4.23 The CMRR versus the frequency of the dual-Op-amp IA.
57
SIMULATIONS
The power consumption of the dual-Op-amp when the output swings between 0 and
12V is shown in Fig. 4.24. The average power consumption is 250mW.
Fig. 4.24 The dynamic power consumption of the dual-Op-amp IA.
The power consumption as a function of the input signal is shown in Fig. 4.25. The
steady state power consumption has a minimum value of 170mW and a maximum of
215mW.
Fig. 4.25 The steady state power consumption of the dual-Op-amp IA
58
SIMULATIONS
4.3 Amplifiers in CMOS
4.3.1 Current Feedback Amplifier
To evaluate the performance of the CMOS CFA presented in chapter 3.2.3, it was
simulated in HSPICE with medium voltage transistors from the process XC06 from
X-Fab. The CFA was simulated in a non-inverting configuration, Fig 4.26. The
amplifier can be designed in different ways depending on its wanted performance. In
the simulations presented, the amplifier is designed for maximum speed.
Vdd1
Mn4
Mn10
Mp4
Mp5
Mn3
Mp3
Vin+
Vss2
Vdd2
Vin-
Mn1
Mp10
Vbias1
Mp6
Mn9
Mp9
(H)
CC
Vout
CL
Mn7
Mn6
Vbias2
Mp1
Mn2
RL
Vss3
Vdd3
Mn5
Mp7
Mn8
Mp2
Mp8
Vss1
RF
RG
Vref
Fig. 4.26 The CMOS CFA in a non-inverting configuration
All transistors in the circuit in Fig 4.26 have their bulk terminals connected to their
source terminals even though that is not feasible in the process used. The need to have
no bulk-source voltage is caused by the high output voltage swing. The high output
voltage swing forces the source terminal of Mn7, Mn9 and Mn10 (the NMOS transistors
close to the positive supply voltage) to have potential close to the positive supply
voltage. If the bulk terminal was connected to the negative supply potential, which is
done in a single-well process, a very high threshold voltage would be generated due to
the body effect.
59
SIMULATIONS
The rise and fall time of the CFA are both 10 ns for a 10V step when the amplifier is
designed for maximum speed. It is important to investigate how the signal appears
when it reached its peak, especially when operating with large voltages. The settling
time (0.1%) of the output voltage is 50ns.
Fig. 4.27 The input and output voltage of the CMOS CFA
The steady state power consumption of the CFA is shown in Fig. 4.28. The power
consumption is considerably higher for a steady state input voltage of 0.5V than for
the positive and negative maximums. The high power consumption is due to the
configuration of the amplifier output stage.
Fig. 4.28 The steady state power consumption of the CMOS CFA
60
SIMULATIONS
The power consumption when the output toggles between 0 and 10V is shown in Fig.
4.29. The average power consumption is 275mW, which is lower than the power
consumption at a steady state output of 6V. Hence, the worst-case power consumption
is not shown in Fig. 4.29.
Fig. 4.29 The dynamic power consumption of the CMOS CFA at full swing
The circuit in Fig. 4.26 can be designed in different ways depending on its wanted
performance. Larger transistors generate smaller overshoots but decrease the rise time
and increase the power consumption. By using higher supply voltage a faster rise time
is obtained but with a trade-off of higher power consumption and possibilities of
transistor breakdown. The rise time of the amplifier can also be decreased by using
smaller feedback resistors or compensation capacitance or both, but with increased
overshoots.
61
SIMULATIONS
4.3.2 Differential to Single Converter
A single Op-amp cannot be used as a receiver in the data channel because the input
signals gets affected by the current flowing in the feedback resistors. A differential to
single converter can be used to isolate the feedback net from the transmission lines. A
differential to single converter using CCII is shown in Fig. 4.30. The CCII used were
presented in chapter 3.3.3.
Ie
Y
V
in+
Ie
CCII Z
X
R1
Vout
R2
X
CCII
Vin-
Y
Vref
Fig. 4.30 A differential to single converter based on CCII
The input and output signals of the differential to single converter are shown in Fig.
4.31. In theory the gain of the differential to single converter is R1/R2, but due to nonidealities of the transistors the gain is smaller than expected. The decreased gain can
be compensated by changing the ratio of the resistors. To lift the input signal CMlevel of 0.25V to the wanted output level of 5V, the reference voltage is used. In
theory, a Vref potential of 5V gives a CM-level of 5V at the output, but due to nonidealities of the transistors an unwanted offset occurs. However, the offset can be
compensated by changing Vref.
Fig. 4.31 The differential input and the single-ended output signals of the differential
to single converter
62
SIMULATIONS
4.3.3 Differential Amplifier in CMOS
A differential amplifier in CMOS was introduced in chapter 3.3.3 and shown in Fig.
4.32. The amplifier was simulated with its inputs connected to the transmission line in
chapter 4.1. The CMOS CFA simulated in chapter 4.3.1 was used as the Op-amp in
this configuration.
Ie
Vin+
CCII
Ie
+
R1
CFA
-
CCII
VinR2
R3
R3
Vbias
Fig. 4.32 Differential amplifier with CCII and CFA
The speed of the circuit is limited by the CFA since the differential to single input
stage is very fast. The rise time of the CFA is 10ns and the same rise time is achieved
of the differential to single amplifier. The input and output signals are shown in Fig.
4.33.
Fig. 4.33 The output signal and the differential input signals of the differential
amplifier
63
SIMULATIONS
The biasing current of the differential to single converter (Ibias in Fig. 3.16) is set to
0.5mA. The power consumption of the differential to single converter with Ibias equal
to 0.5mA is 60mW. The power consumption of the differential amplifier is given by
adding the power consumption of the two stages. Since the average power
consumption of the CMOS CFA is 275mW, the average power consumption at full
swing is 335mW.
In an ideal differential amplifier no current flows from the input nodes. However, in
the differential amplifier in Fig 4.34 small currents flows from the input nodes. These
currents are symmetrical and do not affect the performance of the amplifier. However,
currents like these might cause problems when non-ideal drivers are used.
64
DISCUSSIONS
5 Discussions
An important part of our study was to analyze, compare and understand bipolar and
CMOS implementations of high performance amplifiers. CMOS technology is always
very desirable in terms of high integration and low cost but there exists limitations
when high-performance analog designs are the target. Not only the well-known
problem of low transconductance (gm) but also other secondary effects like bodyeffect and short-channel-effect can limit the feasibility of high performance amplifier
designs.
State-of-the-art IC technologies using smaller dimensions can be used to design fast
amplifiers with a low output voltage swing. However, the high output voltage swing
excludes the possibility to use advanced CMOS technology such as a 0.18µm CMOS
process.
CFA
As shown in chapter 3, CFA is more suitable than VFA when designing high slew rate
and wide bandwidth operational amplifiers. CFAs are usually designed in bipolar
technologies and their slew rates are normally between 500 and 2500V/µs compared
to a maximum slew rate of about 100V/µs from a VFA with comparable quiescent
current. However, there are many difficulties in designing CFAs. The main problem is
the limited availability of very similar complementary transistors, i.e., NPN and PNP
for bipolar transistors, and NMOS and PMOS for MOS transistors. In fact, one cannot
have full control on matching of the complementary transistors. As a consequence,
CFAs have poorer DC-performance and common-mode rejection characteristics than
VFAs. DC errors of CFAs are due to different biasing voltage (Vbe) for NPN and PNP
transistors, or as in a CMOS case, different threshold voltages (Vth) for NMOS and
PMOS transistors. As an example the Vbe can range from a few to 40mV, while the
difference between the Vth can be more than 100mV.
There is not much literature about CMOS CFAs. An explanation for this situation is
that without modern twin-tube technologies it is very difficult to have good designs
for such amplifier architectures. The circuit used in this study was designed using a
classical CMOS technology including its component library with medium voltage
PMOS and NMOS transistors.
65
DISCUSSIONS
Our main problem was caused by the necessity of high output voltage swing (12V).
The high output voltage swing combined with the specific intern circuitry for our
CFA, and the limited drain-source breakdown voltage (15V), results in difficulties to
keep the transistors in the active region. The simulation results show non-linear
behavior of the gain, and limitations of the output swing (10V).
A problem we have ignored in the simulations is the body-effect, which will degrade
the amplifier performance even more. In fact, it is very hard to design a CFA having
such a high performance characteristic (12V output swing and 1.9kV/µs slew rate) in
a single-well CMOS process.
The power consumption in our CMOS CFA design is higher than a comparable
bipolar CFA. The main power consumption comes from the output buffer. The
configuration of the output buffer and the high output voltage swing results in a high
static current consumption and thus high power dissipation.
THS3001
It is not feasible to use a single general-purpose Op-amp such as THS3001 from
Texas Instrument as a difference amplifier together with transmission lines.
Using a single Op-amp causes problems with the differential input signal, it is
affected by the current fed back from the output. A solution to this problem is to
isolate the feedback net from the inputs, which can be achieved by using an
instrumentation amplifier configuration.
Two different instrumentation amplifier configurations, triple-Op-amp and dual-Opamp, were tested using THS3001. Both configurations can handle the required speed.
The triple-Op-amp IA uses more components and has higher power consumption than
the dual-Op-amp. The average full swing power consumption is 300mW and 250mW,
respectively. The main advantage with the triple-Op-amp is that it has higher CMRR
than the dual-Op-amp at high frequencies.
An alternative solution that might be more power effective is to use an extra
component to transform a differential signal to single-ended signal before the input of
THS3001.
CTA
Today CTA is used in comparator designs and in low power applications where small
gains and small output voltages are desirable. Furthermore, the speed together with
the high voltage swing needed in our system is hard to achieve using a CTA.
66
CONCLUSIONS
6 Conclusions
•
Current feedback amplifiers are the best operational amplifier architecture to
handle the wanted slew rate.
•
In a system with an amplifier as a receiver with differential transmission lines, a
single operational amplifier cannot be used. An input stage is needed to isolate the
feedback net from the inputs of the amplifier.
•
A current feedback amplifier in CMOS with the required high output voltages and
slew rate is hard to realize without very high power consumption.
•
THS3001, from Texas Instrument Inc., in an instrumentation amplifier
configuration is feasible in terms of slew rate requirements, but with high power
consumption. The power consumption is 250mW for a dual-Op-amp and 300mW
for a triple-Op-amp.
•
To reduce the power consumption, a bipolar ASIC designed to combine a current
feedback OP with a high impedance input stage is recommended.
67
68
REFERENCES
7 References
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Shaofang Gong, Internal-document, Micronic, “Choice of packaging
and signal transmission techniques for the SLM3 data link interface”
2002-05-21
[2]
David A. Johns and Ken Martin, Analog Integrated Circuit Design,
(1997), John Wiley & Sons, USA
ISBN 0-471-14448-7
[3]
Jacob R. Baker and Harry W. Li and Boyce, David E, CMOS Circuit
Design, Layout and Simulation, (1998), Wiley-IEEE Press, New York
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[4]
J Austin, “Current feedback amplifier: review, stability analysis, and
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[5]
K Manetakis, C Toumazou And C Papavassiliou “A High-Frequency
CMOS Current OPAMP” IEEE Custom Integrated Circuits Conference,
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[6]
Sergio Franco, Design with Operational Amplifiers and Analog
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[7]
J. Popvic, A. Pavasovic, D. Vasiljevic, “Low-power High Bandwidth
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[8]
W. Marble and D. Comer “Analysis of Dynamic Behavior of a ChargeTransfer Amplifier” IEEE Transactions on Circuits and Systems – I,
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[9]
K. Kotani et al., ”CMOS charge-transfer pre-amplifier for offsetfluctuation cancellation in low-power A/D converters” IEEE J. Solidstate Circuits, vol 33 pp.762-768, May 1998
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William Marble. ”Effektsnålare A/D med ny laddningsförstärkare”
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James Kaki, “Driving Capacitance with THS3001” Texas Instrument
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70
APPENDIX B
Appendix A
The Rise Time
A derivation of the relationship of the rise time and -3dB frequency is given in this
appendix. The frequency response of a one-pole amplifier in a closed loop
configuration can be written
A(s ) =
1+
ADC
s
(eq. A.1)
ϖ −3dB
where ADC is the gain of the amplifier and ω-3dB where the amplifer gain has decreased
with 3 dB [6].
If Vin is a step function with magnitude Vin in the time domain, then the Laplace
function is
V
Vin (s ) = in
(eq. A.2)
s
The gain of an amplifier is given by
V (s )
(eq. A.3)
A(s ) = out
Vin (s )
Combining eq. A.1 and A.2 gives an expression of the output voltage of
Vout (s ) =
Vin
ADC
⋅
s 1+ s
=
ϖ −3dB
Vin ADC
⎛
s ⎞
⎟⎟
s⎜⎜1 +
⎝ ϖ −3dB ⎠
(eq. A.4)
The output voltage transformed to the time domain is
(
vout (t ) = ADCVin 1 − e − t / τ
)
(eq. A.5)
where
τ=
1
ϖ −3dB
=
1
2πf −3dB
(eq. A.6)
The rise time from 10% to 90% of Vout is
t R = τ (ln 0.9 − ln 0.1)
(eq. A.7)
or
tR =
ln 9
0.35
=
2πf −3dB
f −3dB
71
(eq. A.8)
APPENDIX B
Appendix B
The Differential Pair
The most important analog building block is the differential transistor pair. It is used
as an input stage of a voltage feedback Op-amp and most integrated filters. The
transistors in a differential pair are usually matched, i.e., they have equal electrical
characteristics. A differential pair with matched MOS transistors and a bias current
source is shown in Fig. B.1. The current source has a total value of IB and bias both
M1 and M2 with a current of IB /2.
ID2
ID1
id1= is1
V+
vM1
id2= is2
v+
M2
vrs1
is1
is2
rs2
IB
Fig. B.1 The differential pair
Since gm1= gm2 the small signal current trough M1 can be expressed as
is1 = id 1 =
vin
vin
g
=
= m1 vin
1
1
2
rs1 + rs 2
+
g m1 g m 2
(eq. B.1)
where vin=v+-v-. The differential output current is defined as iout=- id1- id2. Because the
DC current source does not take any AC current, the same small-signal current flows
in M1 and M2 but with opposite direction, id1=-id2. Since id1=-id2, the output current of
the circuit is
iout = g m1 ⋅ vin
(eq. B.2)
It is important that a change in the common mode voltage in a differential amplifier
do not affect the output voltage. The measure of differential amplification with respect
to common-mode amplification is referred as the Common Mode Rejection Ratio
(CMRR) and defined as
Adiff
(eq. B.3)
CMRR =
Acom
72
APPENDIX B
Differential Amplifier Stage
A differential-input, single-ended-output circuit with active load is shown in Fig. B.2.
This circuit is often used as a first gain stage of a classical two-stage integrated Opamp. The input differential pair is n-channel transistors and the active load is realized
with a p-channel current mirror. The small-signal currents relation is given by
id 4 = id 3 = −id 1
(eq. B.4)
assumed that the output impedance of the transistors are neglected. By combining eq.
B.1. and the fact that id2=-id1,the output voltage is
vout = (− id 2 − id 4 )rout = 2is1rout = g m1rout vin
If the load is both resistive and capacitive, the gain is given by
Av = g m1 z out
M3
M4
vout
Is1
v+
v
M1
M2
Ibias
Fig B.2 A differential amplifier stage with an active load
73
(eq. B.5)
APPENDIX C
Appendix C
Derivation of closed loop bandwidth and gain of a CFA
The CFA consists of two buffers and a high impedance node. To derive the bandwidth
and the closed loop gain of the current feedback amplifier, the analytical model in Fig.
C.1 can be used [13]. Ro is the transimpedance, Cc is the compensation capacitor and
Rinv is the output impedance of the input buffer.
(2)
Cc
If
Vin
x1
Ro
Vout
(1)
x1
If
Rf
Rinv
Rg
Fig C.1 An analytical model of a CFA
Using KCL at node (1) gives the following relationship
Rg
Vin + Vout
Rinv
V1 Vout − V1 Vin − V1
=
+
⇒ V1 =
Rf
Rf
Rg
Rf
Rinv
1+
+
R g Rinv
(eq. C.1)
Using ohm’s law at node (2) results in (assuming infinite input impedance of the
output buffer)
I f Ro
(eq. C.2)
V2 =
1 + sR0 C c
If the output buffer has the gain equal to 1, the output voltage is
Vout = V2 =
I f Ro
1 + sR0 C c
(eq. C.3)
The relationship for If can be written as
⎛ 1
Vin − V1
1 ⎞⎟ Vout
−
(eq. C.4)
= V1 ⎜
+
⎟ R
⎜R
Rinv
R
g
f
f
⎠
⎝
Combining eq. C.1, C.2, C.3 and C.4 gives an expression of the output voltage of
If =
74
APPENDIX C
⎛⎛ R f
⎜⎜
V + Vout
⎜ ⎜ Rinv in
= ⎜⎜
⎜⎜ 1+ R f + R f
⎜⎜
R g Rinv
⎝⎝
⎞
⎟
⎟⎛⎜ 1
1 ⎞ Vout
⎟⎜ R + R ⎟⎟ − R
f ⎠
f
⎟⎝ g
⎟
⎠
⎞
⎟
⎟⎛ R g Abuf
⎟⎜⎜
⎟⎝ 1 + sRo C c
⎟
⎠
⎞
⎟⎟
⎠
(eq. C.5)
Rearranging eq. C.5 to express the gain of the amplifier gives
Rf
1+
Rg
V
A = out =
Vin
⎛ Rf ⎞
⎟ Rinv
R f + ⎜1 +
⎟
⎜
⎛
⎞
R
⎛ Rf ⎞
g
⎠
⎝
⎟ Rinv ⎟C c
+ s ⎜ R 2 + ⎜1 +
1+
⎜
⎜
⎟
R g ⎟⎠
Ro
⎝
⎝
⎠
(eq. C.6)
Vout
The DC-term in the denominator of eq. C.6 approaches zero since Ro is very large, in
the MΩ range, and Rinv is small. The gain is now
1+
A=
Vout
=
Vin
Rf
Rg
⎞
⎛
⎛ Rf ⎞
⎟ Rinv ⎟C c
1 + s ⎜ R 2 + ⎜1 +
⎜
⎟
⎜
R g ⎟⎠
⎝
⎠
⎝
(eq. C.7)
The DC-gain from eq. C.7 is
ADC =
Rf
Vout
= 1+
Vin
Rg
(eq. C.8)
and the pole is located
f pole =
Abuf
⎛
⎞
⎛ Rf ⎞
⎟ Rinv ⎟C c
2π ⎜ R f + ⎜1 +
⎜
⎜
⎟
R g ⎟⎠
⎝
⎝
⎠
(eq. C.9)
Since
⎛ Rf ⎞
⎟ Rinv
R f >> ⎜1 +
⎜
⎟
R
g ⎠
⎝
(eq. C.10)
the following relationship is valid
f pole =
Abuf
2πR f C c
75
(eq. C.11)
APPENDIX D
Appendix D
Integrated–Circuit Devices and Modeling
MOS is an acronym for metal-oxide-semiconductor. MOS circuits normally use two
types of transistors, n-channel and p-channel. N-channel transistors conduct current
with a positive gate voltage and p-channel with a negative gate voltage. Microcircuits
containing both n- and p-channel transistors are called CMOS circuits, for
complementary MOS. There are several different symbols for CMOS transistors and
the ones used in this text are shown in Fig D.1.
The source and the drain terminals in a MOS transistor are interchangeable. The
voltage magnitude at the terminals determines which one is the source. The source
voltage from an n-channel transistor is always lower than the drain voltage. The
source terminal in a p-channel device is determined by which terminal has the higher
voltage.
The MOS transistor is a four-terminal device where the substrate is the fourth
terminal. The substrate is referred as the bulk terminal. The bulk terminal on an nchannel device is almost always connected to the most negative potential in the circuit
i.e., the negative power supply. Normally the p-channel device bulk is connected to
the positive power supply. However, for CMOS technologies at least one of the
transistor types will be formed in a well substrate and do therefore not need to be
connected to one of the power supply nodes. The bulk in a well is often connected to
the source to reduce the body effect.
Drain
Source
Vgs
Id
Gate
Gate
Bulk
+
+
Bulk
Id
Vgs
Drain
Source
p-channel MOSFET
n-channel MOSFET
Fig. D.1 The symbol of a PMOS and NMOS
76
APPENDIX D
The threshold voltage
The gate-source voltage that makes the attracted electron concentration in the
substrate close to gate equal to the hole concentration in the substrate far from gate, is
called transistor threshold voltage and denoted VTHN. The threshold voltage is defined
as
VTHN = VTHN 0 + γ ( 2φ F + VSB −
2φ F
(eq. D.1)
where γ is the body effect coefficient and φF is the electrostatic potential of the
substrate. VTHN0 is threshold voltage when the source is shorted to the substrate, a socalled zero-bias threshold voltage.
Large-Signal Modeling
The relationship between the drain current and the drain-source voltage in a MOS
transistor differs depending which region it operates in. There are two different useful
regions, triode and active. In the triode region (also referred as linear) the drain source
voltage relates to the drain current as
2
VDS ⎤
W⎡
I D = µ 0 C ox ⎢(V gs − VTHN )VDS −
⎥
2 ⎥⎦
L ⎣⎢
(eq. D.2)
where µn is the mobility of electrons and Cox the gate capacitance. The drain current
increases with the drain-source voltage until the drain end of the transistor becomes
pinched off. This pinched off occurs for
V DS = VGS − Vtn = Veff
(eq. D.3)
When the transistor is pinched off the current no longer depends on Vds but only Vgs,
the transistor is in the active region. The relationship Id and Vgs is given by
substituting eq. D.3 into eq. D.2, resulting in
ID =
µ 0 C ox W
2
L
(V
− VTHN )
2
gs
(eq. D.4)
The drain current in eq. D4 is independent from the drain-source voltage, an
approximation that does not concern the channel-length modulation. The channellength modulation is the effect that occurs when the channel length becomes shorter
due to higher VDS. A decrease in the channel length increases the drain current and
VDS do thereby affect ID. A more accurate expression of the drain current is given by
ID =
µ n C ox W
2
⋅
L
(V
[
− VTHN ) 1 + λc (VDS − Veff )
2
gs
77
]
(eq. D.5)
APPENDIX D
Small-Signal Modeling
A small signal model of a NMOS transistor in the active region is shown in Fig. C.2.
The small-signal model shown is only valid for DC or low frequency voltage. When
operating a MOSFET at high frequencies the impact of parasitic capacitance becomes
large and the model of fig C.2 is no longer valid (a high frequency model is not
presented in this text).
id
D
G
vgs
S
gmvgs
gmbvbs
rds
S
vsb
B
Fig C.2 The small signal model of an NMOS transistor
The forward transconductance or gm is given by the slope of ids versus vgs. The
transconductance for a MOSFET gives the ratio between the output current and the
input voltage, i.e., the signal transfer. The transconductance is given by
gm =
∂I D
∂VGS
(eq. D.6)
and can be expressed with voltages by inserting the derivative of eq. D.4
g m = µ 0 C ox
W
(Vgs − VTHN )
L
(eq. D.7)
If the bulk is connected to the source no bulk transconductance occurs and the bulk
current is ignored. When the transistor has a bulk-source voltage a current is
generated due to the body effect. The bulk transconductance for a MOSFET is given
by
g mb =
∂I D
γ
=
⋅ gm
∂VSB 2 VSB + 2φ F
(eq. D.8)
where γ and ΦF are values given by the transistor manufacturer.
The last parameter added to get a useful model is the output resistance ro or output
conductance gds=go=1/ro. The output resistance is given by
ro =
1
λI DSat
78
(eq. D.9)
APPENDIX D
Second Order Model Effects
The MOS transistor model presented above is simplified and neglects a number of
important effects. Some of the missing effects in the basic model are the second order
effects. The basic model is commonly used, even though it is simplified, because it is
easy to use and it generates a basic design that is later optimized by simulations. The
second order effects are mostly used in just simulation programs which give them
tools to achieve a more realistic transistor model. These effects are only briefly
presented here, for more details [3, 14, 15].
Most second order effects are due to narrow or short channel dimensions and hence
called short channel effects. These effects include mobility degrading, reduced output
impedance and hot carrier effects (such as oxide trapping and substrate currents).
Differences in the temperature also cause changes in a MOS transistor behavior. The
threshold voltage and the transconductance parameter change with temperature. The
effects due to temperature differences can be derived to the changes in the mobility of
electrons caused by altering temperature.
An interesting feature of CMOS is the possibilities to predict the speed of the circuits
with a new process. With only the knowledge of the dimensions of the new process
the speed can be predicted. This is known as the scaling laws [16]. The scaling laws
were developed for digital CMOS and can not be applied to analog circuits in CMOS.
Analog circuits require capacitances, resistances etc. to ensure the correct function.
Therefore, analog circuits cannot be scaled without re-evaluating the circuit to ensure
its performance and functionality [16].
79
APPENDIX E
Appendix E
The Current Mirror
Current mirror building blocks are used both as current sources and active loads to
amplifier stages. An important property of the current mirror is its high output
resistance.
VCC
IIN
IOUT
IN
OUT
Current
mirror
VIN
VOUT
COMMON
Fig E.1 A block model of a current mirror
Simple Current Mirror
A basic NMOS current mirror is shown in Fig. D.2. What makes a current mirror
useable is that its two transistors, if they are identical, have the same drain current. ID2
is the circuit’s output or mirrored current and is often used as a current source.
To understand how a current mirror works, study Fig D.2, where the current ID1
through M1 is corresponding to VGS1. Assuming the transistors are in saturation the
same current or a multiple to ID1 is flowing through M2 because they have identical
gate source voltage. The current ID1 is given by
I D1 =
β1
2
(VGS1 − VTNH )2
(eq. E.1)
and the mirrored current ID2 flowing in M2 is
I D2 = I 0 =
β2
2
(VGS 2 − VTNH )2
80
(eq. E.2)
APPENDIX E
It can be desirable to determine ID2 with consideration to ID1. If VDS1= VDS2 the ratio
between the output and reference current is given by
I D2
I D1
W2
L
W L
β
= 2 = 2 1 = 2
W1 W1 L2 β 1
L1
(eq. E.3)
The reference drain current ID1 is calculated by using
I D1 =
VDD − VGS − VSS KP ⋅ W1
2
=
⋅ (VGS 1 − VTNH )
R
2 L1
(eq. E.4)
The output impedance of the mirror equals to the drain source impedance of M2
.
1
(eq. E.5)
rout = rds 2 =
gm2
It is a criterion that M2 is saturated to make the current mirror work. To ensure that
M2 is saturated the minimum voltage across M2 has to be
VDS 2,min = VGS − VTHN
ID1
ID2
M2
M1
Fig E.2 Schematic of a basic current mirror
81
(eq. E.6)
APPENDIX E
High Output Impedance Current Mirrors
It is desirable to have current mirrors with high output-impedance. High outputimpedance generates a better linearity and accuracy to the mirror. Two commonly
used current mirrors with improved output impedance are the cascode and the Wilson
mirror.
THE CASCODE CURRENT MIRROR
To get higher output impedance, cascode-connected transistors can be used. Through
a small signal analyses the output impedance is calculated to
rout = rds 4 (1 + g m 4 rds 2 ) + rds 2
(eq. E.7)
which can be simplified to
rout ≅ rds 4 ( g m 4 rds 2 )
(eq. E.8)
Hence, the output impedance has been increased by a factor gm4rds2 compared to a
basic current mirror. The minimum output voltage needed to keep the transistors in
the active region is
Vout > VDS 2 + Veff = 2Veff 1 + VTHN
(eq. E.9)
This means that the cascode mirrors output swing is lower than the basic current
mirrors.
VDD
Iin
Iout
M3
M4
Vout
M1
M2
VSS
Fig. E.3 Schematic of a cascode current mirror
82
APPENDIX E
WILSON CURRENT MIRROR
The Wilson current mirror is shown in Fig D.4. By using negative feedback Wilson
current mirrors can have a high output swing and remain its stability and high output
impedance.
The feedback in the mirror works as follows. Iin is a stable reference current that does
not get affected of the rest of the circuit. If Vout increases Id3 also increases. The
current through M2 is mirrored to M1, which means Id1 equals Id3. Because Iin does not
change and I1 is higher than Iin a voltage drop occurs at node A. The voltage drop
decreases Vgs3 and the current though M3 is stabilized.
The output impedance is given by
⎛g r ⎞
rout = rds 3 ⎜ m1 ds1 ⎟
⎝ 2 ⎠
(eq. E.10)
which is roughly half the impedance of the cascode current mirror. The minimum
output voltage to keep both M3 and M4 in saturation is
Vout = VGS 2 + VGS 3 − VTHN
(eq. E.11)
VDD
Iin
Id3
A
M3
Vout
M1
M2
VSS
Fig E.4 Schematic of a Wilson current mirror
83
APPENDIX F
Appendix F
Transmission Line Theory
The ideal wire has no resistance, no capacitance and no inductance, such a wire is not
physically realizable. Fig F.1 shows how an infinitesimal segment of a wire can be
modeled. R, L, G and C are given in terms of ohms/meter, henrys/meter,
siemens/meter and farads/meter.
Rdx
Ldx
Cdx
Gdx
Fig F.1 A model of an infinitesimal segment of a wire[17]
The differential equation of the current and voltage in the infinitesimal segment of the
transmission line in Fig. F.1 are
∂V
∂I
= − RI − L
∂t
∂x
(eq. F.1)
∂I
∂V
= −GV − C
∂t
∂x
(eq. F.2)
Differentiating eq. F.2 and substitute it into eq. F.1 gives
∂ 2V
∂V
∂ 2V
(
)
=
−
+
+
+
RGV
RC
LG
LC
∂t
∂x 2
∂t 2
84
(eq. F.3)
APPENDIX F
Lossless
The conductance of a transmission line is usually very small (G=0). A simplification
of eq. F.3 with (G=0) results in
∂ 2V
∂V
∂ 2V
= RC
+ LC 2
∂t
∂x 2
∂t
(eq. F.4)
For wires with large resistive loads such as on-chip wires, the inductance is usually
negligible. If the second term in eq. F.4 is ignored, the equation becomes similar to
the diffusion equation. However, most off-chip wires can be modeled as a lossless
wire. Assuming R=G=0 in eq. F.4 results in
∂ 2V
∂ 2V
= LC 2
∂x 2
∂t
(eq. F.5)
Eq. F.5 is very similar to the wave equation. A solution to eq F.5 for a wire of length
d, has the following solutions
A forward traveling wave with the equation:
x⎞
⎛
V f ( x, t ) = V ⎜ 0, t − ⎟
v⎠
⎝
(eq. F.6)
A reverse traveling wave with the equation:
d − x⎞
⎛
V r ( x, t ) = V ⎜ d , t −
⎟
v ⎠
⎝
(eq. F.7)
Where v is the speed of the wave.
v = L ⋅C
(eq. F.8)
However, real off-chip wires always have some losses and the signal behavior is most
accurately described by a combination of the diffusion and the wave equations.
85
APPENDIX F
Impedance of a Line
An expression for the input impedance of the transmission line in Fig. F.2 is
Z 0 = Rdx + Ldx +
1
(eq. F.9)
1
Cdx + Gdx +
Z0
where Z0 is the total input impedance.
Rdx
Ldx
Cdx
Z0
Gdx
Z0
Fig F.2 An infinite wire with the total impedance of Z0 [17]
Rearranging eq. F.9 gives
Z 0 (Cs + G ) − Z 0 (R + Ls )(Cs + G )dx − (R + Ls ) = 0
2
(eq. F.10)
Since dx is infinitesimal the term in the middle approaches zero and can be excluded.
Rearranging and excluding the middle term of eq. F.10 results in
⎛ R + Ls ⎞
Z0 = ⎜
⎟
⎝ G + Cs ⎠
0.5
(eq. F.11)
Thus, the wire impedance is independent of the length of the transmission line. If the
line is approximated with a lossless (LC) line, the impedance of the transmission line
is
Z0 =
L
C
86
(eq. F.12)
APPENDIX F
The impedance in a lossless wire is independent of frequency and the length of the
transmission line. From the perspective of the drivers, it is like driving a purely
resistive load. We can now derive the current traveling wave equations from equation
F.6, F.7 and F.12
If =
V f ( x, t )
Ir = −
(eq. F.13)
Z0
V r ( x, t )
Z0
(eq. F.14)
The negative sign because the current is by definition traveling in the positive xdirection.
Reflections
When a transmission line is of finite length, a consideration of what happens when a
traveling wave reaches the end of a transmission line must be taken. The transmission
line is always terminated in some way, ZT corresponds to the impedance associated
with the impedance of the termination.
If
2Vi(d,t)
Ir
Z0
+
-
ZT
IT
Fig F.3 A model of a transmission line of finite length
Vi is the incident wave, Z0 the characteristic impedance of the transmission line, and
ZT the impedance of the termination.
IT in Fig. F.3 is given by
IT =
2Vi
Z 0 + ZT
(eq. F.15)
where Vi is the first incident wave. From Fig F.3 we can also see that
I r = I f − IT =
87
2Vi
Vi
−
Z 0 Z 0 + ZT
(eq. F.16)
APPENDIX F
Rearranging eq. F.16 gives
Ir =
Vi
Z0
⎛ ZT − Z 0 ⎞
⎟⎟
⎜⎜
⎝ Z 0 + ZT ⎠
(eq. F.17)
If we rewrite this expression we have the Telegrapher’s equation. Where Γ is called
the reflection coefficient
Γ=
I r Vr Z 0 − Z T
=
=
I i Vi Z 0 + Z T
(eq. F.18)
The Telegrapher’s equation tells us that when ZT= Z0 (perfect match) the refection
coefficient is equal to zero. Thus, there is no reflected wave. Moreover, if ZT=∞ (open
circuit termination) then Γ=1 which implies that the reflected wave is equal to the
incident wave. Similarly, when Γ=-1 (ZT=0) (short circuit termination) the reflected
wave is equal to the incident but with opposite sign. Thus, they cancel each other out.
Multiple reflections
Fig F.4 Multiple reflections caused by termination mismatches
If the transmission line is not terminated properly in neither the far- nor the near-end,
multiple reflections occurs. Fig. F.4 illustrates this phenomenon, when both far- and
near-end is terminated to 500Ω. The delay in the wire is 2.5ns.
In theory it is enough with terminating one end of the transmission line. This has a
positive impact on the abortions of spurious reverse traveling waves at the source.
These reverse traveling waves can be the result of cross talk [19].
88