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Cubesat LAICE Photometer and Temperature Probe Integration Design Review David Schlais – Robbie Wankewycz – Jamie Barber TA: Kevin Bassett ECE 445 – Senior Design Group #21 October 2, 2014 1.0 Introduction 1.1 Statement of Purpose The LAICE Cubesat is a low-orbit satellite designed to help scientists study the coupling between lower and upper atmosphere. One area of interest is the study of gravity waves and how they transfer energy from low to high altitudes. These waves are detected by the payload sensors. The control board handles the data on the satellite. The objective of this project is to help design and develop the photometer payload control board so that the control board may collect, process, and transmit data received from photon counters with optical filters and temperature sensors. The board operates PMT sensors via power switching and monitors on-board components via temperature sensors. 1.2 Objectives 1.2.1 Goals Use FPGA to count number of photons received by photometer multiplier tubes (PMTs) Implement command/telemetry interface to spacecraft bus Utilize DC-DC conversion to step down unregulated 7.4V to regulated 5V Implement power switching for each PMT Monitor temperature of each PMT and optical filter 1.2.2 Functions Process specific commands from command and data handling system (C&DH) Process/count PMT pulses using VHDL code within FPGA Transmit data packets for the 11 temperature sensors and the 7 photon counters in response to commands 1.2.3 Benefits Simple, convenient tracking of on-board and atmospheric conditions Robust design; if one PMT fails the satellite will continue to operate 1.2.4 Features Temperature resolution of less than 1 ºC Individual power switches for each PMT PMT fault detection 2.0 Design 2.1 Block Diagrams 2.1.1 Signals Block Diagram Figure 1: Top LevelSignals Block Diagram 2.1.2 Power Block Diagram Figure 2: Top Level Power Block Diagram 2.2 Block Diagram Block Descriptions and Details 2.2.1 Data Collection And Transmission Unit This block is responsible for collecting input data from the temperature sensors and photon detectors, and be able to communicate that data using RS-422 protocol with the satellite. We will be using a Spartan 6 LX9, as an FPGA is a low-power way to process this data, create state machines needed for full functionality, and still maintain simplicity. The Spartan 6 has the I/O pins needed for this project. We will be using a Mojo v3 FPGA development board for prototyping, and place a Spartan 6 chip on a PCB in the final version. The Spartan 6 requires a 3.3V regulated power line from the power supply to operate. The FPGA is part of the Mojo development board, and will handle data manipulation and communication protocols through serial data transmission. The temperature sensors will output an analog signal representing temperature, which will go to an ADC before being sent to the FPGA. Although the signal from the PMTs (see 2.2.2) is also analog, it resembles a digital pulse, which can be used for the count/no-count detection needed without an ADC. The FPGA will be required to take data from the PMTs (which comes out as analog voltage pulses upon detecting a photon), and count the number of photons that came in since the last data request was received from the communication interface with the command and data handling board. The Spartan 6 FPGA has volatile memory, so the code must be loaded on boot-up by an additional flash memory chip. This flash memory must be programmable so that new VHDL code can be loaded into the FPGA. The flash memory contents will be programmed via an external laptop/desktop computer. We will use a JTAG interface to program the FPGA and flash memory. On bootup, the FPGA will program itself if there is a valid memory source connected. [1] (See Figure 3). The FPGA will also receive overlight condition (OLC) signals from each of the PMTs. If this signal is registered as voltage high for 50ms, 1 50𝑚𝑠 = 50𝑀𝐻𝑧 ∗ 𝑐𝑦𝑐𝑙𝑒𝑠 or in other words 2,500,000 cycles, then the FPGA will send a shutdown command to the power switching unit. Figure 3: JTAG Interface between Spartan6 and Xilinx Flash Memory Chip [2] The clock/oscillator will be responsible for keeping a steady clock signal for the FPGA to operate properly within the tolerable clock skew limits. 2.2.2 Photomultiplier Tubes (PMTs) and Optical Filters This module will consist of 7 photomultiplier tubes (PMTs) and 4 optical filters that will be mounted on the LAICE Cubesat. Each time a photon is detected, a PMT will typically emit a pulse. This pulse has a ~2V amplitude, a pulse duration of 10ns, and a pulse-pair resolution of 20ns. The PMTs will be driven by a regulated 5V power line. This module will also be connected to 7 power switches so that each PMT may be powered up and shut down individually. The PMTs and optical filters have already been purchased and are a part of our project. It is our group’s task to interface the PMTs with the FPGA. 2.2.5 Temperature Sensing The temperature sensing module is responsible for monitoring the temperature of the PMTs and the optical filter. Temperature will affect the behavior of the PMTs and optical filters. At high temperatures PMT’s are more susceptible to noise. And the optical filter’s bandpass is temperature-dependent. Monitoring the temperature sensitive components allows for science data to be properly calibrated on the ground during science data processing and analysis. Each temperature sensor will be driven by a regulated 3.3V power line. The sensors will communicate with a 16-channel, 12-bit ADC (AD7490) which will send a single digital signal to the FPGA to be processed. A PMT’s operating temperature is (5ºC - 40ºC). We will use a Resistance Temperature Detector (RTD) (a more robust alternative to the thermistor) to sense the temperature of each PMT and optical filter. The temperature sensors will be most accurate for the range (-50ºC 500ºC). Temperature is measured as a function of resistance. As the temperature goes up, the resistance increases. The U.S. Sensor we have chosen increments up or down about 4 ohms for every degree Celsius temperature change. The temperature sensor circuit will include a resistive network to further linearize the signal; a capacitor to filter out low frequency noise and a stable current generator circuit, to ensure an accurate measurement of the voltage drop over the RTD. Schematics Figure 4: Schematic of Current Generating Circuit for Thermistor In Figure 4, is a layout of one method of providing a steady reliable current to the RTD. This circuit design includes a feedback system utilizing 2 op-amps (AD295) that will ensure the current does not rise or fall below the chosen value. The excitation current chosen is 0.1mA. A detailed data sheet of a similar RTD from a different manufacturer recommended 0.1 to 0.3 mA for the measurement current [3]. Furthermore the current was chosen with the intent of providing a reasonable voltage drop across the RTD for a range of temperatures, as well as to minimize the effects of self-heating. The 1k Ohm platinum RTD chosen has an operating temperature range of -50 ºC-500ºC. and an accuracy of 0.15 ºC. RThermistor = RT (-50 ºC) =803.14Ω ± 0.99Ω RT (500ºC) =2.809kΩ ± 3.83Ω RT (0 ºC) =1kΩ ± 0.59Ω VA VA Vout1 0 R2 R1 VREF VA VA Vout 2 R3 R4 VA VA VoutA VoutB 100 A RREF With some algebraic manipulation, these equations eventually yield the fact that the voltage gain of OpAmp A can be independent of R1 and R2 given that R1 = R2. In which case, OpAmp A yields a gain of two. That results turn out to be the same for the unity gain OpAmp B and resistors R3 and R4 [4]. Signal Conditioning Prior to ADC It’s very important that the signal that arrives at the ADC is as clean as possible. Any variation in voltage will result in errors in the signal processing and ultimately loss of data and accuracy. A 16-channel, 12-bit ADC (AD7490) was chosen for this circuit for its price and input range. To maximize ADC performance the output voltage range of the signal from the RTD needs to vary over the input voltage range for the ADC [5]. VIN1 = R(500ºC)* 100uA = 208.9mV VIN2= R(-50 ºC)* 100uA = 0.8mV VIN1 .8mV VIN2 208.9mV VOUT1 0V VOUT2 2.5V Gain Needed from Op-Amp C, from the RTD to the ADC: 2.5V 0V 12.46 280.9mV .8mV Furthermore, through basic circuit analysis the following equations may be derived from Figure 2: VR 22 VR 22 VREF VRTDin VR 22 R22 R11 RG Through extensive algebraic manipulation, one can find an equation for VoutC that depends VRTDin VoutC VRTDin VR 22 on VRTDin and VREF. In 2.) order to characterize the RF RG desired OpAmp behavior, we used the gain found earlier as the slope and solved the offset using points from the chart above. The OpAmp can be described by: Vout 12.46Vin 1 [5]. 1.) ADC Processing We will be using a successive approximation ADC with 16 input channels and one 12-bit output channel. One of the requirements is to satisfy a 0.5 ºC ± .1 ºC specification set based on what the sponsor explained he needed and the available resources. This resolution can be achieved by a 12-bit ADC which is shown in the following: V log( RTD _ range ) Vresolution Nbits log(2) VRTD_range= The difference in the voltage drop across the RTD at its highest temperature and its lowest temperature. Vresolution= The desired ºC resolution in terms of mV. Nbits= The number of bits required in order to achieve Vresolution And therefore the desired ºC resolution: log( 280.1mV ) .4mV 9.45bits log(2) In an ideal case, the temperature analog signal would increase in the same increments as the digital signal (or discrete values) to which it’s being compared. This set up would reduce errors and maintain useful resolution in the circuit [6]. This only gives us 1 ºC resolution. We reiterate the process until we find a practical solution and compromise, for .33 ºC resolution: log( 280.1mV ) .133mV 11.03 bits log(2) Using .33 ºC instead of .1 ºC or smaller, allows room for errors. Errors will play a large role in degrading the accuracy of the RTD reading. The amount of mV that will be assigned per ADC bit can be found using the following: 2.5V .61mV / value (212 1) values The resolution for the ADC will be about 0.6 mV/bit [6]. In the Op-Amp chosen (AD295) there is a typical offset voltage or 30 µV and a maximum offset of 300 µV. These offsets will result in less than 1-2 bits of error. Variances in the Op-Amp minimum and maximum output, as well as the combined variance in resistance due to its tolerance can result in much larger errors. This is why signal conditioning is important, in addition to the potentiometers, which will help offset some of the resistor tolerance error. Tolerance Analysis We are interested in knowing how many bits can be incorrect and still maintain an accuracy of ±1 ºC. We have decided on a resolution of 0.33 ºC so the number of mV per bit is: 2.5V 1.22mV / value 11 (2 1) values 1 ºC according to the U.S Sensor data sheet is close to 4 Ohms, and therefore translates into 0.4mV per degree Celsius. 12 bits to describe each 1.22mV increment in voltage drop from the RTD and 16-bit packets will be sent from the FPGA, while only 11 bits are needed to represent the entire range. Therefore 32 values go unused and 5 bits may be lost, through voltage offset, resistance tolerance, or any other type of error that would alter the voltage measurement, and the reading should still be useful. We know the minimum amount of bits we can use to meet the requirement of less that one degree resolution: log( 280.1mV ) .4mV 9.45bits log(2) 2.2.4 DC/DC converter This circuit will take in the unregulated 7.4v battery output, which can swing between 6 and 9v in the worst cases, and convert it to 5v DC. This 5v voltage will be used to power the 7 photomultiplier tubes which require 5 volts each. The circuit will be a switching buck converter. The chip we will use for this is the LT3971[7] made by Linear Technologies and was chosen because it meets all of our requirements, has thorough documentation, and is relatively affordable. We chose the switching regulator because although there is a bit more noise than a linear regulator, it has a higher efficiency (between 85% and 90% vs around 67% for an LM317 or other similar linear regulator). [8] The LT3971 has an adjustable output voltage that is set by a resistor network attached to the feedback pin (FB). The equation for determining the resistor values is 𝑉𝑜𝑢𝑡 𝑅1 = 𝑅2 ( − 1) 1.19𝑉 where the 1.19V is an internal reference voltage and R1 and R2 are arranged as shown in Figure 6. Figure 6. Voltage-setting resistor network The higher the resistor values the better the accuracy will be because the tolerance percentage of the resistors will have less effect on such large values. Still, the resistors should be selected to be 1% tolerance. Solving for R1 and R2 using Vout = 5V and choosing R1 to be large (~1MΩ), we can calculate the ideal R2 value. 𝑅1 1𝑒6 𝑅2 = 𝑉𝑜𝑢𝑡 = 5 = 312335.95 ~312𝑘 [9] ( 1.19 −1) 1.19 −1 Using R2 = 312kΩ and R1 = 1MΩ, we can calculate what the high and low ends of the voltage tolerance are knowing that the resistors will have a 1% tolerance. 𝑅1 ∗ 1.01 + 1) ∗ 1.19 = 5.0812V 𝑅2 ∗ .99 𝑅1 ∗ .99 =( + 1) ∗ 1.19 = 4.9286V 𝑅2 ∗ 1.01 𝑉𝑜𝑢𝑡𝐻 = ( 𝑉𝑜𝑢𝑡𝐿 We then must take into account the output ripple which is at the worst case 15mVp-p. 𝑉𝑜𝑢𝑡𝐻 = 5.0812V + 15mV = 5.0887𝑉 2 𝑉𝑜𝑢𝑡𝐿 = 4.9286V − 15mV = 4.9211𝑉 2 These extremes falls within the range of operation of the Hamamatsu H10682 PMTs we will be using, which is 4.75v to 5.25v. Other than the resistor network, the switching regulator requires a few more components to fine tune its functionality. First, a few capacitors are needed: an input capacitor, output capacitor, boost capacitor, and phase lead capacitor. The input capacitor helps to minimize input voltage ripple caused by the pulsed nature of how the input is supplied. Through trial and error the capacitor can be found to be ideally in the 4.7𝜇F - 10𝜇𝐹 range. The output capacitor serves a similar purpose in minimizing the ripple of the output but it also, in conjunction with the inductor, turns the square wave output into a DC signal. The boost resistor makes sure the voltage on the boost pin is higher than the supply voltage which will ensure that the switching transistor is fully saturated. The resistor Rt is used to select the switching frequency and the switching frequency has a large effect on efficiency. What to aim for is to maximize the time between pulses while still keeping the pulse width and the frequency of pulses reasonable. Figure 7. DC/DC Regulation circuit 2.2.5 Power Switching There will be a current limiter preceding each photomultiplier tube which will monitor the voltage and current that goes to each photomultiplier tube and break the circuit if the current surges above 40mA. There will be one of these for each photomultiplier tube. Each current limiter will also be able to be reset electronically by a logic signal sent to the chip. We will use Texas Instrument’s TPS22946 Selectable Current Limit Load Switch [10]. This device was chosen because it supports a trip current as low as 40mA, has an output flag signal for overcurrent, and an enable pin. The input supply voltage is between 1.62V and 5.5V. We will use the ENABLE pin to turn the PMTs on or off with an FPGA control signal. This signal will be determined by the overcurrent flag output from the TPS22946 and the overlight output flag from the PMT. The overcurrent flag (OC) is inverted and OR’d with the overlight condition to determine if the device should be shut down. Figure 8. Shutdown logic There is an input and output capacitor to help with ripple on both ends and there is also a resistor pulling up the OC output to Vin. The device has a selectable current limit which is selected using the CL pin. In this case we want the limit to be 30mA, which is designated by leaving the pin hanging. Figure 9. Power Switching circuit Figure 10. Full schematic of power system 2.2.6 Software/Program Descriptions Figure 11: Temperature VHDL Program Flowchart 2.2.6.1 Temperature Data Handling The temperature program is responsible for converting signals from the temperature sensors and ADCs into temperatures, and sending the temperatures to the serial communications unit. The “digital to temp conversion” block in Figure 11 takes the digital representation of the RTD voltage and calculates the corresponding temperature. This value is stored into 16 bit registers for each corresponding sensor. All 11 registers are combined into a 176 bit packet that is connected to the serial communications unit (see Figure 11). 2.2.6.2 Photon Counting The photon counting program is responsible for taking 7 separate photometer readings, and sending to the serial communications unit how many voltage pulses have occurred for each photometer since the last data request. The output of the photometers roughly output 2V pulses 10ns in length. Upon a rising edge of a pulse, the flag register is set for the corresponding photometer (see Figure 12). On each FPGA clock cycle, if the flag is set for a photometer, the corresponding 24-bit count is incremented. The seven 24-bit counts are combined into a 168 bit packet that is connected to the serial communications unit (see Figure 12). Figure 12: Photon Counting VHDL Program Flowchart 2.2.6.3 Serial Communication Program The serial communication program is responsible for sending and receiving data via RS422 protocol. This program must interpret serial data sent from the satellite bus. If the data received by the program is a “request_data” packet, this program will serially transmit the 168bit photometer data packet (see Figure 12). If the data received by the program is a “request_houskeeping” packet, this program will serially transmit the 176-bit temperature data packet (see Figure 11). The other two commands request to turn off and turn on the photometers. The shutdown lines for each photometer is sent to the respective power switching circuits. Note that the satellite block is external from this project (see Figure 13). Figure 13: Serial Communication VHDL Program Flowchart *Note: Blocks below dashed line are external from this project 3.0 Simulations and Schematics Simulations DC/DC Converter Simulating the DC/DC conversion circuit with normal operating conditions gave expected and satisfactory results. A constant input of 7.4V produced a steady output of 5.0V after about 0.7ms. Figure 14. Simulation of normal conditions for DC/DC conversion Simulating the same circuit under extreme conditions (Vin fluctuating between 6 and 9V), also gave satisfactory results. The output voltage still settled at a steady 5V (see Figure 15). Figure 15. Simulation of extreme input conditions for DC/DC conversion Looking at a zoomed in version of Figure 15 (Figure 16), it is clear that the voltage output is less stable because of the fluctuating input but the voltage is still well within the desired operating range. The maximum is on the first rise and that is still only about 5.15V. Figure 16. Zoomed in look at Vout during fluctuating input Figure 17: Pinout and Schematic of FPGA and FPGA required components Modified, but based off of Mojo v3 Dev Board [11] 4.0 Requirements and Verification Requirements Verification FPGA Functional FPGA integrated into PCB, and reprogrammable (must be programmed on PCB, not development board. The rest of the requirements can be tested on FPGA dev board or PCB to demonstrate working VHDL code) FPGA can detect analog signal similar to that of a pulse from photometer. Accurately count number of counts (within .1%) at frequencies up to 10MHz Detect Housekeeping, Data collect, science mode, and shutdown signals Convert digital inputs to meaningful temperature Ability to serially send out values held in temperature and photon count registers. Program and reprogram the FPGA/Flash chip on PCB. This demonstrates both chips powered up and working. Hook up function generator to simulate pulse width (10-20ns width). Show the FPGA reads a non-zero count value (read register value). Given pulses created from function generator at 10MHz, read count values from code at 1 second intervals. Should be 10,000,000 +/10,000 Turn separate pins to voltage high when each request is detected. Measure with Voltmeter. Should read above 2V for respective pins. Hook input lines to all voltage high, all voltage ground, and 3-4 predetermined in-between values to see if converted to the correct corresponding temperatures (exact values to be determined after RTDs purchased and calibrated) Pre-load temperature and photon count registers with values, and demonstrate the data is sent out serially (0101010101010101) -16 bits (temperatures) (101010101010101010101010) -24 bits (photon count) Frequency Drift under 6% Hook up oscillator pins to network analyzer, see frequency of oscillator and use “frequency drift” function. For 50MHz oscillator, should be less than 3MHz/sec. Temperature Probes There should be a steady excitation current at 0.1mA, to ensure precise RTD readings. The range of output voltage from the RTD should match as closely as possible (within 0.8mV) to the range of input voltage of the ADC Measure current with an ammeter after the resistor RREF, and verify excitation current is within 20 uA of 0.1 mA Measure the gain of the op-amp that connects to the ADC and verify that the op-amp has a gain of 10.95dB within 2 dB RTD needs to behave linearly within the context of Verify the RTD behaves linearly, by measuring the the circuit RTD and ADC should provide 0.4 degree celcius(+/- 0.3 degree celcius) resolution voltage at the output of the RTD, while using hot and cold plates. Voltage drop across the RTD needs to be within 3mV of expected. Test software and hardware together using a power supply and inject voltage into the RTD's spot (remove the RTD to do so) in the circuit to simulate temperature, or use hot plates/cold plates DC/DC Conversion Must step down an unregulated input of 6-9V to a regulated 5V with a 5% tolerance Must be able to hold the 5V regulation requirements for loads 10 - 300mA Must make output drop to 0v if 3.3v power line drops to 0v Power Switching If the output current is greater than 40mA, the switching circuit must be powered down to an output current of 0.1uA (maximum) If an overlight condition signal is recieved from the PMT connected to the switching circuit then a signal between 2.0 and 4.1V must be sent to the FPGA for shutdown request. If an overcurrent condition is met in the switching circuit then a signal between 2.0 and 4.1V must be sent to the FPGA for shutdown request. A signal line from the FPGA to each of the 7 switching circuits must be able to shut down the switching circuit to an output current of 0.1uA maximum. The signal line must be <0.6V for the device to be shut down. If there is no overcurrent condition and no overlight condition, the signal to the FPGA must be 0.55V max. Sweep the input of the regulator circuit from 6 to 9 volts and verify on simulations and a voltmeter that the output is between 4.75 and 5.25v Hook the circuit up to an electronic load to simulate a load and sweep the current from 10mA to 300mA and verify that the voltage stays between 4.75v and 5.25v Connect a 3.3v voltage source to the triggering pin while the device is operating correctly, drop the 3.3v to zero, and measure that the output becomes 0v Attach a load that draws 80mA in line with an ammeter and make sure the output current is 0.1uA or less. Simulate the overlight signal using a function generator and measure the shutdown signal output on a multimeter to verify it is between 2.0 and 4.1V Simulate the overcurrent condition with a function generator and measure the shutdown signal output on a multimeter to verify it is between 2.0 and 4.1V Simulate a signal of 1.4 to 5.5V going into the 'ON' pin and dropping to 0.4V with a load attached to the switching circuit and verify with an ammeter that the output current is 0.1uA or less. Simulate the off-state condition signals with a signal generator and measure the output voltage of the logic circuit to verify it is <=0.55V 4.1 Tolerance The FPGA will need to be able to count the number of pulses from the PMT correctly with a frequency of no less than 10MHz. In other words, the FPGA must be able to count distinct pulses that are greater than or equal to 100ns apart. Counts recorded should be within 0.1% of the number of pulses generated by the PMTs. The DSP slices can operate at a maximum of 340MHz on the Spartan-6. Depending how efficient the VHDL code runs (how many clock cycles are needed between counts added following voltage pulses), the acceptable clock skew/drift will change. Loop operating frequency [1/(sec*cycles)] * cycles = Clock frequency needed (1/sec) If it takes 30 clock cycles in the loop, the minimum clock rate needed is 30*10MHz=300 MHz. So if the clock was centered at 320MHz, a drift of 6% above the frequency would still be under 340MHz DSP slicing maximum, while a drift 6% below the frequency would still be over the 300MHz minimum code requirement. Even with a clock skew/drift of 6%, the signal processing should still be fast enough to detect 10MHz pulses on the 7 PMT channels. 4.2 Safety Statement The safety concerns of our project fall mostly on us, the designers, seeing as there is no intended end-user for the device which will be orbiting in the lower atmosphere. During the prototyping phase, we will be soldering surface-mount components to our PCB. This creates potential fire and burn hazards, so we will take extra precautions for that. During testing, we will be using expensive lab equipment, using ESD ground bracelets if/when necessary. Concerns to be aware about mostly come from the temperature sensor testing. We will be testing RTDs on some sort of heating surface, which may pose a fire hazard. The proper safety precautions will be taken when using the device. 4.3 Ethics The following ethics guidelines were taken from the IEEE code of ethics and explained how our group is compliant with the guidelines. [12] 3) to be honest and realistic in stating claims or estimates based on available data; We comply with this code from IEEE by being up-front and true with UIUC’s cubesat team about concerns and possible modes of failure/inaccurate data when known. Since our data collection will be used by the University of Illinois and Virginia Tech in research findings and discoveries, our data measurements are critical. Our precision and accuracy in data collection will be clearly discussed with the team so that our data tolerance is known by all. This way, all conclusions made by UIUC and VT through our measurements will be able to take into account the error known by us in our measurements." 7. to seek, accept, and offer honest criticism of technical work, to acknowledge and correct errors, and to credit properly the contributions of others; In our project especially, one in which we are working in conjunction with a campus research group, and in which we are working on one part of a bigger project, honest criticism is necessary to facilitate progress. Seeking and accepting and offering this criticism will allow everyone to give their say on what they think would work from the perspective of another part of the project. While we are the only ones actually developing the payload hardware, many different people have given their input and guided our project in a certain direction, including the students who started the project in years earlier. 4.4 Schedule Week Jamie Preliminary temp sensor design, ask for sampes from company; complete schematic w/o ADC; find ways to model IC temp sensor in ADS; Choose two appropriate ADC 9/22/2014 options 9/29/2014 (Design Rvw) Finalize temperature circuits; Finalize simulation results; Finalize components needed; Complete plan for how ADC needs to be interfaced with analog temp sensor David Robbie Preliminary software flowchart for photon counters. FPGA choice (Xilinx vs Altera). Finding all components needed. Oscillator, flash chip, ADC, FPGA, etc based on Mojo PCB layout open_source Choose a device to work as the circuit breaker (or determine if wee need to make one), come up with a few designs for protection circuit, determine if voltage regulator chip will suffice. Make simulation of DC/DC converter Finalize ADC choice -- work with Jamie to decide if this is done with ADC from dev board or external. Counter FPGA logic. First draft layout of FPGA, flash chip, etc. Make changes based on design review Finalize circuit breaker, dc/dc conversion, and protection circuit, make schematics and have ready for design review, simulate protection circuit and circuit breaker Preliminary interface ADC Build up schematics on ideas, 1st draft of photon breadboard, test counting software. Integrate schematics on breadboard ADC with FPGA. Get using function generator; accurate corresponding 10/6/2014 Finalize ADC interface readings Preliminary software flowchart for power switching, buy components for buidling circuits (given that the design was OK'd in the design review), build prototype dc/dc conv. Debug breadboard, Preliminary PCB layout, tolerance analysis of 10/13/2014 temperature sensors Final draft Photon counting software operating fully with function generator (may or build and test breadboard may not meet 10MHz design protection circuit, test circuit spec, but get it working) breaker, Initial PCB layout Test temperature sensor circuit on cold/hot plate; Continue PCB layout 10/20/2014 work; Make sure photon counter working fully at 10MHz spec. First draft of communication protocol. Send data via bench test of ADC, test ADC respective commands to and temp sensor working FPGA together 10/27/2014 Finalize PCB layout Final draft communication protocol FPGA software Finalize PCB layout Have working code to Integrate power switching, convert analog values from FPGA, into temperature temperature sensors to 11/3/2014 sensor design "useful" data Tolerance analysis of DC/DC converter, protection circuit, and circuit breaker Debugging integrated design, soldering, building Soldering, building circuits, 11/10/2014 up PCB wiring up PCB Preliminary demonstration of power circuits Bring together sensor circuitry for preliminary Combine power aspects with 11/17/2014 demonstration, debugging Full functional testing of PCB FPGA and sensors 11/24/2014 Prepare temperature (Thanksgiving) demonstration Prepare software demonstration Prepare power demonstration 12/1/2014 (Demo/Pres) Prepare explanation and Prepare debugging and Prepare development part of introduction part of testing part of presentation presentation presentation 12/8/2014 (Pres) Finalize sensor part of final paper Finalize FPGA part of final paper Finalize power part of final paper 4.5 Parts Parts Name Desc Quant Cost Total XC6SLX9-3TQG144I Spartan 6 FPGA 1 19.82 19.82 XCF025VOG20C Xilinx Platform Flash Chip 1 4.25 4.25 LD1117S12CTR 1.2V .8A Voltage Reg for FPGA 1 0.7 0.7 NCP1117ST25T3G 2.5V 1A Voltage Reg for FPGA 1 0.49 0.49 353011779-1-ND 50MHz Clock -- -40 to 85 degrees C Silicon oscillator 1 1.28 1.28 LT3971 MSOP Step-down Switching Regulator 1 4.07 4.07 Passives Various resistors, capacitors, inductors 1 20 20 TPS22946 30mA Current Limit Load Switch 7 1.16 8.12 DFLS220L Catch diode 1 0.81 0.81 SN74LV32 Quad 2-input positive-OR gates 2 0.41 0.82 SN7404 Hex Inverter 2 1.91 3.82 PPG102A1 US Sensor Platinum RTD AD7490 OP295 11 5.61 61.71 12-bit ADC 2 7.00 14.00 Op-AMP 3 2.64 7.92 0 Total 147.81 5.0 Labor Name Jamie Barber Robbie Wankewycz David Schlais Total Wage $35.00 $35.00 $35.00 Hours 125 125 125 Total $4,375.00 $4,375.00 $4,375.00 $13,125 6.0 References [1] "Configuration for Spartan-6 FPGA." Spartan-6 FPGA. Xilinx, n.d. Web. 2 Oct. 2014. <http://www.xilinx.com/products/design_resources/config_sol/s6/config_s6.htm>. [2]"Spartan-6 Configuration Guide." S6 Family Specifications. Xilinx, n.d. Web. 25 Sept. 2014. <http://www.xilinx.com/support/documentation/user_guides/ug380.pdf>. [3] “700 series platinum RTDs datasheet” Honeywell. Web, 2 Oct 2014. <http://sensing.honeywell.com/700%20series_009018-3-en_final_21apr10.pdf> [4] Baker, Bonnie. “Precision Temperature-Sensing With RTD Circuits” Microchip Technology Inc. Web. 2 Oct 2014. <http://www.ottomat.hu/Kapcsrajzok/aramgenerator4.pdf> [5] Mancini, Ron. "Sensor to ADC- Analog Interface Design." Texas Instruments. Web. 2 Oct. 2014. <http://www.ti.com/lit/an/slyt173/slyt173.pdf>. [6] Katupitiya, Jayantha, and Kim Bentley. Interfacing with C Programming Real-world Applications. Berlin: Springer, 2006. Print. [7] "LT3971 2MHz Step-Down Regulator," Linear Technology, 2009. [Online]. Avaliable: http://cds.linear.com/docs/en/datasheet/3971fd.pdf [8] Keeping, Steven. "Understanding the Advantages and Disadvantages of Linear Regulators." DigiKey Electronics. N.p., n.d. Web. 2 Oct. 2014. <http://www.digikey.com/en/articles/techzone/2012/may/understanding-the-advantages-anddisadvantages-of-linear-regulators>. [9]McClure, Linden. "Resistor and Capacitor Standards." UC Boulder Department of ECEE. University of Colorado Boulder, n.d. Web. 1 Oct. 2014. <http://ecee.colorado.edu/~mcclurel/resistorsandcaps.pdf> [10]"TPS22946 Data Sheet," Texas Instruments, February 2010. [Online]. Available: http://www.ti.com/lit/ds/symlink/tps22946.pdf [11] "Mojo v3 FPGA Development Board." - DEV-11953. N.p., n.d. Web. 2 Oct. 2014. <https://www.sparkfun.com/products/11953>. [12] "IEEE IEEE Code of Ethics." IEEE. N.p., n.d. Web. 1 Oct. 2014. <http://www.ieee.org/about/corporate/governance/p7-8.html>. 7.0 Appendix 1) Graph of constant current op-amp circuit.