Download Macro-model Based SPICE Simulation of DC/DC Switching Regulators C. Bunlaksananusorn

Macro-model Based SPICE Simulation of DC/DC
Switching Regulators
C. Bunlaksananusorn
Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok 10520, Thailand
Email: [email protected]
ABSTRACT
A macro-model is a simplified model that emulates
functional characteristics of a device or circuit, and
widely used in system-level simulation. In this paper,
macro-model based SPICE simulation of DC/DC
switching regulators is presented. Macro-models of a
power switch and Pulse Width Modulation (PWM)
control circuit are described. Two simulation examples
are given to demonstrate the capability of these macromodels in simulating switching regulator performances.
Keywords: DC/DC switching regulators, Simulation
1. INTRODUCTION
Computer simulation plays an important role in
modern design of DC/DC switching regulators. It allows a
regulator’s performance to be evaluated prior to
construction of a prototype; hence design flaws, if any,
can be detected and corrected at the early stages in the
design process, reducing time-to-market and saving costs.
The switching regulator performance can be simulated on
an average or a cycle-by-cycle basis [1]. Though the
average simulation is known to be faster, the advantage of
the cycle-by-cycle simulation nevertheless is that it yields
the simulated waveforms contain a switching ripple,
resembling to those found in the real converter. The ability
to predict the switching ripple and ringing of the output
voltage is crucial in design of power supplies for modern
high speed data processing loads (e.g. microprocessors),
which demand tight voltage tolerance from the power
supplies [2].
Simulation time of the cycle-by-cycle simulation can
be reduced considerably by using a macro-model of a
device or circuit, instead of the detailed one. The macromodel is a simple model that emulates functional
characteristics of a device or circuit [3]; other secondary
effects are often ignored. It is widely used in system-level
simulation to evaluate overall system performances. In the
case of switching regulators, the macro-model can
effectively simulate both steady state performance such as
an output voltage and inductor current ripples, and
transient performance such as an output voltage transient
response due to an input voltage and/or output current
change. These simulations provide an efficient mean to
check a primary design without having to resort to breadboarding the circuit. Only until simulation shows a
satisfactory result, the designer then can move on to build
a prototype with confidence that no major design error has
been overlooked. In this paper, macro-model-based SPICE
simulation of a DC/DC switching regulator is presented.
2. MACRO-MODEL BASED SIMULATION
A buck switching regulator is shown in Fig. 1. The
power MOSFET and diode conduct alternately, converting
the DC input voltage, Vs, into the lower DC output
voltage, Vo. There are two operating modes concerning
the inductor current, iL. It could be continuous at all time,
namely Continuous Conduction Mode (CCM), or fallen to
zero at some points in a switching cycle, namely
Discontinuous Conduction Mode (DCM). Vo is regulated
by controlling the duty cycle of the power MOSFET. A
control circuit consists of an error amplifier and voltage
comparator. The error amplifier amplifies the difference
between a reference voltage, Vref, and a sensed output
voltage, V’o. The resulting control voltage, Vc, is then
compared with a fixed frequency sawtooth voltage, Vsaw,
generating a pulse-width modulated voltage, Vd, to drive
the power MOSFET to maintain the constant output
voltage.
In macro-model based SPICE simulation, the power
MOSFET, error amplifier, and voltage comparator in Fig.
1 will be replaced by their respective macro-models
described below, and the diode by its ideal model readily
available in SPICE.
L
iL
Vs
+
C
Vo
-
Error Amplifier
Vc
-
Vd
+
-
Comparator
Vsaw
V'o
+
Vref
Fig. 1: Buck switching regulator
2.1 Macro-model of a power MOSFET
The power MOSFET is emulated by an on/off switch,
which has a macro-model shown in Fig. 2 [4]. The
resistance across terminals A-B is switched between zero
and high-value controlled by an external voltage at node C.
E1=V1
A
- +
Vc
+
C
+
Rd
V1
-
+
Rin
+
V
Vref
-
Rin
Re
Vin
V'o
Eg
Rc
This can be explained as follows. The equivalent current
flowing through terminal A-B is
(1)
By assigning the controlled source E1 equal to V1, the
equivalent voltage at terminal A-B is
Veq = E g .
D2
Vcmin
Vcmax
(a)
Fig. 2: Macro-model of power MOSFET
V1 V − E g
=
.
Rd
Rd
D1
Gc=(Vref -V'o)
B
I eq =
Ce
(2)
Vd
Vc
Rin
Vsaw
+
-
Cc
D1
D2
Vdmin
Vdmax
Ed=106(Vc-Vsaw)
(b)
Fig. 3: Macro-models of (a) error amplifier (b) voltage
comparator
From equations (1) and (2), the equivalent resistance across 2.3 Macro-model of a voltage comparator
terminal A-B equals
A macro-model of the voltage comparator is shown in
Fig. 3(b). The voltage across Rin, which represents the
V
E R
difference between a control voltage, Vc, and a sawtooth
R eq = eq = g d .
(3) voltage, V , is amplified by the high-gain (106) voltage
saw
I eq
V − Eg
controlled voltage source Ed. The resulting large positive
Letting the controlled source Eg be equal to V(1-Vin), Req or negative voltage, depending on whether Vc is greater or
smaller than Vsaw, is clamped to one and zero respectively
becomes
by a voltage clamp circuit. Rc and Cc are a very small
resistor and capacitor added only to aid simulation
(1 − Vin )R d
(4) convergence and do not affect the circuit function. Thus,
R eq =
.
Vin
Vd is a unit pulse signal whose frequency is determined by
the frequency of Vsaw. Vd is used to drive the power
It can be seen from equation (4) that when Vin is a unit
MOSFET macro-model in Fig. 2.
pulse signal, Req is switched between zero and a very high
value. In the simulation, Vin is taken from the output of a
3. SIMULATION RESULTS
voltage comparator described in Section 2.3.
To demonstrate the capability of macro-model based
simulation, two simulation examples are given. The first
2.2 Macro-model of an error amplifier
example deals with simulation of a prototype buck
A macro-model of the error amplifier is shown in Fig.
regulator, where simulated waveforms are compared with
3(a). The current source Ge, which is controlled by the
their experimental counterparts. The objective of this
voltage difference between a reference voltage, Vref, and a
example is to validate accuracy and capability of the
sensed output voltage, Vo’, together with Re define the
presented macro-models. In the second example, the
error amplifier function
application of the macro-models to simulate a power
supply module for Intel Pentium microprocessors is
'
(5)
Vc = R e (Vref -Vo )
illustrated.
where Re is the error amplifier’s open-loop gain. The error
amplifier’s cut-off frequency is determined from the
values of Ce and Re
fe =
1
.
2 π R e Ce
(6)
An excursion of the control voltage, Vc, is limited to
between Vcmax and Vcmin by a voltage clamp circuit
consisting of D1, D2, Vcmin, and Vcmax.
3.1 Simulation of a prototype buck regulator
A prototype buck regulator depicted in Fig. 4(a) has
the following specifications: an input voltage (Vs) of 20V
to 25V, an output voltage (Vo) of 5V, an output current (Io)
of 1A to 10A, and a switching frequency (fs) of 100kHz.
The UC3825 PWM control IC [5] is used as a control
circuit. This IC integrates inside it an error amplifier,
voltage comparator, fixed reference voltage, and other
essential circuitry, with a switching frequency
programmed by a resistor and capacitor connected at pins
55µH
IRF640
VS
0.095Ω
MBR1645
20-25V
5Ω
200µF
3.3µF
10Ω
1N4148
1kΩ
15V
3.3µF
0.1µF
R1
R2
R3
R4
1kΩ
C2
1kΩ
UC3825
1 INV
VREF 16
2 NINV
VCC 15
3 E/A Out
10µF
0.1µF
+15V
Out B 14
VC 13
4 CLK
Pwr Gnd 12
5 RT
4.7nF
10kΩ
0.1µF
25
10µF
0.1µF 10µF
Out A 11
6 CT
7 Ramp
20
Gnd 10
8 Soft Start
ILIM/SD 9
Vo (V) and iL (A)
C1
(a)
rL = 0.3Ω
iL
VS
2025V
rC = 0.095Ω
C = 200µF
10
Vo
5
+
R=
0.5 − 5Ω Vo
-
R 2 = 500kΩ
R 4 = 560Ω
C2 = 0.22µF
+
iL
0
0
0.5
1
Time (ms)
1.5
2
Fig. 5: Simulated waveforms of Vo and iL from the model
in Fig. 4(b)
C1 = 0.22µF
5.2
+
2.8V
1V
15
L = 55µH
R 2 = 560Ω
R 1 = 120Ω
5V
5.1
Vo (V)
15V
start to 2ms, for Vs = 22V and Ro = 2.5Ω. The simulation
time taken is about 1.3s. It can be seen that Vo and iL reach
the steady state values of 5V and 2A respectively after
approximately 0.8ms. The short interval, where iL became
discontinuous, can also be noticed in the figure. Fig. 6
depicts the magnified steady-state portion of the
waveforms in Fig. 5. The output voltage ripple (∆Vo) and
inductor current ripple (∆iL) are less than 0.1V and 1A
respectively. These results agree with the experimental
results measured from the prototype regulator shown in
Fig. 7. Compared with their experimental counterparts, the
simulated results are noise-free because parasitics in the
regulator’s power circuit, which is responsible for
switching noises, have not been modeled.
Vo=5V
4.8
0.95
f=100kHz
5 and 6 respectively. The error amplifier is accessible at
pins 1 (an inverting input), 2 (a non-inverting input), and 3
(an output). The feedback compensation circuit, consisting
of R1, R2, R3, R4, C1, and C2, connected around the error
amplifier helps stabilize and enhance output performance
of the regulator. The PWM output signal is available at pin
11 of the IC, which drives the power MOSFET through a
standard drive circuit. The pulse transformer is
incorporated into the drive circuit to isolate the
MOSFET’s source pin from the power circuit’s ground.
Fig. 4(b) shows a schematic macro-model of the
system in Fig. 4(a). The error amplifier inside UC3825 has
an open-loop gain of about 95dB and a cut-off frequency
of about 90Hz. From these values, Re and Ce of the macromodel in Fig. 3(a) are found to be 56kΩ and 30nF
respectively. The regulator model in Fig. 4(b) is simulated
by SPICE, running on a Pentium III, Personal Computer
(PC). Fig. 5 shows simulated waveforms of Vo and iL from
0.97
0.99
1.01
1.03
1.05
0.97
0.99
1.01
1.03
1.05
Time (ms)
3
(b)
2.5
iL (A)
Fig. 4: (a) Prototype Buck regulator (b) Simulation
model
5
4.9
2
1.5
1
0.95
Time (ms)
Fig. 6: Simulated steady-state waveforms of Vo and iL
Fig. 7: Experimental steady-state waveforms of Vo (top
trace: 200mV/div) and iL (bottom trace: 1A/div)
3.2 Simulation of a power supply module for Intel
Pentium processors
A power supply module for Intel Pentium
microprocessors [2] is shown in Fig. 8. It is a buck
regulator that converts a 5V input voltage from the frontend converter to a 1.8V output voltage supplying the
processor. The regulator operates at a switching
frequency of 300kHz and is capable of delivering an
output current up to 20A. Linterc is an inductance of a track
connecting the converter’s output to the processor’s
power supply input. Cdecoup is a decoupling capacitor
inserted across the Vcc and GND pins of the processor to
reduce an output voltage ringing due to Linterc, during
transient. The processor’s supply voltage (VL) is tightly
regulated within ±5% of the nominal value, or between
+1.89V and 1.71V, throughout the operating current (iL)
range. The error amplifier is compensated to yield a
system crossover frequency of 30kHz.
Fig. 9 shows a transient waveform of VL, when the
processor draws a step current of 15A (i.e. from 5A to
20A), simulated by SPICE, using the presented macromodels. The simulation time is about 5.5s. It can be seen
that VL is maintained well within the regulation band. The
output voltage spike and ringing caused by Linterc can still
be noticed, though its severity has been lessen by Cdecoup.
This result is in close agreement with that presented in
[2].
1.92µH
Linterc
2nH
2m Ω
5V
VL
iL
Cdecoup
2.5mF
100µF
6.2pF
0.94nF 170kΩ
Comparator
E/A
+
+
-
1.9nF
2.6k Ω
10k Ω
1.8V
1.8V
0V
Fig. 8: Power supply for Intel Pentium processors
1.82
1.80
VL (V)
1.78
1.76
Lower regulation limit, -5%
1.74
1.72
1.70
25
IL (A)
20
15
10
5
0
1.46
1.48
1.5
1.52
1.54
1.56
1.58
time (ms)
Fig. 9: Simulated VL when iL is stepped from 5A to 20A
4. CONCLUSIONS
As the electronic equipment becomes more
sophisticated with a trend toward operating at lower
supply voltages and higher clock speeds, designing a
power supply for these modern loads poses many
challenges to a power supply designer. Simulation is an
indispensable tool in the modern days of power supply
design; it can be used to check the validity of the resulting
design and the regulator’s performance under various
operating conditions as well as under the influence of
circuit parasitics. Adoption of simulation into the design
process often results in the increased productivity and the
reduced time-to-market. In this paper, SPICE simulation
of DC/DC switching power supplies based on macromodels has been studied. Its potential as an efficient tool
in modern power supply design has been demonstrated
through the simulation examples.
5. REFERENCES
[1] S. Kelkar, “Comparison of Two Circuit-Level
Simulation
Techniques
for
Power-Processing
Circuits,” Proceeding of IEEE Applied Power
Electronics Conference and Exposition (APEC90), pp.
605-611, 1990.
[2] M. T. Zhang, M. M. Jovanovic, and F. C. Lee,
“Design Considerations for Low-Voltage On-Board
DC/DC Modules for Next Generations of Data
Processing Circuits,” IEEE trans. Power Electronics,
Vol. 11, No. 2, pp. 328-333, 1996.
[3] J. A. Connelly and P. Choi, Macromodeling with
SPICE, Prentice Hall, Inc., 1992.
[4] R. K. Swami and R. Senani, “Macromodeling Ideal
Switches for SPICE,” IEEE Circuits and Devices
Magazine, Vol. 11, pp. 8-10, 1995.
[5] Unitrode’s Power Supply Circuit Data Book, Unitrode
Corp., 1993.