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AN2787
Application note
Monolithic VR demonstration board for chipset
and DDR2/3 supply for ultramobile PC (UMPC) applications
Introduction
PM6641 demonstration board order code: STEVAL-ISA050V1 (previously coded as
PM6641EVAL).
The PM6641 demonstration board is a monolithic voltage regulator (VR) module with
internal power MOSFETs, specifically designed to supply DDR2/3 memory and chipset in
ultramobile PC and real estate constrained portable systems.
It integrates three independent, adjustable, constant frequency buck converters, a ±2 Apk
low dropout (LDO) linear regulator, and a ±15 mA low-noise buffered reference.
Each regulator is provided with basic undervoltage (UV) and overvoltage (OV) protections,
programmable soft-start and current limit, active soft-end, and pulse skipping at light loads.
This document describes all features of the PM6641 demonstration board.
Figure 1.
September 2008
PM6641 demonstration board
Rev 1
1/37
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Contents
AN2787
Contents
1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Demonstration kit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Component assembly and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Recommended equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
JP1 VDDQ output discharge (DSCG pin) . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2
JP3 switching regulator phase control (SET_PH1 pin) . . . . . . . . . . . . . . 15
7.3
JP4 1.8 V (VDDQ) external/internal divider (VFB_1S8 pin) . . . . . . . . . . . 16
7.4
JP5 1.5 V external/internal divider (VFB_1S5 pin) . . . . . . . . . . . . . . . . . . 17
7.5
JP6 1.05 V external/internal divider (VFB_1S05 pin) . . . . . . . . . . . . . . . . 17
7.6
JP7 current limit (CSNS pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9
Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10
STEVAL-ISA050V1 evaluation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.1
SW regulators turn-on (soft-start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10.2
SW regulator - working mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.3
Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10.4
Load transient responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10.5
Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.6
Phase management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10.7
Fault management (OVP, UVP, UVLO, thermal) . . . . . . . . . . . . . . . . . . . 30
10.8
SW regulators current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.9
Soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2/37
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AN2787
Contents
10.10 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
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List of figures
AN2787
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
PM6641 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
PM6641 demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Top side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Layer 2 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Layer 3 view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bottom side component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
JP1 DSCG pin setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JP3 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
JP4 1.8 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
JP5 1.5 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
JP6 1.05 V divider selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PM6641 demonstration board programmed current limit vs. CSNS resistor . . . . . . . . . . . 18
JP8 setting switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PM6641 demonstration board test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VDDQ turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VDDQ, VTT and VTTREF turn-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PWM mode: VDDQ output voltage, phase voltage and inductor current, current
load = 2.3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pulse skip mode: VDDQ output voltage, phase voltage and inductor current, current
load = 0 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Forced PWM mode (soft OV): VDDQ output voltage, phase voltage, inductor current
and Power Good signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VDDQ (1.8 V) load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5 V load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.05 V load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VTT load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VTTREF load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
VDDQ, VTT and VTTREF, VDDQ load transient response, IVDDQ = 0 to
2.3 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5 V output voltage and inductor current, 1.5 V rail load transient response,
1.5 V = 0 to 1.25 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.05 V output voltage and inductor current, 1.05 V rail load transient response.
I1.05 V = 0 to 1.75 A at 2.5 A/µs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
VDDQ, VTTREF, VTT and VTT output current, VTT rail load transient response,
IVTT = –1 A to +1 A at 2.5 A/µs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SW regulators efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SW regulators phases, 120 deg phase shift. SETPH1 pin tied to AGND . . . . . . . . . . . . . . 29
SW regulators phases, no phase shift - synchronous clock, SETPH1 pin tied to AVCC . . 30
VDDQ, VTT, VTTREF output voltage, VDDQ temporarily shorted to 3.3 V, output
overvoltage protection triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
VDDQ, VTT, VTTREF output voltage and VDDQ inductor current, VDDQ feedback pin
temporarily shorted to GND, output undervoltage protection triggered . . . . . . . . . . . . . . . 31
VDDQ (1.8 V), 1.5 V, 1.05 V output voltage and AVCC input power supply, input
undervoltage lockout triggered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VDDQ (1.8 V), 1.5 V, 1.05 V and VTT rails output voltage, thermal shutdown triggered . . 32
1.5 V rail output voltage, 1.5 V inductor current and output current, peak current limit
4/37
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AN2787
Figure 39.
Figure 40.
Figure 41.
List of figures
reached . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
VDDQ(1.8 V), VTT and VTTREF rail output voltage, EN_1S8 and EN_VTT tied to
AGND - soft off with tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VDDQ(1.8 V), VTT and VTTREF rail output voltage. EN_1S8 and EN_VTT tied to
AGND - soft off without tracking discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PM6641 demonstration board surface temperature when loaded with typical currents,
Tamb = 23 °C, VIN = 3.3 V, FSW = 660 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5/37
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Main features
1
AN2787
Main features
Switching section
●
0.8 V ±1% voltage reference
●
2.7 V to 5.5 V input voltage range
●
Fast response, constant frequency, current mode control
●
Three independent, adjustable, SMPS for DDR2/3 (VDDQ) and chipset supply
●
S3-S5 states compliant with DDR2/3 section
●
Active soft-end for all outputs
●
Selectable tracking discharge for VDDQ
●
Separate Power Good signals
●
Pulse skipping at light load
●
Programmable current limit and soft-start for all outputs
●
Latched OVP, UVP protection
●
Thermal protection
Reference and termination voltages (VTTREF and VTT)
●
±2 Apk LDO for DDR2/3 termination (VTT) with foldback
●
Remote VTT output sensing
●
High-Z VTT output in S3
●
±15 mA low-noise DDR2/3 buffered reference (VTTREF)
6/37
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2
3
1
JP4
STRIP 3
1
0603-1u
C1
0603-100p
C29
+ C5
EL SMD C-10u
R6
0603-120k
R5
0603-150k
TP8
GND
TP9
VOUT_1S8
VCC
1
R3
0603-100k
VIN
C22
0603-330p
R11
0603-100k
0603-22n
C19
0603-15p
C32
C2
0805-10u
1
C15
B Case - 220u
C6
B Case - 220u
2839-1u
C21
2
3
1
2
JP6
STRIP 3
C24
0603-330p
C17
C12
0805-10u
0603-33n
C18
R10
0603-180k
U1
PM6641_QFPN
1
AVCC
TP16
AGND
C11
1206-22u
36
35
34
33
32
31
30
29
28
27
26
25
C9
B Case - 220u
EN_VTT
EN_1S5
EN_1S05
VIN_1S5
VSW_1S5_2
VSW_1S5_1
SGND_1S5_2
SGND_1S5_1
VFB_1S5
COMP_1S5
SS_1S5
PG_1S5
L3
2839-1u
VOUT_1S05
1
TP12
0603-100p
C31
THERMAL
R9
0603-56k
R2
0603-4R3
0603-100n
AGND_1
SET_SWF
VOUT_1S8
CSNS
SGND_1S8_1
SGND_1S8_2
VSW_1S8_1
VSW_1S8_2
VIN_1S8_1
VIN_1S8_2
VFB_1S8
COMP_1S8
0603-15p
C33
49
1
2
3
4
5
6
7
8
9
10
11
12
R33
0603-join
1
TP14
VTT
1
TP1
VTTREF
1
AVCC
R13
0603-68k
0603-join
R32
R4
0603-68k
JP1
STRIP 3
2
0603-22n
L1
2
1
STRIP 2
JP8
2
1
1
STRIP 2
JP7
0603-100n
AVCC
R1
0603-4R3
C16
1
1
AVCC
1
2
AVCC
C4
0805-10u
VIN
GND
1
TP13
R31
0603-join
1
2
VCC
GND
TP17
EL SMD C-10u
1
2
2839-1u5
VIN
0603-100p
C25
R34
0603-join
1
VIN
TP7
TP18
AUX
0603-100p
C26
R17
0603-68k
AUX
R18
0603-68k
AUX
R22
0603-68k
R19
0603-68k
1
2
3
4
TP2
PG_1S8
TP3
PG_1S5
8
7
6
5
TP4
PG_1S05
R8
0603-120k
R7
0603-100k
SW DIP-4
SW1
JP5
STRIP 3
0603-100p
C28
R23
0603-68k
2
+ C8
EL SMD C-10u
0603-100p
C27
R21
0603-68k
AUX
R20
0603-68k
0603-100p
C30
C7
B Case - 220u
C3
0805-10u
R30
0603-join
C23
0603-470p
L2
C34
0603-15p
1
C20
0603-22n
R12
0603-47k
JP3
STRIP 3
+ C13
C10
EL SMD C-10u
B Case - 220u
C14
2
AVCC
3
1
TP15
LDOIN
2
1
1
TP6
AGND
3
2
48
47
46
45
44
43
42
41
40
39
38
37
VCC
VTT_FB
DSCG
VTTREF
LDO_IN
VTT
VTT_GND
AVCC
AGND_2
SET_PH1
AGND_3
EN_1S8
SS_1S8
SS_1S05
COMP_1S05
VFB_1S05
SGND_1S05_1
SGND_1S05_2
VSW_1S05_1
VSW_1S05_2
VIN_1S05_1
VIN_1S05_2
PG_1S05
PG_1S8
13
14
15
16
17
18
19
20
21
22
23
24
1
2
TP5
VCC
+
1
1
2
3
1
1
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1
TP10
VOUT_1S5
TP11
GND
1
Figure 2.
1
2
1
AN2787
Demonstration kit schematic
Demonstration kit schematic
PM6641 demonstration board schematic
7/37
Bill of material
AN2787
3
Bill of material
Table 1.
PM6641 demonstration board list of components
Qty Component
Description
Package
Part number
MFR
Value
Standard
1µ
Murata
10 µ
Note
1
C1
Ceramic, 10 V,
X5R, 20%
SMD 0603
4
C2, C3, C4,
C12
Ceramic, 10 V,
X5R, 20%
SMD 0805
4
C5, C8, C13,
C14
5
C6, C7, C9,
C10, C15
Ceramic, 4 V,
X5R, 20%
SMD 1206
AMK316BJ107ML
Taiyo Yuden
100 µ
1
C11
Ceramic, 6.3 V,
X5R, 10%
SMD 1206
GRM31CR60J226KE19
Murata
22 µ
2
C16, C17
Ceramic, 16 V,
X7R, 10%
SMD 0603
Standard
100 n
1
C18
Ceramic, 25 V,
X7R, 10%
SMD 0603
Murata
33 n
3
C19, C20,
C21
Ceramic, 16 V,
X7R, 10%
SMD 0603
Standard
22 n
2
C22, C24
Ceramic, 50 V,
C0G, 5%
SMD 0603
Standard
330 pF
1
C23
Ceramic, 50 V,
C0G, 5%
SMD 0603
Standard
470 pF
4
C25, C26,
C27, C28
Ceramic, 50 V,
C0G, 5%
SMD 0603
Standard
100 pF
3
C29, C30,
C31
Ceramic, 50 V,
C0G, 5%
SMD 0603
n.m.
3
C32, C33,
C34
Ceramic, 50 V,
C0G, 5%
SMD 0603
n.m.
2
R1, R2
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
3R3
1
R3
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
100 kΩ
9
R4, R13
R17, R18,
R19, R20,
R21, R22,
R23
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
68 kΩ
1
R16
Chip resistor,
0.1 W, 1%
SMD 0603
1
R5
Chip resistor,
0.1 W, 1%
SMD 0603
GRM21BR61A106KE19
SMD C case
n.m.
GRM188R71E333KA01
n.m.
Standard
8/37
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150 kΩ
AN2787
Bill of material
Table 1.
PM6641 demonstration board list of components (continued)
Qty Component
Description
Package
Part number
MFR
Value
2
R6, R8
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
120 kΩ
1
R7
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
100 kΩ
1
R9
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
56 kΩ
1
R10
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
180 kΩ
1
R11
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
100 kΩ
1
R12
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
47 kΩ
3
R32, R33,
R34
Chip resistor,
0.1 W, 1%
SMD 0603
Standard
0Ω
2
R30, R31
Chip resistor,
0.1 W, 1%
SMD 0603
2
L1, L3
SMT 11Arms,
9.5 mΩ
SMD 2827
744312100 /LF
Würth
1.0 µH
1
L2
SMT 9 Arms,
10.5 mΩ
SMD 2827
744312150 /LF
Würth
1.5 µH
1
U1
IC VR - 48-pin
VFQFPN 7x7
PM6641
STMicroelectronics
5
JP1, JP3,
JP4, JP5,
JP6
Header, 3-pin
SIP3
2
JP7, JP8
Header, 2-pin
SIP2
5
TP1, TP2,
TP3, TP4,
TP18
Header, single
pin
13
TP5, TP6,
TP7, TP8,
TP9, TP10,
TP11, TP12,
TP13, TP14,
TP15, TP16,
TP17
Test point
1
SW1
Switch 4-SPST
DIP-8
Note
short
n.m.
Standard
9/37
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Component assembly and layout
4
Component assembly and layout
Figure 3.
Top side component placement
Figure 4.
Top view
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Component assembly and layout
Figure 5.
Layer 2 view
Figure 6.
Layer 3 view
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Component assembly and layout
Figure 7.
Bottom view
Figure 8.
Bottom side component placement
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5
I/O interface
I/O interface
The PM6641 demonstration board has the following test points given in Table 2.
Table 2.
PM6641 demonstration board input/output interface
Test point
Description
VCC (TP5)
+5 V IC supply, positive terminal
LDOIN (TP15)
LDO (VTT) linear regulator input power supply
AUX (TP18)
Auxiliary 3.3 V for pull-up (not required)
AGND (TP6, TP16)
VCC, LDO, VTT and VTTREF common return
VIN (TP7)
Power supply input voltage positive terminal
GND (TP8, TP11, TP13, TP17)
Power supply and switching regulator outputs common return
V1S8 (TP9)
1.8 V (VDDQ) switching regulator output
V1S5 (TP10)
1.5 V switching regulator output
V1S05 (TP12)
1.05 V switching regulator output
VTT (TP14)
LDO (VTT) linear regulator output
VTTREF (TP1)
Voltage reference (VTTREF) buffer output
PG1S8 (TP2)
1.8 V (VDDQ) switching regulator Power Good signal
PG1S5 (TP3)
1.5 V switching regulator Power Good signal
PG1S05 (TP4)
1.05 V switching regulator Power Good signal
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Recommended equipment
6
Recommended equipment
●
5 V power supply
●
3.3 V, 20 W power supply
●
Active loads
●
Digital multimeters
●
500 MHz four-trace oscilloscope
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7
Configuration
Configuration
The PM6641 demonstration board allows the user to test all the main features of the VR
PM6641, acting on 7 different jumpers and 4 switches. SW1 (4 SPST switches) lets the user
enable the switching regulators and the VTT linear regulator.
In the following sections each jumper is analyzed.
7.1
JP1 VDDQ output discharge (DSCG pin)
The JP1 jumper is used to choose between the tracking discharge or nontracking discharge
of the 1.8 V rail (VDDQ) output.
When the 1.8 V rail is deactivated (EN_1S8 goes low) and the DSCG is set high, tracking
discharge takes place:
●
The 1.8 V rail regulator is discharged by the internal MOSFETs
●
The 0.9 V LDO and VTTREF work tracking with half of the 1.8 V rail
When the 0.9 V LDO and VTTREF reach a voltage threshold of about 300 mV, the
nontracking discharge mode is performed by closing the internal discharge MOSFETs.
If the nontracking discharge mode is chosen, when EN_1S8 goes low, the 1.8 V and 0.9 V
rails and the VTTREF buffer are independently discharged by internal MOSFETs.
Figure 9.
JP1 DSCG pin setting
Tracking Discharge
Non Tracking Discharge
7.2
JP3 switching regulator phase control (SET_PH1 pin)
The JP3 jumper allows selecting two different oscillator settings in order to change the delay
between the pulses that start the control cycle. The inner clock is divided in order to obtain
three slower clocks with a fixed delay of 120 deg. By setting JP3 as depicted in Figure 10, it
is possible to synchronize the 1.8 V, 1.5 V and 1.05 V switching regulator clocks or to select
120 deg delay in order to decrease the total RMS input current.
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Configuration
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Figure 10. JP3 phase control
JP3
120deg Phase Shifting
Synchronous
The 120 deg phase shifting is the default configuration in which the inner clock is divided
and three pulses delayed by 120 deg are obtained to trigger the switching regulator loops.
The synchronous clocking allows all the regulators to start at the same pulse, avoiding the
jitter due to simultaneous turn-on and off of different sections, but increasing the overall
RMS input current.
7.3
JP4 1.8 V (VDDQ) external/internal divider (VFB_1S8 pin)
The JP4 jumper allows selecting the internal divider or the external divider for the 1.8 V
switching regulator. When the VFB_1S8 pin is connected directly to the output capacitor, the
internal divider is enabled and this section provides 1.8 V output voltage. When the
multifunction pin VFB_1S8 is tied to the central tap of an external divider, the switching
regulator becomes adjustable, with the following output voltage:
Equation 1
⎛R
⎞
Vout = ⎜⎜ 5 + 1⎟⎟ ⋅ 0.8 V
⎝ R6
⎠
Figure 11. JP4 1.8 V divider selection
External Divider Enabled
Internal Divider Enabled
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7.4
Configuration
JP5 1.5 V external/internal divider (VFB_1S5 pin)
The JP5 jumper allows selecting the internal divider or the external divider for the 1.5 V
switching regulator. When the VFB_1S5 pin is connected directly to the output capacitor, the
internal divider is enabled and this section provides 1.5 V output voltage. When the
multifunction pin VFB_1S5 is tied to the central tap of an external divider, the switching
regulator becomes adjustable, with the following output voltage:
Equation 2
⎛R
⎞
Vout = ⎜⎜ 7 + 1⎟⎟ ⋅ 0.8 V
R
⎝ 8
⎠
Figure 12. JP5 1.5 V divider selection
Internal Divider Enabled
External Divider Enabled
7.5
JP6 1.05 V external/internal divider (VFB_1S05 pin)
The JP6 jumper allows selecting the internal divider or the external divider for the 1.05 V
switching regulator. When the VFB_1S05 pin is connected directly to the output capacitor,
the internal divider is enabled and this section provides 1.05 V output voltage. When the
multifunction pin VFB_1S5 is tied to the central tap of an external divider, the switching
regulator becomes adjustable, with the following output voltage:
Equation 3
⎛R
⎞
Vout = ⎜⎜ 9 + 1⎟⎟ ⋅ 0.8 V
R
⎝ 10
⎠
Figure 13. JP6 1.05 V divider selection
External Divider Enabled
Internal Divider Enabled
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Configuration
7.6
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JP7 current limit (CSNS pin)
Each switching regulator current limit is set by inserting a resistor between the CSNS pin
and AGND. By changing this resistor value, all the current limits change, as shown in
Figure 14.
Figure 14. PM6641 demonstration board programmed current limit vs. CSNS
resistor
Peak Current Limit
7,00
6,00
Current Limit [A]
5,00
CL_1V8
4,00
CL_1V5
3,00
CL_1V05
2,00
1,00
0,00
50
70
90
110
130
150
170
Rcsns [kOhm ]
If the CSNS pin is tied to AVCC, the current limit is set through the inner reference resistor
(equal to 50 kΩ).
Figure 15. JP8 setting switching frequency
Default Switching Frequency
Adjusted Switching Frequency
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8
Test setup
Test setup
Figure 16 shows the suggested setup connections between the PM6641 demonstration
board, the loads, and the external supply.
Figure 16. PM6641 demonstration board test setup
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Getting started
9
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Getting started
The following step-by-step power-up and power-down sequences are provided in order to
correctly evaluate the PM6641 demonstration board performance.
Power-up sequence
●
Connect power supplies as shown in the PM6641 demonstration board test setup
(Figure 16) and insert the meters in order to perform the desired performance
evaluation. Connect the scope-probes as desired
●
Set the JP1 through JP8 jumpers in order to properly configure the PM6641
demonstration board. Set the SW1 switches (EN_1S8, EN_VTT, EN_1S5, EN_1S05)
to the ON position. Do not change jumper settings when the board is powered
●
Set the VCC supply to 5 V ±5% and the current limit to 100 mA
●
Set the VIN supply to a voltage in the range 2.7 V to 3.6 V
●
Set all active loads to 0 A
●
Turn-on the VIN supply
●
Turn-on the VCC supply
●
Vary the 1.8 V (VDDQ) load from 0 A to 4 A
●
Vary the 1.5 V load from 0A to 2.5 A
●
Vary the 1.05 V load from 0A to 3.5 A
●
Vary the 0.9 V (VTT) load from 0 A to 2 A to test source capability. To test sink
capability use the alternative VTT load connection shown in Figure 16
●
Vary VTTREF load to test source capabilty.
Power-down sequence
●
Decrease VTTREF and VTT loads to 0 A
●
Turn-off the 1.8 V (VDDQ), 1.5 V, 1.05 V loads
●
Decrease VCC supply from 5 V to 3.8 V in order to test the input undervoltage lockout
(UVLO)
●
Increase VCC supply from 3.8 V to 5 V to restart the device
●
Use the EN_1S8 and En_VTT switches to enter/exit the S0-S3-S5 states
●
Turn-off the VCC supply
●
Turn-off the VIN supply.
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STEVAL-ISA050V1 evaluation tests
10
STEVAL-ISA050V1 evaluation tests
10.1
SW regulators turn-on (soft-start)
When the EN_xx pin is toggled high, the correspondent SW regulator performs the soft-start
as programmed through the external soft-start capacitor. Figure 17 depicts VDDQ (1.8 V)
turn-on with CSS = 22 nF.
Figure 17. VDDQ turn-on
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Figure 18. VDDQ, VTT and VTTREF turn-on
10.2
SW regulator - working mode
Each switching regulator changes working mode with the appropriate load. When the load is
heavy, the SW enters PWM mode, but when the load is light, pulse skip mode is entered.
Each SW regulator is also able to sink current from the output (forced PWM mode when a
soft overvoltage occurs).
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STEVAL-ISA050V1 evaluation tests
Figure 19. PWM mode: VDDQ output voltage, phase voltage and inductor current,
current load = 2.3 A
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Figure 20. Pulse skip mode: VDDQ output voltage, phase voltage and inductor
current, current load = 0 A
Figure 21. Forced PWM mode (soft OV): VDDQ output voltage, phase voltage,
inductor current and Power Good signal
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10.3
STEVAL-ISA050V1 evaluation tests
Load regulation
Figure 22. VDDQ (1.8 V) load regulation
Figure 23. 1.5 V load regulation
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Figure 24. 1.05 V load regulation
Figure 25. VTT load regulation
Figure 26. VTTREF load regulation
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10.4
STEVAL-ISA050V1 evaluation tests
Load transient responses
Figure 27. VDDQ, VTT and VTTREF, VDDQ load transient response, IVDDQ = 0 to
2.3 A at 2.5 A/µs
Figure 28. 1.5 V output voltage and inductor current, 1.5 V rail load transient
response, 1.5 V = 0 to 1.25 A at 2.5 A/µs
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Figure 29. 1.05 V output voltage and inductor current, 1.05 V rail load transient
response. I1.05 V = 0 to 1.75 A at 2.5 A/µs
Figure 30. VDDQ, VTTREF, VTT and VTT output current, VTT rail load transient
response, IVTT = –1 A to +1 A at 2.5 A/µs
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10.5
STEVAL-ISA050V1 evaluation tests
Efficiency
Figure 31. SW regulators efficiency
10.6
Phase management
Figure 32 and 33 show the SW regulators loaded with 1.3 A (VDDQ rail), 1.25 A (1.5 V rail)
and 1.75 A (1.05 V rail). By connecting the SETPH1 pin to AGND or to AVCC the following
two different phase shifts are allowed.
Figure 32. SW regulators phases, 120 deg phase shift. SETPH1 pin tied to AGND
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Figure 33. SW regulators phases, no phase shift - synchronous clock, SETPH1 pin
tied to AVCC
10.7
Fault management (OVP, UVP, UVLO, thermal)
Each switching regulator is able to detect the output overvoltage and undervoltage. When
the OV is detected the high-side MOSFET is turned off and the low-side MOSFET is turned
on. When the UV is detected, the power MOSFETs are both turned off and the discharge
MOSFET is turned on (soft-end). The soft-end is also performed when the junction
temperature is higher than 150 °C.
Figure 34. VDDQ, VTT, VTTREF output voltage, VDDQ temporarily shorted to 3.3 V,
output overvoltage protection triggered
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Figure 35. VDDQ, VTT, VTTREF output voltage and VDDQ inductor current, VDDQ
feedback pin temporarily shorted to GND, output undervoltage protection
triggered
When the input undervoltage is detected, the VDDQ (1.8 V) rail performs the output voltage
soft-end. The 1.5 V and 1.05 V rails turn-off the high-side power MOSFET and turn-on the
low-side one.
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Figure 36. VDDQ (1.8 V), 1.5 V, 1.05 V output voltage and AVCC input power supply,
input undervoltage lockout triggered
Figure 37. VDDQ (1.8 V), 1.5 V, 1.05 V and VTT rails output voltage, thermal
shutdown triggered
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10.8
STEVAL-ISA050V1 evaluation tests
SW regulators current limit
Cycle-by-cycle the high-side MOSFET current is monitored and if it's higher than the
programmed current limit, the high-side MOSFET is immediately turned off.
Figure 38. 1.5 V rail output voltage, 1.5 V inductor current and output current, peak
current limit reached
10.9
Soft-end
Each SW regulator, when turned off, performs the output voltage soft-end by turning off the
power MOSFET and turning on the discharge MOSFET. When the output voltage is lower
than about 300 mV, the low-side power MOSFET is turned on. VTTREF and VTT can track
half of VDDQ also during the soft off.
These rails are allowed two different modes of discharge: tracking and nontracking
discharge.
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Figure 39. VDDQ(1.8 V), VTT and VTTREF rail output voltage, EN_1S8 and EN_VTT
tied to AGND - soft off with tracking discharge
Figure 40. VDDQ(1.8 V), VTT and VTTREF rail output voltage. EN_1S8 and EN_VTT
tied to AGND - soft off without tracking discharge
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10.10
STEVAL-ISA050V1 evaluation tests
Thermal behavior
The device temperature is mainly influenced by LDO VTT current. The typical working
currents are shown in Table 3.
Table 3.
Average working currents for each rail
Rail
Current [A]
VDDQ (1.8 V)
1.35
1.5 V
1.25
1.05 V
1.75
VTT (0.9 V)
0.3
VTT is supplied by VDDQ and the device (average) temperature is 54.5 °C.
Figure 41. PM6641 demonstration board surface temperature when loaded with
typical currents, Tamb = 23 °C, VIN = 3.3 V, FSW = 660 kHz
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Revision history
11
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Revision history
Table 4.
Document revision history
Date
Revision
05-Sep-2008
1
Changes
Initial release
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