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Transcript
STL70N4LLF5
N-channel 40 V, 0.0061 Ω, 18 A, PowerFLAT™ 5x6
STripFET™ V Power MOSFET
Features
Order code
VDSS
RDS(on)
max
ID
STL70N4LLF5
40 V
0.0067 Ω
18 A (1)
1. The value is rated according to Rthj-pcb
1
■
RDS(on) * Qg industry benchmark
■
Extremely low on-resistance RDS(on)
■
High avalanche ruggedness
■
Low gate drive power losses
2
3
4
PowerFLAT™ 5x6
Applications
■
Switching applications
Figure 1.
Internal schematic diagram
Description
This device is an N-channel Power MOSFET
developed using STMicroelectronics’
STripFET™V technology. The device has been
optimized to achieve very low on-state resistance,
contributing to an FOM that is among the best in
its class.
$
$
$
$
'
3
3
3
"OTTOM6IEW
4OP6IEW
!-6
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL70N4LLF5
70N4LLF5
PowerFLAT™ 5x6
Tape and reel
December 2011
Doc ID 15229 Rev 3
1/13
www.st.com
www.bdtic.com/ST
13
Contents
STL70N4LLF5
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
.............................................. 8
Doc ID 15229 Rev 3
www.bdtic.com/ST
STL70N4LLF5
1
Electrical ratings
Electrical ratings
.
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
40
V
VGS
Gate-source voltage
± 22
V
ID(1)
Drain current (continuous) at TC = 25 °C
70
A
ID (1)
Drain current (continuous) at TC = 100 °C
44
A
ID(2)
Drain current (continuous) at Tpcb = 25 °C
18
A
(2)
Drain current (continuous) at Tpcb=100 °C
11.5
A
ID
IDM(2),(3)
Drain current (pulsed)
72
A
PTOT (1)
Total dissipation at TC = 25 °C
60
W
Total dissipation at Tpcb = 25 °C
4
W
0.03
W/°C
-55 to 150
°C
Value
Unit
PTOT
(2)
Derating factor
TJ
Operating junction temperature
Storage temperature
Tstg
1. The value is rated according to Rthj-c .
2. The value is rated according to Rthj-pcb.
3. Pulse width limited by safe operating area.
Table 3.
Thermal resistance
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
2.08
°C/W
Thermal resistance junction-pcb
31.3
°C/W
Value
Unit
9
A
1090
mJ
Rthj-pcb
(1)
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec.
Table 4.
Symbol
Avalanche data
Parameter
IAV
Not-repetitive avalanche current,
(pulse width limited by Tj max)
EAS
Single pulse avalanche energy
(starting TJ = 25 °C, ID = IAV , VDD = 24 V)
Doc ID 15229 Rev 3
www.bdtic.com/ST
3/13
Electrical characteristics
2
STL70N4LLF5
Electrical characteristics
(TCASE = 25 °C unless otherwise specified)
Table 5.
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown
voltage (VGS= 0)
ID = 250 µA
Zero gate voltage drain
current (VGS = 0)
IGSS
Gate body leakage current
(VDS = 0)
VGS = ±22 V
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 9 A
Symbol
Ciss
Coss
Crss
Qg
Qgs
Qgd
RG
Min.
Typ.
Max.
40
Unit
V
VDS = 40 V,
IDSS
Table 6.
4/13
On/off states
VDS = 40 V,TC = 125 °C
1
10
µA
µA
±100
nA
1
V
Ω
Ω
0.0061
0.0076
0.0067
0.009
Min.
Typ.
Max.
Unit
-
1570
257
32
-
pF
pF
pF
-
12.9
3.9
5.3
-
nC
nC
nC
-
1.5
-
Ω
VGS= 4.5 V, ID= 9 A
Dynamic
Parameter
Input capacitance
Output capacitance
Reverse transfer
capacitance
Total gate charge
Gate-source charge
Gate-drain charge
Gate input resistance
Test conditions
VDS = 25 V, f=1 MHz,
VGS=0
VDD=15 V, ID = 18 A
VGS = 4.5 V
(see Figure 14)
f=1 MHz Gate DC Bias = 0
Test signal level = 20 mV
open drain
Doc ID 15229 Rev 3
www.bdtic.com/ST
STL70N4LLF5
Electrical characteristics
Table 7.
Symbol
td(on)
Switching times
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
tr
td(off)
tf
Table 8.
Symbol
ISD
Test conditions
Min.
Typ.
Max.
Unit
-
14
42
37
5.2
-
ns
ns
ns
ns
Min.
Typ.
Max.
Unit
VDD=15 V, ID= 9A,
RG=4.7 Ω, VGS=10 V
(see Figure 13)
Source drain diode
Parameter
Test conditions
Source-drain current
-
18
A
ISDM(1)
Source-drain current (pulsed)
-
72
A
VSD(2)
Forward on voltage
ISD = 18A, VGS=0
-
1.1
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 18A,
trr
Qrr
IRRM
di/dt = 100 A/µs,
VDD= 25 V, TJ=150 °C
-
27.2
24.5
1.8
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration=300µs, duty cycle 1.5%
Doc ID 15229 Rev 3
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5/13
Electrical characteristics
STL70N4LLF5
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
!-V
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AR ON
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4J #
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Figure 4.
)$
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6$36
Output characteristics
!-V
6'36
!-V
)$
!
6$36
6
6
6
Figure 6.
6$36
Normalized BVDSS vs temperature
!-V
"6$33
NORM
Figure 7.
6'36
Static drain-source on resistance
!-V
2$3ON
/HM
)$—!
6/13
4* #
6'36
Doc ID 15229 Rev 3
www.bdtic.com/ST
)$!
STL70N4LLF5
Figure 8.
Electrical characteristics
Gate charge vs gate-source voltage Figure 9.
!-V
6'3
6
6$$6
)$!
Capacitance variations
!-V
#
P&
#ISS
#OSS
1GN#
Figure 10. Normalized gate threshold voltage
vs temperature
!-V
6'3TH
NORM
#RSS
6$36
Figure 11. Normalized on resistance vs
temperature
!-V
2$3ON
NORM
4* #
4* #
Figure 12. Source-drain diode forward
characteristics
!-V
63$
6 4* #
4* #
4* #
)3$!
Doc ID 15229 Rev 3
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7/13
Test circuits
3
STL70N4LLF5
Test circuits
Figure 13. Switching times test circuit for
resistive load
Figure 14. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 15. Test circuit for inductive load
Figure 16. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 17. Unclamped inductive waveform
AM01471v1
Figure 18. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDS
VDD
90%
VGS
AM01472v1
8/13
0
10%
Doc ID 15229 Rev 3
www.bdtic.com/ST
AM01473v1
STL70N4LLF5
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Doc ID 15229 Rev 3
www.bdtic.com/ST
9/13
Package mechanical data
Table 9.
STL70N4LLF5
PowerFLAT 5x6 type S-C mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
1.00
A1
0.02
0.05
A2
b
0.25
0.30
0.50
D
5.20
E
6.15
D2
4.11
4.31
E2
3.50
3.70
e
1.27
e1
0.65
L
0.715
1.015
K
1.05
1.35
Figure 19. PowerFLAT 5x6 type S-C drawing
4OPVIEW
"OTTOMVIEW
3IDEVIEW
?$?TYPE#
10/13
Doc ID 15229 Rev 3
www.bdtic.com/ST
STL70N4LLF5
Package mechanical data
Figure 20. PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
5.35
0.95
0.98
6.26
3.86
4.33
4.41
1.27
0.62
Footprint
Doc ID 15229 Rev 3
www.bdtic.com/ST
11/13
Revision history
5
STL70N4LLF5
Revision history
Table 10.
12/13
Document revision history
Date
Revision
Changes
01-Dec-2008
1
First release
18-Jul-2011
2
Section 4: Package mechanical data has been modified:
– Added Table 9: PowerFLAT 5x6 type S-C mechanical data
– Added Figure 19: PowerFLAT 5x6 type S-C drawing
– Added PowerFLAT™ 5x6 type C-B mechanical data
– Added PowerFLAT™ 5x6 type C-B drawing
– Added Figure 20: PowerFLAT™ 5x6 recommended footprint
(dimensions are in mm).
Minor text changes.
21-Dec-2011
3
Section 4: Package mechanical data has been modified.
Doc ID 15229 Rev 3
www.bdtic.com/ST
STL70N4LLF5
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13/13