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STL23NM50N N-channel 500 V, 0.170 Ω typ., 14 A MDmesh™ II Power MOSFET in a PowerFLAT™ 8x8 HV package Datasheet — production data Features Type VDSS @ TJmax RDS(on) max ID STL23NM50N 550 V < 0.210 Ω 14 A (1) 3 3 3 "OTTOMVIEW ' $ 1. The value is rated according to Rthj-case ■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance 0OWER&,!4X(6 Applications ■ Switching applications Description Figure 1. This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Internal schematic diagram $ ' 3 !-V Table 1. Device summary Order code Marking Package Packaging STL23NM50N 23NM50N PowerFLAT™ 8x8 HV Tape and reel October 2012 Doc ID 022339 Rev 2 This is information on a product in full production. www.bdtic.com/ST 1/13 www.st.com 13 Contents STL23NM50N Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuits 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 .............................................. 8 Doc ID 022339 Rev 2 www.bdtic.com/ST STL23NM50N 1 Electrical ratings Electrical ratings Table 2. Symbol Absolute maximum ratings Parameter Value Unit VDS Drain-source voltage (VGS = 0) 500 V VGS Gate-source voltage ± 25 V Drain current (continuous) at TC = 25 °C 14 A ID (1) ID (1) Drain current (continuous) at TC = 100 °C 11 A ID (3) Drain current (continuous) at Tamb = 25 °C 2.8 A ID (3) Drain current (continuous) at Tamb = 100 °C 2.1 A (1),(2) Drain current (pulsed) 56 A PTOT (3) Total dissipation at Tamb = 25 °C 3 W PTOT(1) Total dissipation at TC = 25 °C 125 W IDM IAR Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max) 4 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 300 mJ Peak diode recovery voltage slope 15 V/ns - 55 to 150 °C 150 °C Value Unit dv/dt (4) Tstg Storage temperature Tj Max. operating junction temperature 1. The value is rated according to Rthj-case 2. Pulse width limited by safe operating area 3. When mounted on FR-4 board of inch², 2oz Cu 4. ISD ≤ 14 A, di/dt ≤ 400 A/µs, VDSpeak ≤V(BR)DSS, VDD = 80% V(BR)DSS Table 3. Symbol Thermal data Parameter Rthj-case Thermal resistance junction-case max 1 °C/W Rthj-amb(1) Thermal resistance junction-amb max 45 °C/W 1. When mounted on 1inch² FR-4 board, 2 oz Cu Doc ID 022339 Rev 2 www.bdtic.com/ST 3/13 Electrical characteristics 2 STL23NM50N Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4. Symbol On /off states Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 IDSS Zero gate voltage drain current VDS = Max rating VDS = Max rating, TC=125 °C VGS = 0 1 100 µA µA IGSS Gate-body leakage current VGS = ± 25 V, VDS = 0 100 nA 3 4 V 0.170 0.210 Ω VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onVGS = 10 V, ID = 7 A resistance Table 5. Symbol Ciss Coss Crss Coss eq. (1) Qg Qgs Qgd Rg 500 V 2 Dynamic Parameter Test conditions Min. Typ. Max. Unit - pF pF pF Input capacitance Output capacitance Reverse transfer capacitance VDS = 50 V, f = 1 MHz, VGS = 0 - 1330 84 4.8 Equivalent output capacitance VGS = 0, VDS = 0 to 400 V - 210 - pF Total gate charge Gate-source charge Gate-drain charge VDD = 400 V, ID = 17 A, VGS = 10 V, (see Figure 14) - 45 7 24 - nC nC nC Gate input resistance f=1 MHz Gate DC Bias=0 Test signal level=20 mV open drain - 4.6 - Ω 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDS Table 6. Symbol td(on) tr td(off) tf 4/13 Switching times Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 250 V, ID = 17 A RG = 4.7 Ω VGS = 10 V (see Figure 13) Min. Typ. - 6.6 19 71 29 Doc ID 022339 Rev 2 www.bdtic.com/ST Max. Unit - ns ns ns ns STL23NM50N Electrical characteristics Table 7. Symbol Source drain diode Parameter Test conditions Min Typ. Max Unit - 17 68 A A 1.5 V ISD ISDM (1) Source-drain current Source-drain current (pulsed) VSD (2) Forward on voltage ISD = 17 A, VGS = 0 - Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 17 A, di/dt = 100 A/µs VDD = 60 V (see Figure 18) - 286 3700 26 ns nC A Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 17 A, di/dt = 100 A/µs VDD = 60 V, Tj = 150 °C (see Figure 18) - 350 4800 27 ns nC A trr Qrr IRRM trr Qrr IRRM 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% Doc ID 022339 Rev 2 www.bdtic.com/ST 5/13 Electrical characteristics STL23NM50N 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance AM10372v1 ID (A) Zth PowerFLAT 8x8 HV K Tj=150°C Tc=25°C Single pulse δ=0.5 is 0.2 10µs S( o n) Op Lim era ite tion d by in th m is ax ar RD ea 10 0.1 100µs -1 10 0.05 0.02 1 1ms 0.01 Single pulse 10ms -2 0.1 0.1 Figure 4. )$ ! 10 1 100 VDS(V) Output characteristics 10 -5 10 Figure 5. !-V 6'36 tp (s) 10 !-V )$ ! 6$36 6 6 Figure 6. -2 -3 10 Transfer characteristics -4 10 6$36 Normalized BVDSS vs temperature AM10374v1 BVDSS (norm) Figure 7. ID=1mA 6'36 Static drain-source on-resistance AM10373v1 RDS(on) (Ω) 0.178 1.07 VGS=10V 0.176 1.05 0.174 1.03 0.172 1.01 0.170 0.99 0.168 0.166 0.97 0.164 0.95 0.93 -50 -25 6/13 0.162 0 25 50 75 100 TJ(°C) 0.160 0 2 4 6 8 Doc ID 022339 Rev 2 www.bdtic.com/ST 10 12 14 ID(A) STL23NM50N Figure 8. Electrical characteristics Gate charge vs gate-source voltage Figure 9. !-V 6'3 6 6$3 6$$6 )$! 6$3 6 Capacitance variations !-V # P& #ISS #OSS #RSS 1GN# Figure 10. Normalized gate threshold voltage vs temperature AM10375v1 VGS(th) (norm) AM10376v1 RDS(on) 1.00 1.7 0.90 1.3 0.80 0.9 25 0 75 100 50 ID=7A 2.1 ID=250µA 0.70 -50 -25 6$36 Figure 11. Normalized on-resistance vs temperature (norm) 1.10 TJ(°C) 0.5 -50 -25 0 25 50 75 100 TJ(°C) Figure 12. Source-drain diode forward characteristics AM10377v1 VSD (V) 1.4 TJ=-50°C 1.2 TJ=25°C 1.0 TJ=150°C 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 ISD(A) Doc ID 022339 Rev 2 www.bdtic.com/ST 7/13 Test circuits 3 STL23NM50N Test circuits Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit VDD 12V 47kΩ 1kΩ 100nF 3.3 μF 2200 RL μF VGS IG=CONST VDD 100Ω Vi=20V=VGMAX VD RG 2200 μF D.U.T. D.U.T. VG 2.7kΩ PW 47kΩ 1kΩ PW AM01468v1 AM01469v1 Figure 15. Test circuit for inductive load Figure 16. Unclamped inductive load test switching and diode recovery times circuit A A D.U.T. FAST DIODE B B L A D G VD L=100μH S 3.3 μF B 25 Ω 1000 μF D VDD 2200 μF 3.3 μF VDD ID G RG S Vi D.U.T. Pw AM01470v1 Figure 17. Unclamped inductive waveform AM01471v1 Figure 18. Switching time waveform ton V(BR)DSS tdon VD toff tr tdoff tf 90% 90% IDM 10% ID VDD 10% 0 VDS VDD 90% VGS AM01472v1 8/13 0 10% Doc ID 022339 Rev 2 www.bdtic.com/ST AM01473v1 STL23NM50N 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 8. PowerFLAT™8x8 HV mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.95 1.00 1.05 D 8.00 E 8.00 D2 7.05 7.20 7.30 E2 4.15 4.30 4.40 e L 2.00 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.10 Doc ID 022339 Rev 2 www.bdtic.com/ST 0.60 9/13 Package mechanical data STL23NM50N Figure 19. PowerFLAT™ 8x8 HV drawing mechanical data BOTTOM VIEW b CA B L bbb 0.40 E2 PIN#1 ID D2 C A ccc C A1 0.20±0.008 SIDE VIEW SEATING PLANE 0.08 C D A B E INDEX AREA aaa C TOP VIEW aaa C 8222871_Rev_B 10/13 Doc ID 022339 Rev 2 www.bdtic.com/ST STL23NM50N Package mechanical data Figure 20. PowerFLAT™ 8x8 HV recommended footprint 0.60 7.70 4.40 7.30 2.00 1.05 Footprint Doc ID 022339 Rev 2 www.bdtic.com/ST 11/13 Revision history 5 STL23NM50N Revision history Table 9. 12/13 Document revision history Date Revision Changes 10-Oct-2011 1 First release. 08-Oct-2012 2 Updated title on the cover page. Updated value for dv/dt on Table 2: Absolute maximum ratings. Document status promoted from preliminary to production data. Doc ID 022339 Rev 2 www.bdtic.com/ST STL23NM50N Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 022339 Rev 2 www.bdtic.com/ST 13/13