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Transcript
The Optical Transmitters for the LHCb L0 Calorimeter Trigger G.Avoni, G. Balbi, A. Carbone, I. D’Antone, D. Galli, I. Lax, U. Marconi and V. Vagnoni, INFN, Bologna Introduction Multi-channel Optical Transmitter Multi-channel Optical Transmitter Part 1 Part 2 Top view The L0 trigger system of LHCb is used to reduce the bunch crossing rate of LHC (40.08 MHz) to the 1 MHz rate sustainable for the High Level Trigger. Using the CRT4T as a power supply switch for the GOL Clock distributor The calorimeter system of LHCb is used to select the highest energetic clusters in the ECAL (electromagnetic calorimeters) or HCAL (hadronic calorimeters) for the L0 calorimeter trigger. NB100LVEP221FA SAMTEC 0.635 mm Hi-Speed Header QTS-125-03-L-D-A 250 pin connectors Optical Transducer HFBR772BH Pluggable package MPO connector Bottom view 1mm Signal from the auxiliary detectors SPD and Pre-Shower are used in the Validation phase to assess the cluster type. ECAL is segmented in 5952 cells (each cell is a possible cluster). Validation (determine the cluster type) is done by the PS/SPD (some geometry) to get the electron and photon candidates. Combination of the detector signal to select π0 candidates are also foreseen. Jumper to set the I2C address Meg-Array ® 100 Position Plug, 0.00 mm Stack Height, 1.27 mm x 1.27 mm ( 0.050 in. x 0.050 in.) Centerline -- FCI 84512-102 HCAL is segmented in 1484 cells (each cell is a possible cluster). Addition of the energy possibly lost in ECAL if available. The multi-channel optical transmitter board can host up to 12 optical GOL serializers. The optical transducer used is a HFBR772BH. 850 nm VCSEL array source 12 independent channels per module. Standard MTP® (MPO) ribbon fiber connector interface. 50/125 µm multimode fiber. The clock distributor is a NB100LVEP221FA. The jitter introduced is guaranteed to be less than 2ps RMS. 10m cables The optical transmitter board receives the control signals and the power from the carrier board through the SAMTEC 0.635 mm Hi-Speed Connectors. FE boards 8x4 input channels OFF/ ON GOL CRT4T Attenuation 0 dB Attenuation 3 dB Attenuation 14 dB Eye top 293.6 μW Eye top 143.3 μW Eye top 11.92 μW The GOL ASIC is packaged in a 144-pin fpBGA 13 mm side package with 1mm solder-ball pitch. The cluster energy is measured on 2x2 cells at the front-end board, from 8x8 cm2 (inner ECAL) to 52x52 cm2 (outer HCAL). L0 Calorimeter Trigger Logical Scheme Vcc BER vs. Optical Attenuation Bottom view The 32 channels front end board selects a cluster as a local maximum energy deposit. To implement the GOL power switch, two PMOS devices are used in parallel in order to reduce the “on” resistance of the switch (this reduces the voltage drop across the switch). An NMOS device is additionally used to short the GOL power to ground when the power switch is open. This device guarantees that the GOL power supply rail is pulled to ground even in the presence of active inputs. Attenuation (dB) Eye Top (μW) Time (hours) Errors (C.L.95%) 0 293.6 24 <10-13 3 143.3 24 <10-13 6 72.34 120 <10-14 9 36.12 24 <10-13 12 18.39 24 <10-13 13.9 11.92 ½ Errors observed Attenuation of the light pulses has been varied to establish the range within the transmission is errors free. Data shall go through 100m long cables and two optical patch panels The quality of the clock used to drive the GOL serializer is a critical parameter. The GOL maximum tolerable jitter value is 100 ps (peak-to-peak). The clock signal from the LHC TTC (Timing Trigger and Control) system to the GOL is distributed to the Optical Transmitter board from the Carrier Board through the connector clock pin and then distributed by the NB100LVEP221FA. The quality of the clock measured at the GOL clock pin after having passed through the entire distribution chain shows rather a good σ value of about 7 ps. LVDS connections 12x32 bits data Validation Cards Parallel Fiber GOL Control Optical links 100m fibers AGILENT 12 Ch x12 12x1.6 Gbps Connectors Selection Boards 40.08MHz Optical links 5m fibers clock Distributor Power CRT4T L1 Buffer Single-channel Optical Transmitter The clock signal used to drive the optical mezzanine presents a jitter of σ = 14.34 ps (picture on the left). The quality of the jitter at the pin clock of the GOL improves σ = 6.95 ps due a QPLL filter used in the carrier boards. BER measurements Selection Board First method: direct comparison of the transmitted and received patterns. Control Status LED Dip switch to set the GOL I2C address 40 mm BERT For the ECS (Experimental Control System) an on-board Credit Card PC has been adopted for local configuration and monitoring by interfacing with i2c buses, jtag chains and a 32-bit parallel local bus. nx32bit TOP SIDE VIEW Rx Board BOTTOM SIDE VIEW 80 mt. fiber Tektronix TLA 720 Logic Analyzer GOL 1.6 Gb/s Transmitter board nx32bit Tx Board VCSEL with SMA threaded connector GOL Controls Power from the TELL1 custom backplane 40.08MHz 80.160MHz TTCrq Tektronix CSA 7404 Scope The TTCrq contains a TTCrx, a QPLL with its associated crystal and a TrueLight pin-preamplifier VCSEL 32 data bits Connectors SAMTEC High Speed Connectors 0.635mm Hi-Speed Header QTS and QSS series Pseudo Random Pattern Sequence Generator BER To fiber Clock 40MHz Power • VCSEL Laser ULM850-05-TN USMB0P by ULM Photonics. • High speed, up to 2.5 Gbps. Inter-board communication goes through a dedicated interface and a point-to-point connector. It is used to transmit partial results from one board to another. Receiver board Xilinix FPGA Solder switch to control the VCSEL bias current, set at the production to grant optimal performance The Selection Boards receives data from the Validation Cards through the optical links. Each board is equipped with 30 optical receivers (28+2 spares). bits _ received _ in _ error total _ bits _ received BER n(bits) t 10-12 2.3·1012 30 min 10-13 2.3·1013 5h 10-14 2.3·1014 50 h ECS interface 3 channels Optical Transmitters Process FPGA To reach a sensitivity of 10-12 in measuring the transmission error probability with this technique, when no error is detected during the entire data transmission, aiming a confidence level of 90%, lasts about 30 minutes. • SMA fibre connector. Second method: eye diagram analysis • Operate on multimode fibre at wavelength of 850nm. TTCrq • The VCSEL option considered is that of 1mW @ 6mA. BER vs. Optical Attenuation Attenuation 0 dB Attenuation 9 dB Attenuation 14 dB SNR 1 BER erfc 2 2 e Q 2 2 LAN 30 channels Optical Receivers and deserializers 2 Q Top layer Q 1 0 1 0 The “Q” value has been measured with the digital scope embedded software, specifically developed by Tektronix for eye-diagram analysis. This formula returns estimated values better than 10-13. Eye top 462.8 μW Eye top 57.6 μW Attenuation (dB) Eye Top (μW) Time (hours) Errors (C.L.95%) 0 462,8 24 <10-13 3 232 24 <10-13 6 114,5 120 <10-14 9 57,6 24 <10-13 12 27,34 24 <10-13 14 18,29 24 Errors Observed Eye top 18.29 μW Attenuation of the light pulses has been varied to establish the range within the transmission is errors free. Data shall go through 100m long cables and two optical patch panels The optical attenuator used in our test is the Amphenol AFO 46946. it is an adjustable attenuator without pre-definite steps. The attenuation level can be varied by rotating a milled ring. Attenuator: Amphenol AFO 46946 The board (VME 9U standard, 2.4mm total thickness) consists in 16 layers. Temperature sensors allow monitoring of several areas of the board. Critical signals are routed differentially. Special care has been taken to improve several points: - controlled line impedance of for the clock and serial data lines; - similar length of the traces between different deserializers; - signal integrity, by minimizing crosstalk and reflections. 12th Workshop on Electronics for LHC and Future Experiments – Valencia, Spain – 25-29 September 2006