Download Thermal

Budapest University of
Technology and
Economics
Thermal-electric logic circuit:
a solution for nanoelectronics
Department of Electron Devices
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Mizsei, János
www.eet.bme.hu
Outline
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electro-thermal integrated circuit: basic concept
the MIT effect
MIT resistor as memristor
new thermal-electric device (phonsistor) and the
(CMOS compatible) thermal-electric logic circuit
(TELC)
nanosized CMOS versus TELC
analogy between neurons and TELC
some measured results (thermal OR and AND gate)
S/W analysis
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February 6, 2013
© BME Department of Electron Devices, 2012.
Electro-thermal integrated circuit: basic
concept (TCL: thermally coupled logic)
aI 2  R IN R th  U F
to switch on the next gate
U OUT  U IN
RIN
RIN
U OUT  U IN
The forward voltage of silicon diodes (p-n
junctions) decrease about a=2 mV/K at a
constant forward current The early idea for
thermal-electronic logic circuit (TELC)
operates with p-n junctions and control
resistors. Either of input resistors is heated
up, the output voltages decrease (NOR logic
function).
U 2IN
= UF  a
R th
R IN
U F  aIU F R th
I  R IN  U F
to switch on the next gate
avoid to thermal
switch on the pn
junction itself
avoid to electrical
switch on the pn
junction itself
3
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© BME Department of Electron Devices, 2010.
U F  aIU F R th
1  aIR th
I  R IN  U F
aI 2  R IN R th  U F
Contradiction!!!
I  R IN  U F
Something different
is needed, instead of
simple pn junctions!
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© BME Department of Electron Devices, 2010.
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© BME Department of Electron Devices, 2012.
Metal-Insulator-Transition (MIT) VO2 thin films:
MIT effect
Optical and electrical switching
characteristics of MIT effect induced by
Joule-heating method. Very high optical
density films with T(l)≈ 0 @ 1550 mm in
metal state(red line).
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© BME Department of Electron Devices, 2010.
MIT memristive effect
resistor: no memory, ohmic
capacitor: charge memory
inductor: current memory
memristor: charge memory, ohmic
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7
Applications
• (New) functional device by thermal
coupling (phonon coupler, phonsistor).
SeMgO2-V2 O5 , Jc-E, 88 mm/5.82 mm (Pt elect.); 509 W , step 0.2 V, delay 0.5 s
Iin
4,0E+05
Iout
SeMgO2-V2 O5 , Jc-E, 88 mm/5.82 mm (Pt elect.); 509 W , step 0.2 V, delay 0.5 s
4,0E+05
3,0E+05
Vin
-4,00E+06
-3,00E+06
-2,00E+06
0,0E+00
-1,00E+06
0,00E+00
2,0E+05
2
Current density [A/cm]
2
Current density [A/cm]
1,0E+05
-5,00E+06
3,0E+05
VinIin
2,0E+05
1,00E+06
2,00E+06
3,00E+06
4,00E+06
-1,0E+05
5,00E+06
1,0E+05
-5,00E+06
-4,00E+06
-3,00E+06
-2,00E+06
0,0E+00
-1,00E+06
0,00E+00
-1,0E+05
-2,0E+05
-2,0E+05
-3,0E+05
-3,0E+05
1,00E+06
2,00E+06
3,00E+06
4,00E+06
5,00E+06
Properties of the phonsistor:
- active device
- ohmic input and
- thyristor-like output
characteristics
- it saves the output state
-4,0E+05
Electric field [V/m]
-4,0E+05
Electric field [V/m]
Vout
Ballistic transport, thermalisation in the SMT:
Input power: P=VinIin
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© BME Department of Electron Devices, 2010.
minority carrier diffusion
Bipolar
transistor and
metal base
transistor
analogy
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© BME Department of Electron Devices, 2010.
ballistic transport of electrons
through the metal base
Applications
• New functional device by mutual thermal
coupling (reciproque phonsistor).
SeMgO2-V2 O5 , Jc-E, 88 mm/5.82 mm (Pt elect.); 509 W , step 0.2 V, delay 0.5 s
SeMgO2-V2 O5 , Jc-E, 88 mm/5.82 mm (Pt elect.); 509 W , step 0.2 V, delay 0.5 s
4,0E+05
Iin
4,0E+05
Iout
VoutIout
3,0E+05
• New functional logic cell by mixed
thermal coupling
2
Current density [A/cm]
2,0E+05
2
1,0E+05
-5,00E+06
-4,00E+06
-3,00E+06
-2,00E+06
0,0E+00
-1,00E+06
0,00E+00
1,00E+06
2,00E+06
3,00E+06
4,00E+06
-1,0E+05
5,00E+06
1,0E+05
-5,00E+06
-4,00E+06
-3,00E+06
Vin
-2,0E+05
-2,00E+06
0,0E+00
-1,00E+06
0,00E+00
-1,0E+05
-2,0E+05
-3,0E+05
-3,0E+05
-4,0E+05
-4,0E+05
3,00E+06
4,00E+06
5,00E+06
Vout
Output(s),
controlled by
input(s), but
they can
control each
other too
Output (?)
Input(s),
independent
from each
other
VO2
VO2
Input (?)
2,00E+06
Electric field [V/m]
VO2
Electric field [V/m]
1,00E+06
VO2
Current density [A/cm]
VinIin
3,0E+05
2,0E+05
Properties:
- active device (thyristor-like characteristics),
- it saves both input and output states
- symmetric (symmetry depends on size of the resistors)
- and “reciproque” (“input” can be switched on from the “output”, too) !
- the output conditions can be seen from the input side, too !
Thermally coupled logic (TCL) next slides!
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10
© BME Department of Electron Devices, 2010.
Electro-thermal integrated circuit: basic
concept (TCL: thermally coupled logic)
•OR gate:
VO2
Thermal
diffusion
length
VO2
(VO2)
Input(s)
(three input)
Output
•AND gate:
•Complex (AND OR) gate:
11
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© BME Department of Electron Devices, 2010.
Patent (phonsistor,
thermal-electric
integrated circuit)
submitted to the
Hungarian
Patent Office by the
Budapest University of
Technology and
Economics
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© BME Department of Electron Devices, 2010.
1
Thermal diffusivity:
In heat transfer analysis, thermal diffusivity (symbol: a ) is
the ratio of thermal conductivity to volumetric heat capacity.
where:
• : thermal conductivity (SI units: W/(m K) )
• : volumetric heat capacity (SI units: J/(m3K) )
• : density (SI units: kg/(m3) )
• : specific heat capacity (SI units: J/(kg K) )
Thermal diffusion length (characteristic lenght at given time scale):
Lth = at
a~106 m2/s (SiO2), time is 10-10 sec, than Lth=10-8 m (10nm)
a~6x105 m2/s (Si), time is 10-10 sec, than Lth=7x10-8 m (70nm)
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© BME Department of Electron Devices, 2010.
Electro-thermal integrated circuit: a bit
more…
Power supply
•Electrical coupling: NOR
VO2
Pull up
resistor
VO2
1
Input(s)
0 (low voltage level)
Output
SeMgO2-V2 O5 , Jc-E, 88 mm/5.82 mm (Pt elect.); 509 W , step 0.2 V, delay 0.5 s
Iout
4,0E+05
Pull up
resistor
loadline
3,0E+05
2
Current density [A/cm]
2,0E+05
1,0E+05
-5,00E+06
-4,00E+06
-3,00E+06
-2,00E+06
0,0E+00
-1,00E+06
0,00E+00
-1,0E+05
-2,0E+05
VinIin
1,00E+06
2,00E+06
3,00E+06
4,00E+06
•Thermal coupling: OR
5,00E+06
Two, stable
operating points
1 (high temperature level)
-3,0E+05
-4,0E+05
Electric field [V/m]
1
Practical realisation: vertical (three dimensional thermal
IC, possibly stacked, see more later)
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© BME Department of Electron Devices, 2010.
Electro-thermal integrated circuit: thermal
transmission line with three OR/NOR input
Power supply
Output
1
propagation of the thermal „1” state, signal regeneration
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© BME Department of Electron Devices, 2010.
Some ideas for practical realisations:
Vertical (three dimensional thermal IC), cross section:
OR
AND OR
OR
VO2
SiO2 , thermal and
electrical isolator
Cu, or
carbon
nanotubes:
thermal
ground
for thermal
separation
Thermal diffusion
length
VO2
VO2
Cu, or
carbon
nanotubes:
thermal
ground
for thermal
separation
Silicone (with conventional CMOS integrated circuit)
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© BME Department of Electron Devices, 2010.
„Nothing beats scaled silicon but nanotechnology can complement”
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© BME Department of Electron Devices, 2010.
Some ideas for practical realisations: CMOS
compatibility
Vertical (three dimensional thermal and CMOS IC), cross section:
CMOS IC
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© BME Department of Electron Devices, 2010.
Some ideas for practical realisations: real size
and scalability
ITRS (roadmap)
90 nm — 2002
65 nm — 2006
45 nm — 2008
32 nm — 2010
22 nm — 2011
16 nm — 2013
11 nm — approx.
2015
Phonsistor size:
Geometry, volume
Power
supply
voltage
Clock
frequency
Number of
components
Recent CMOS gate
properties:
(22+22)x50x50 nm, 110000 nm3
0.8-0.7 V
4 GHz
2 (“driver-loader”)
Theoretical limits (overestimated) for CMOS:
(11+11)x30x30 nm (3D) 19800 nm3
0.5 V
6 + (?) GHz
2 (“driver-loader”)
Estimated limits for
TELC:
10x10x30 nm (3D) 3000 nm3
0.4- 0.2 V
10 Ghz
1 (functional device)
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© BME Department of Electron Devices, 2010.
Problems with CMOS:
typical surface device
device limits (6 or even more interfaces)
Phonsistor:
simple bulk
device
with less number
of interfaces
scale down limits: depletion layers,
gate-tunnel current -> direct tunnel
distance: 2 nm)
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© BME Department of Electron Devices, 2010.
scale down limits:
tunnel current,
size effect on MIT
P
(power delay product), PDP: energy, related to
transfer, store or process of one bit
[J/s]
fJ
better chip cooling
aJ
one bit, two stable state
CMOS
CNT
TELC
kT
Ptd=W > kT ln2
thermodinamics
Ptdtd =DEDt  h/2p Heisenberg relation
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© BME Department of Electron Devices, 2010.
P
product for thermal electric gate
W = P = L c p DT  L
3
th
Energy for
3
MIT
MIT cMIT DT  L
3
MIT
MIT L
heating the environment + heating the MIT element itself + heat for phase transiton
where:
Lth = at
  MIT
c p cMIT
thermal diffusion length (characteristic lenght at given time
scale, SI units: m, value: ~10-8 m for 10 GHz
density of the environment (SiO2) and MIT material,
respectively, SI units: kg/(m3) , value: 2650, 4600
specific heat capacity of the environment and MIT material,
respectively, SI units: J/(kg K) 703 , 340-> 770
L
specific latent heat, SI units: J/(kg), value: 51410
LMIT
characteristic size of the MIT device, value: 10-8 m (10 nm)
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© BME Department of Electron Devices, 2010.
P
product (aJ) for thermal electric gate
W = P = L3th c p DT  L3MIT MIT cMIT DT  L3MIT MIT L
Energy for
heating the environment + heating the MIT element itself + heat for phase transiton
W = P = 19 16  236 = 271 aJ
P
product (aJ) for CNT: ~400
P
product (aJ) for CMOS: 50-500-1000
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© BME Department of Electron Devices, 2010.
Thermal electric logic circuit in the „gap”
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The “secret” of the huge performance of the human brain (after J. von
Neumann, Neumann Janos) is, that
it is analogue: higher excitation – higher response
it is digital: certain combination of excitations -> response
it is parallel: certain combination of excitations -> response
it is sequential: two (or more) subthreshold excitation
within recovery time -> response (sequential AND function)
…depending on the given job!
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© BME Department of Electron Devices, 2010.
Electro-thermal integrated circuits (systems) are:
SeMgO2-V2 O5 , Jc-E, 88 mm/5.82 mm (Pt elect.); 509 W , step 0.2 V, delay 0.5 s
Iin
Iout
4,0E+05
3,0E+05
Iin
2
Current density [A/cm]
2,0E+05
•analogue: higher excitation – higher response
1,0E+05
-5,00E+06
-4,00E+06
-3,00E+06
-2,00E+06
0,0E+00
-1,00E+06
0,00E+00
1,00E+06
2,00E+06
3,00E+06
4,00E+06
5,00E+06
-1,0E+05
-2,0E+05
-3,0E+05
-4,0E+05
Vin
Electric field [V/m]
Vout
•digital: certain combination of excitations -> response
Combination network:
(AND OR) gate
•paralel: certain combination of excitations -> response
•sequential: two or (more) subthreshold excitation
within recovery time (thermal time constant) -> response (memristor)
sequential: (AND) gate
…depending on the given job and timing!
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© BME Department of Electron Devices, 2010.
Electro-thermal integrated circuit: a bit more…
•Electrical coupling: NOR (for longer distances too)
chemical coupling (diffusion of ions)
1
0 (low voltage level)
•Thermal (diffusion) coupling: OR (for the next gate only)
1 (high temperature level)
1
electrical coupling (for longer distances too)
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Electro-thermal integrated circuit: a bit more…
gate with three inputs
chemical coupling
(diffusion of ions)
electrical coupling (for
longer distances too)
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thermal transmission line
even with an additional input
28
© BME Department of Electron Devices, 2010.
Electro-thermal integrated circuit: even more…
gate with three inputs
hormon release into the
intercellular liquid
heat emission
slow diffusion of hormons
thermal diffusion between non-contacted
gates (subsystems or systems)
chemical coupling
between noncontacted cells
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© BME Department of Electron Devices, 2010.
Electro-thermal integrated circuit: even more…
light excitation
gate with three inputs and light excited MIT
effect
retine
heat emission
different
coupling
possibilities
(thermal,
electrical,
optical): easy
communication
with other kind
of systems
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thermal diffusion between non-contacted
gates (subsystems or systems)
30
© BME Department of Electron Devices, 2010.
Experimental results: Nano-size VO2 switch-on
U2
U1
U2
off
on
1ms
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© BME Department of Electron Devices, 2010.
U1
Experimental results:
thermal – electronic
logic gates
V1
V2
V3
V4
„CLOCK”
V1in
OR
V2in
V3out
V4clock
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© BME Department of Electron Devices, 2010.
AND
Nanosized experimental TELC gate (planned)
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Nanosized experimental TELC gate (realised)
Resistance(Ohm) through nanoholes:
1.00E+07
1.00E+06
1.00E+05
1.00E+04
20.00
40.00
60.00
Temperature C
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© BME Department of Electron Devices, 2010.
80.00
100.00
SWOT
„Strength”
- extremely simple structure („bulk” resistors with common bottom
electrodes, only two interfaces)
- better tolerance against radiation
- less physical limits considering the scaling down (10nm)
- compatible with the recent IC technology
„Weaknesses”
- thermal dissipation and
- cooling and temperature stabilising (thermal management)
- a very exact and very sophisticated electro-thermal-logic simulation and
new design principles are needed for proper realisation
„Opportunities”
- easy communication with other part of systems (electrical or
thermal coupling to CMOS, optical coupling)
- technological flexibility (horizontal, vertical or mixed realisation)
- design flexibility (signal paths for all directions-> brain like
operation)
„Threats”
-
there are no data about reliability of the thermal-electric computing
the thermal transport at nm scale is still unknown field
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© BME Department of Electron Devices, 2010.
Acknowledgement
The research was partially supported by the project
No. NN 110867 of the Hungarian Scientific Research Fund
(OTKA).
Acknowledgement
is really great  to all organizers of this conference for
their excellent work and inviting me.
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Budapest University of
Technology and
Economics
Thank You for your attention!
Department of Electron Devices
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