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CHAPTER 5 FIELD EFFECT TRANSISTORS(part b) (FETs) JFET Biasing Just as we learned that the bipolar junction transistor must be biased for proper operation, the JFET too must be biased for operation. Let’s look at some of the methods for biasing JFETs. In most cases the ideal Q-point will be the middle of the transfer characteristic curve which is about half of the IDSS. JFET ID IDSS (1 I D = IS IG 0 A VGS 2 ) VP BJT IC = IB IC IE VBE 0.7 V 2 JFET Biasing, Self- Bias Configuration Most common type of JFET bias. Eliminates the need for two dc supplies. The controlling gate-to-source is determined by the voltage across a resistor RS. For analysis, resistor RG replaced by a short circuit equivalent since IG = 0 A. 3 JFET Biasing, Self- Bias Configuration Voltage drop across source resistor, RS VRS = ISRS; since IS = ID then VRS = IDRS For indicated closed loop in the Figure 7.9 -VGS – VRS = 0 VGS = - VRS VGS = -IDRS Drain current, ID: Fig. 7.9 DC analysis of the self-bias configuration. 4 I D I DSS (1 VGS 2 ) VP I D I DSS (1 I D RS 2 ) VP I D I DSS (1 I D RS 2 ) VP JFET Biasing, Self- Bias Configuration Voltage between drain-to-source, VDS VDD – IDRD – VDS – ISRS = 0 Since IS = ID VDD – IDRD – VDS – IDRS = 0 VDS = VDD – ID(RD + RS) OR VDS = VD – VS VS = ISRS and VD = VDD – IDRD Fig. 7.9 DC analysis of the self-bias configuration. 5 Voltage between gate-to-source, VGS VGS = VG – VS; Since VG = 0 VGS = -VS and VS = ISRS Then VGS = - ISRS JFET Biasing, Self- Bias Configuration The value of RS needed to establish the computed VGS can be determined by the previously discussed relationship below. RS = | VGS/ID | The value of RD needed can be determined by taking half of VDD and dividing it by ID. RD = (VDD/2)/ID 6 JFET Biasing, Self- Bias Configuration Remember the purpose of biasing is to set a point of operation (Qpoint). In a self-biasing type JFET circuit the Q-point is determined by the given parameters of the JFET itself and values of RS and RD. Setting it at midpoint on the drain curve is most common. One thing not mentioned in the discussion was RG. It’s value is arbitrary but it should be large enough to keep the input resistance high. 7 Summary Self-Bias JFET must be operated that gate-source junction is always reverse-biased. VG=0V 8 Summary Self-Bias i. ii. iii. iv. v. 9 Since VG = 0V, IG = 0A IS = ID VS = IDRS VGS = VG – VS = 0 – IDRS = -IDRS VD = VDD – IDRD VDS = VD – VS = VDD – ID(RD + RS) Summary Self-Bias • • Rs is needed to establish VGS ID can be determined from : i. Transfer characteristic curve ii. Formula, by using IDSS and VGS(off) given in datasheet V I D I DSS 1 GS VP 2 Example : Self-Bias Find VDS and VGS . VDD=15V, ID = 5mA, RD = 1.0kΩ, RS=220Ω dan RG=10MΩ. Example : Self-Bias Find VDS and VGS . VDD=12V, ID = 8mA, RD = 860Ω, RS=390Ω. Example : Self-Bias Determine the value of RS required to self-bias an n channel JFET has the transfer characteristic curve shown in Figure below. IDSS=25mA,VGS = -3V and VGS(off) = -10V Example : Self-Bias Determine the value of RS required to self-bias an p channel with datasheet values IDSS=18mA, VGS = 4V and VGS(off) = 8V JFET Biasing, Fixed- Bias Configuration IG = 0 so VRG = IGRG = (0 A)RG = 0 then RG can be removed from the circuit. RG only need in ac analysis through the input Vi - VGG – VGS = 0 15 VGS = - VGG JFET Biasing, Fixed- Bias Configuration Drain-to-source voltage can be determined by applying Kirchoff’s voltage law VDS + IDRD –VDD = 0 VDS = VDD – IDRD Source voltage to ground; VS = 0 Drain-to-source voltage can also be determined through; VDS = VD – VS but VS = 0 then VDS = VD Fig. 7.5 Measuring the quiescent values of ID and VGS. 16 Gate-to-source voltage VGS = VG – VS ; since VS = 0 VGS = VG Summary Fixed- Bias CIRCUIT RECOGNITION Since the configuration requires two dc supply,VGG and VDD DISADVANTAGE limited and not included in the list of common FET configurations. JFET Biasing, Voltage-Divider Configuration The basic construction exactly the same with BJT, but the dc analysis quite different with IG = 0 for FET The voltage at source, VS must be more positive than the voltage at the gate, VG in order to keep gatesource junction reverse-biased. 18 JFET Biasing, Voltage-Divider Configuration Gate-to-source analysis VG ( R2 )VDD R1 R2 VS = IDRS Gate-to-source voltage; VGS = VG – VS And source voltage is VS = VG – VGS The drain current can be expressed as ID 19 VS VG VGS RS RS JFET Biasing, Voltage-Divider Configuration Drain-to-source analysis VDS = VDD – ID(RD + RS) VD = VDD – IDRD VS = IDRS I R1 I R 2 20 VDD R1 R2 Example Given the drain to ground voltage is 5V,VDD = 9V, RD=4.7k,RS=3.3k,R1=10M and R2=2.2M. Determine the Q-point of the circuit.