Download Dynamic Gate - Washington State University

EE 466/586
VLSI Design
Partha Pande
School of EECS
Washington State University
[email protected]
Lecture 15
Dynamic Logic
Dynamic CMOS

In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type)
devices

Dynamic circuits rely on the temporary
storage of signal values on the capacitance of
high impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type)
transistors
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
Clk
CL
PDN
A
C
B
Me
Clk
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
1
Out
((AB)+C)
off
Me on
Conditions on Output




Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
Inputs to the gate can make at most one transition
during evaluation.
Output can be in the high impedance state during
and after evaluation (PDN off), state is stored on CL
This behavior is fundamentally different than the
static counterpart that always has a low resistance
path between the output and one of the power rails.
Properties of Dynamic Gates

Logic function is implemented by the PDN only
 number of transistors is N + 2 (versus 2N for static complementary
CMOS)



Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect the logic
levels
Faster switching speeds
 reduced load capacitance due to lower input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 no Isc, so all the current provided by PDN goes into discharging CL
Properties of Dynamic Gates

Overall power dissipation usually higher than static
CMOS





no static current path ever exists between VDD and GND
no glitching
higher transition probabilities
extra load on Clk
Needs a precharge/evaluate clock
Issues in Dynamic Design 1: Charge
Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Me
Evaluate
VOut
Precharge
Leakage sources
leakage sources are reverse-biased diode and the sub-threshold leakage of
the NMOS pull down device.
Solution to Charge Leakage
Keeper
Clk
Mp
A
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic
During precharge, Out is VDD and inverter out is GND,
so keeper is on
Issues in Dynamic Design 2: Charge
Sharing
Clk
Mp
Out
A
CL
B=0
Clk
CA
Me
CB
Charge stored originally on
CL is redistributed (shared)
over CL and CA leading to
reduced robustness
CA initially discharged and
CL fully charged
Charge Sharing
VDD
case 1) if V out < VTn
VDD
Clk

Mp
Mp
Out
Out
CL
A
A
==
BB
00
Clk 
CL
Ma
Ma
M
Mb
b
Mee
M
XX
a
CC
a
CC
bb
C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
or
Ca
V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
CL
case 2) if V out > VTn
Ca 
 ---------------------
Vout = –V DD 
C
+
C
 a
L
Charge Sharing Example
Clk
A
A
B
B
B
Cc=15fF
C
C
Ca=15fF
Clk
Out
CL=50fF
!B
Cb=15fF
Cd=10fF
Solution to Charge Redistribution
Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor
(at the cost of increased area and power)
Issues in Dynamic Design 3: Clock
Feedthrough
Clk
Mp
A
CL
B
Clk
Out
Me
Coupling between Out and
Clk input of the precharge
device due to the gate to
drain capacitance. So
voltage of Out can rise
above VDD. The fast rising
(and falling edges) of the
clock couple to Out.
Clock Feedthrough
Clock feedthrough
Clk
Out
2.5
In1
In2
1.5
In3
In &
Clk
0.5
In4
Clk
Out
-0.5
0
0.5
Time, ns
1
Clock feedthrough
Cascading Dynamic Gates
V
Clk
Mp
Clk
Mp
Out1
Me
Clk
Out2
In
In
Clk
Clk
Me
Out1
VTn
V
Out2
t
Only 0  1 transitions allowed at inputs!
Cascading Dynamic Gates




Out2 should remain at VDD since Out1 transitions to 0
during evaluation. However, since there is a finite
propagation delay for the input to discharge Out1 to
GND, the second output also starts to discharge.
The second dynamic inverter turns off (PDN) when
Out1 reaches VTn.
Setting all inputs of the second gate to 0 during
precharge will fix it.
Correct operation is guaranteed (ignoring charge
redistribution and leakage) as long as the inputs can
only make a single 0 -> 1 transition during the
evaluation period
Domino Logic
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
Out2
00
01
In4
In5
Clk
PDN
Me
Ensures all inputs to the Domino gate are set to 0 at the end of the precharge
period. Hence, the only possible transition during evaluation is 0 -> 1
Why Domino?
Clk
Ini
Inj
Clk
PDN
Ini
Inj
PDN
Ini
Inj
PDN
Like falling dominos!
Ini
Inj
PDN
Designing with Domino Logic
VDD
VDD
VDD
Clk
Mp
Clk
Mp
Out1
Mr
Out2
In1
In2
In3
PDN
PDN
In4
Can be eliminated!
Clk
Me
Clk
Inputs = 0
during precharge
Me
Footless Domino
VDD
Clk
VDD
Mp
Clk
Mp
Out1
0
0
Clk
Mp
Out2
1
0
In1
1
VDD
Outn
1
0
In2
1
0
In3
1
0
The first gate in the chain needs a foot switch
Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage
Inn
1
0
1
np-CMOS
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Me
In4
In5
PUN
00
01
Clk
Out2
Mp
Only 0  1 transitions allowed at inputs of PDN
Only 1  0 transitions allowed at inputs of PUN
Properties of Domino Logic
Only non-inverting logic can be implemented
 Very high speed

 static inverter can be skewed, only L-H transition
 Input capacitance reduced
Differential (Dual Rail) Domino
off
Mp Mkp
Clk
Out = AB
1
on
Mkp
0
Clk
Mp
1
A
!A
0
!B
B
Clk
Me
Solves the problem of non-inverting logic
Out = AB
Take Home Exercise
 Design
a dual-rail XOR/XNOR domino
gate and share as many transistors as
possible between the true and
complement logic blocks