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High Performance MOS Current Mode Logic Circuits
Saied Hemati
Ph.D. Candidate
Ottawa-Carleton Institute for Electrical & Computer Engineering
(OCIECE)
Carleton University
Ottawa, Canada
Outline
 Introduction
 CML versus VML
 Different types of CML
- ECL
- CSL
- MCML
- DyCML
- Feedback MCML
 A 10-Gbps MUX/DeMUX
 Conclusion
Motivations for new logic styles:
- Higher speed.
- Lower power consumption.
- Lower area consumption.
- Lower fabrication cost.
- Higher robustness (environment noise , fabrication fluctuations, …).
- Low noise operation.
- Lower complexity (design, optimization, test,…).
What is wrong with CMOS?
1- It is not suitable for high speed applications.
- Turn off time and turn on time limit the maximum speed.
- Power consumption increases by frequency.
- Each input at least is connected to two gates.
- P-type devices play a key role in CMOS.
- Voltage swing is too large.
- Rate of charging and discharging is not constant.
2- High dynamic power dissipation.
- Large swing voltage.
- Large supply voltage and threshold voltage.
What
isis
Wrong
With
CMOS?
What
is Wrong
With
CMOS?
What
Wrong
With
CMOS?
What
isis
Wrong
With
CMOS?
What
Wrong
With
CMOS?
3- CMOS produces lots of noise.
- Sharp switching currents.
- Voltage variation.
CMOS
4- CMOS suffers from low robustness.
- Propagation delay varies with supply voltage.
- Propagation delay varies with threshold voltage (80%).
- Noise can degrade the performance.
5- CMOS consumes too much area.
- Pull up network.
6- Low degree of freedom in optimization.
1963
201X
Current Mode Logic
1- Transistors are always on (fully or partially).
- Higher speed
- Low threshold devices can be used.
- Lower Vdd .
out
R1
R2
Inputs
- Lower power dissipation.
- Static power dissipation.
I
out
Current Mode Logic
2- Swing voltage is small.
- Higher speed
- Lower dynamic power dissipation.
- Lower noise generation .
out
R1
R2
Inputs
- Lower noise margin.
3- Gates are based on n-type differential pair.
- Immunity to common mode noise (supply bounce).
- Smaller input capacitance.
- Transistors should be identical.
I
out
Current Mode Logic
4- Gates draw a static amount of current from
power supply.
- Reduces the amount of spiking of the supply
and substrate voltages (lower noise).
out
R1
R2
- Rate of charging and discharging is constant.Inputs
CV
, Power  p  Vdd I
I
C 2Vdd V 2
E  p  CVdd V , E 
I
- Higher level of freedom.
delay  
- Static power consumption.
I
out
Current Mode Logic
5- P-type devices are never used as switch.
- Higher speed.
out
- Lower number of transistors.
6- Pull up resistors are expensive.
R1
R2
Inputs
7- Suitable power down techniques
should be found.
8- The matching of fall and rise delays is
not easy.
I
out
Emitter Coupled Logic (ECL)
ECL is the fastest known logic family for silicon integrated
circuits.
ECL gates consists of :
- differential amplifier.
Rl
A+B
A
R2
B
Vref
A+B
- temperature and voltage
compensated bias network.
VEE Vcs
Vref=-1.25V
- Emitter follower output.
VEE
VOH= -0.85V
VOL= -1.75V
ECL NOR/ OR
VEE
Emitter Coupled Logic (ECL)
Chip Technology in top500 supercomputers
Current Steering Logic (CSL)
Vdd
Ibias
A simple current mode logic with
shortened swing voltage.
VOH = VT + Veff
VOL  Veff
Vref
Vout
A
B
C
D
A 4-input CSL NOR
MOS Current Mode Logic (MCML)
Inputs and outputs are differential.
Buffer and Inverter gates are the same.
RFP
Nor/Or/And/Nand gates are the same.
out
Mux/Xor gates are similar.
A
out
A
RFN
Buffer/ Inverter
MOS Current Mode Logic (MCML)
RFP
out
out
B
B
B
A
A
RFN
RFP
Out(out)
Out(out)
B(B)
B (B)
A(A)
A(A)
RFN
Xor
And/ Nand (Or/Nor)
MOS Current Mode Logic (MCML)
70
60
Energy-Delay (pJ*ps)
Energy-delay (pJ*ps)
2.5
MCML XOR3
CMOS XOR3
CMOS
MCML
2
1.5
50
40
30
20
1
0
200
400
600
800
Delay (ps)
Energy-Delay vs. Delay for
MCML and CMOS Inverters
1000
10
0
500 1000 1500 2000 2500 3000
Delay (ps)
Energy-Delay vs. Delay for
MCML and CMOS XOR3
MOS Current Mode Logic (MCML)
RFP
out
Vdd- Vswing
+
out
Vdd
RFN
Dynamic Current Mode Logic (DyCML)
Current source and load resistors
Vdd
have been redesigned.
This configuration is similar
CLK
to differential cascode voltage swing
logic (DCVSL).
Inputs
Vdd
CLK
out
out
MCML Circuit
CLK
CLK
Feedback MOS Current Mode Logic
Threshold voltage fluctuation in short channel devices degrade
matching between transistors in CML circuits.
Vth fluctuation is due to fluctuation in fabrication process :
- gate-oxide thickness.
- channel length.
- Random placement of the channel dopants.
.
.
Negative feedback can be used to improve robustness.
Feedback MOS Current Mode Logic
out
out
A
A
RFN
Buffer/ Inverter
Feedback MOS Current Mode Logic
For a first order system, gain-bandwidth is constant and feedback
decreases gain and consequently increases bandwidth.
Sensitivity of the circuit to transistor mismatch decreases too.
Feedback MOS Current Mode Logic
D_Type
flip-flop
out
out
A
A
CLK
RFN
CLK
Feedback MOS Current Mode Logic
A 10 Gb/s1:2 DeMux
Master
Slave
Master
D
D
Q
D
Q
D
Q
Q0
D
D
Q
D
Q
D
Q
Q0
CLK CLK
CLK CLK
CLK CLK
Slave
Master
D
Q
D
Q
Q1
D
Q
D
Q
Q1
CLK CLK
CLK
CLK
CLK CLK
Feedback MOS Current Mode Logic
Power-delay product for different approaches
Conclusion:
 Current mode logic is attractive because of:
- high speed.
- Energy-delay product can be optimized by designer.
- immunity against noise.
- quiet logic family.
- suitable for low voltage applications.
 Optimization of CML circuits is challenging and need more
research.
References:
 N. S. Pickles, M. C. Lefebvre,“ ECL I/O buffers for BiCMOS integrated systems: a
tutorial overview,” IEEE Trans. Education, vol. 40, No. 4, pp.229-241, Nov. 1997.
 H. Ng, D. Allost, “ CMOS current steering logic for low-voltage mixed-signal
integrated circuits,” IEEE Trans. VLSI Systems, Vol. 5, No. 3, pp.301-308, Sept. 1997.
 J. Musicer, An Analysis of MOS Current Mode Logic for Low Power and High
Performance Digital Logic, M.Sc. Thesis, University of California, Berkeley, 2000.
 M.W. Allam, M. I. Elmasry, “ Dynamic current mode logic (DyMCL): A new lowpower high performance logic style,” IEEE J. Solid State Circuits, Vol. 36, No. 3, pp.
550-558, March. 2001.
 A. Tanabe, et al ,“ 0.18u CMOS 10Gb/s Multiplexer/Demultiplexer ICs using
current mode logic with tolerance to threshold voltage fluctuation,” IEEE J. Solid
State Circuits, Vol. 36, No. 6, pp. 988-996, June. 2001.