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Transcript
Use of Data Analysis and TCAD Simulations to Understand the Characteristics and Reliability of High Voltage MOS Transistors Jone F. Chen Department of Electrical Engineering and Institute of Microelectronics, National Cheng Kung University, Tainan, Taiwan Purpose • High voltage metal-oxide-semiconductor (MOS) transistors are widely used in smart power management integrated circuits (IC), liquid-crystal display (LCD) drivers, and NAND flash memory periphery circuitry because of the compatibility to be integrated into standard complementary metal-oxidesemiconductor (CMOS) process. • Since high voltage MOS transistors are operated under high voltage, breakdown voltage (VBD) is a critical device parameter and hot-carrier induced device degradation is an important reliability concern. • This work reports analysis of VBD and hot-carrier induced device degradation in high voltage MOS transistors with varied process in drift region. 2 Outline • Off-state Breakdown • Hot-carrier Induced Degradation • TCAD Simulations • Device Description • Results and Discussions • Conclusions 3 Off-state Breakdown • High E-field in the junction causes electron/hole pair generation. This avalanche multiplication results in breakdown. 4 Hot-carrier Induced Degradation • Carriers accelerate in high E-field region and gain sufficient energy to create damage in gate oxide or oxide/Si interface, degrading device characteristics. 6 5 Fresh Stressed Id (mA) 4 3 2 1 0 0.0 0.4 0.8 1.2 Vd (V) 1.6 2.0 5 Hot-carrier Stress Procedure • Stressing were carried out at high drain voltage and interrupted periodically to measure ID degradation. 6 Technology Computer-Aided Design (TCAD) Simulations About TCAD TCAD combines two kinds of tools: Core tools in charge of running different parts of simulations. Interactive tools are which users manage their settings. ATHENA DeckBuild Structure File Command File ATLAS Device Simulator Runtime Output Log Files Solution Files TonyPlot Visualization Tool 7 Device Description • High voltage MOS transistors were fabricated by an advanced CMOS compatible process. The length of gate and N- drift region are 2 mm and 1.2 mm, respectively. • Four devices (A, B, C, D) were fabricated. A is the control device. B, C, D are implanted with BF2 with low, medium, and high doping levels in N- drift region. 8 Net Doping • Device D has less net doping due to BF2 implant in drift region. A D 9 VBD Results • Device D has the highest VBD. Higher BF2 implant dosage results in higher VBD . 10 VBD Analysis • TCAD simulations suggest that higher VBD in device D is due to the absence of high E-field in drift region. A D 11 Hot-carrier Stress Results • Device D has the greatest ID degradation. Higher BF2 implant dosage results in higher ID degradation. 12 Hot-carrier Stress Analysis • TCAD simulations show that the current-flow path in device D is closer to Si-SiO2 interface. The effect of hotcarrier induced damage on ID degradation is greater, leading to enhanced ID degradation in device D. A D 13 Conclusions • BF2 implant in drift region of high voltage MOS transistors results in higher VBD. • BF2 implant in drift region of high voltage MOS transistors enhances hot-carrier induced device degradation. • Care should be taken in determining drift region process because a trade-off between VBD and hot-carrier induced device degradation is observed. 14 Thank you for your Attention